Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 4S)

Test 1: uops

Code:

  ld1 { v0.4s, v1.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)09l2 tlb miss instruction (0a)0e191e1f223a3f43464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafb5bbl1d cache miss ld nonspec (bf)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)f5f6f7f8fd
6200529436220024120106004655288170002428520002000200010025516048286532933031020002000200029254291061161001100010000200006200000020006201290592256898306497720578305038181156502835816266137031567720002932129155292242928829306
6200429320219022018003014578286910202425120002000200010004516026285222925031020002000200029140291191161001100010001200006200001220006061288292656842304595320539310338131563592836415444136051553820002931129220293082918829240
6200429225219020018000004572288390202423520002000200010000516032286732919031020002000200029133290501161001100010000200000200200220004001284892156835306015552052331503817856572842215964136101518320002933929429293572926929280
6200429356220023018004004625288730022422920002000200010000916032286432923931020002000200029093291541161001100010000200006200000020004041300992987050325286020566314938171256572842816277135991551920002933929359293112923029208
62004293342200220210020046182882200224261200020002000100007160352871529228310200020002000291032909511610011000100002000002002000200052412847947768503055105920575312638141655592833315585135291552820002935429211293012931129384
62004292922200210230060045632883700024204200020002000100003160442888629305310200020002000291032908511610011000100002000002002002200042012965926268933105115620630314438111360562831916230136531558920002932829386292462926429327
6200429333219021014008004610288020202420720002000200010000616040285482934331020002000200029134291101161001100010000200004200000020006041297992186861309175420542306238161360552839916205135141545020002934629242292332930029200
6200429185219028022000014612287220002405220002000200010000216045285302931831020002000200029068291341161001100010000200000200001020000161306795086828309095520550309638111654542831916185136031557420002927629266293462933129135
6200429320219020020003014621287460002420620002000200010000716044288512921531020002000200029143291461161001100010000200004200300020024041289992606856310586120566307338161955582841316026136941552820002935329255293302933829315
62004293202190180220000046512882200224211200020002000100003160452863829256310200020002000290732907911610011000100002000002000000200202412922931568243051126420691320338151261522850615955137981546420002927729270294142921329342

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s, v1.4s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)0309l2 tlb miss data (0b)0e0f18191e1f22243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5bbl1d cache miss ld nonspec (bf)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
6020512005789910100060001120040967201097442570103401021000120000301001000020000104270915733436346562601200271201101200771121486112489601003020320004100016020620004100011200551200511150201100991004010010000100000100200002200001020000202321011612119824400021410132000040100120056120056120052120056120036
60204120051899000000000001200409672010974025701004010210001200003010010000200001042709157326663465626012003112051312003811213931125136010030200201921000060200200001000012003512005111502011009910040100100001000011002000002000013200002023210116121198084000201092000040100120056120056120036120056120036
602041200558990001000000112002096716109744257010040102100012000030100100002000010425228573266634651560120035120051120122112143311249360100302002000010000602002000010000120051120035115020110099100401001000010000010020000220000002000000232102161111982840000100132000040100120052120052120052120036120052
6020412005589900000020001120036967211097242570103401021000120000301001000020000104270915733628346515601200311200351201441121393112513601003020020000100006020020000100001200551200351150201100991004010010000100000100200000200000020000202321011622119808400021414132000040100120056120036120052120036120056
6020412005589900000020000120020967201097242570103401021000120000301001000020000104270915733436346562601200111200511200761121443112517601003020020000100006020020000100001200551200511150201100991004010010000100000100200000200001020000200321011611119828400021414132000040100120036120036120056120056120056
602041200358990000008000112004096720109724257010040102100002000030100100002000010427091573362834656260120031120035120177112143311251360100302002000010000602002000010000120055120051115020110099100401001000010000010020000020000002000020232101161111982840002101402000040100120056120056120036120056120036
602041200558990000000000112004094808109744257010040102100012000030100100002000010427091573362834651560120011120051120302112132311249360100302002006410000602002000010000120055120051115020110099100401001000010000010020000020000002000020232102161211982840002100132000040100120036120056120036120056120056
602041200518990000002010112003696720109740257010340102100012000030100100002000010427091573266634656260120031120051120116112139311251360100302002000010000602002000010000120055120035115020110099100401001000010000010020000220000002000000032101161211982440002140132000040100120036120052120052120056120056
602041200558990000002001011200369740310974425701034010210001200003010010000200001042674357336283465156012003112005112012511213931124936010030200200001000060200200001000012005112005111502011009910040100100001000001002000022000000200002023210216121198084000201402000040100120056120056120056120083120056
602041200558990000000000012002097403109740257010340102100002000030100100002000010427091573266634656260120027120035120106112139311249360100302002000010000602002000010000120035120051115020110099100401001000010000010020000020000002000020032102162111982840002014132000040100120056120056120036120036120056

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f43494d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
600251200558990000000201000120040209663310973625700164001210001200003001010000200001042502657330523465118012002312004312004711215831125276001030020200001000060020200001000012004712005511500211091040010100001000001020000042000200220002222000314061635119830400046602000040010120048120044120056120044120048
6002412004390000000002000001200280096633109736257001340014100022000030010100002000010425722573305234651181120031120043120047112166311252760010300202000010000600202000010000120043120082115002110910400101000010000010200000220002800220002222000314041634119830400046052000040010120056120056120044120044120104
6002412004790000000002000001200282096633109744257001340012100022001630010100302000010424678573305234651180120019120055120043112166311253560010300202000010000602162000010000120047120047115002110910400101000010000010200000220002860520002220000314031635119831400020652000040010120048120056120048120048120100
600241200558990100000201000120043009664510974442700164001210002200003001010000200001042467857336283465118012003112005512004311215831125236001030020200001000060020200001000012005512004311500211091040010100001000001020000002000000220000220000314041655119818400026652000040010120044120044120056120056120048
600241200439000100000201000120028009663310973625700134001210001200003001010000200001042467857330523465118012003112004312005511216631125366001030020200001000060020200001000012005512005511500211091040010100001000001020000022000000220002020000314041643119830400326602000040010120044120044120056120044120048
600241200559000000000201000120028209664510974425700164001210002200003001010000200001042502657332443465234112002312004312004711215831125276001030020200001000060020200001000012005512004711500211091040010100001000001020000002000200220002022000314041644119822400026652000040010120044120044120044120044120120
600241200438990001000201000120032029664510973225700164001210001200003001010000200001042502657330523465234012003112008712004311215831125276001030020200001000060020200001000012004312004311500211091040010100001000001020000022000200220002220000314031644119822400026652000040010120048120044120048120044120048
60024120043899000000020100112002820966451097442570013400121000120016300101000020000104250265733244346546601200621200551200471121543112527600103002020000100006002020000100001200431200431150021109104001010000100000102000002200061150220002020000314031653119818400020652000040010120044120044120056120044120048
60024120047899010000011000001200322096633109732257001340012100012000030010100002000010425890573329234652340120031120055120055112158311253560010300202000010000600202000010000120055120043115002110910400101000010000010200000020000880220000020000314051655119822400020602000040010120048120044120056120056120048
600241200559000000000200000120040009663710973225700134001210001200003001010000200001042467857336283465466112003112004312005511215431125236001030020200001000060020200001000012005012005611500211091040010100001000001020000022000000020000220000314031655119830400020052000040010120056120056120044120056120048

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s, v1.4s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)c2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
60205120051899000110020100012003696716109724257010340102100012000030100100002000010426743573343634656263112002712005112005111213931125116010030200200001000060200200001000012005112003511502011009910040100100001000011002000002200000020000200032101161111980840000101002000040100120036120052120052120052120052
6020412005189900000002010001200209671610974125701004010210001200003010010000200001042522857334363465626011200111200511200511121393112493601003020020000100006020020000100001200511200351150201100991004010010000100000100200000220000002000020003210116111198244000210002000040100120052120052120052120052120052
602041200519000000000651010001200209671610974025701034010210001200003010010000200001042674357334363465626011200271200801200881121393112509601003020020000100006020020000100001200511200511150201100991004010010000100000100200000220000032000022003210116111198084000210092000040100120052120052120052120052120052
60204120051899000000020100012002097403109740257010340102100002000030100100002000010426743573343634651560112002712005112003511213931125096010030200200001000060200200001000012005112005111502011009910040100100001000011002000002200000020000220032101161111982440002101092000040100120054120055120036120052120055
60204120051899000000020000012002096716109740257010340102100012000030100100002000010426743573266634656260112002712005112005111213931125096010030200200001000060200200001000012005112005211502011009910040100100001000011002000002200000020000220032101161111982440002101002000040100120052120052120052120036120036
6020412005189900000002010001200369671610974025701034010210001200003010010000200001042674357334363465626011200111200511200541121393112509601003020020000100006020020000100001200511200511150201100991004010010000100000100200000220000002000022003210116111198244000010092000040100120052120052120052120052120052
60204120051899000000020010012003696716109740257010340102100012000030100100002000010426743573343634656260112002712005112005111213931125096010030200200001000060200200001000012005112005111502011009910040100100001000001002000002200000020000200032101161111982440002101092000040100120036120036120052120052120036
602041200518990000000200100120036967171097402570103401001000120000301001000020000104267435733436346562601120011120051120035112123311250960100302002000010000602002000010000120035120035115020110099100401001000010000010020000022000003620000220032101161111982440002101092000040100120052120036120052120036120052
60204120051899000000000010012002097403109724257010340102100012000030100100002000010425228573343634656260112002712003512005111212331125096010030200200001000060200200001006412005112005111502021009910040100100001000001002000000200000320000220032101161111982440002101092000040100120052120052120052120036120052
6020412005189900000002001001200369740310972425701034010010001200003010010000200001042674357326663465626011200271200511200511121233112510601003020020000100006039220000100001200351200521150201100991004010010000100001100200000220000002000022003210116111198244000201092000040100120052120036120052120052120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)03l1i tlb fill (04)090e0f1e22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)branch cond mispred nonspec (c5)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
60025120047899100001011200209663710973625700294003010001200003001010000200001042502657326663465234120012120047120047112158311252760010300202000010000600202000010000120035120047115002110910400101000010000010200000220000002000022031420161601013119822400026652000040010120048120048120048120048120048
60024120047899100021011200329663710973625700104001210001200003001010000200001042502657332443465234120023120047120047112146311252760010300202000010000600202000010000120035120047115002110910400101000010000010200000220000002000000031420131601416119855400020602000040010120048120048120048120048120048
60024120047899100021011200329663710973625700134001010001200003001010000200001042502657332443465234120023120047120047112158311252760010300202000010000600202000010000120047120047115002110910400101000010000010200000220000002000022031420131601218119822400006652000040010120048120036120048120048120048
60024120092899100021011200329663710973625700134001210001200003001010000200001042502657332443465234120011120047120047112158311251560010300202000010000600202000010000120035120047115002110910400101000010000010200000220000032000020031420121601315119810400020602000040010120051120048120036120048120048
60024120047899100021011200209663710973625700134001210001200003001010000200001042397457332443465234120023120047120047112158311251560010300202000010000600202000010000120047120035115002110910400101000010000010200000220000002000022031420151601318119822400026652000040010120048120048120048120036120048
60024120048899100121011200329663710973625700134001210001200003001010000200521042502657332443465234120023120047120047112158311251560010300202000010000600202000010000120038120047115002110910400101000010000010200000220000002000022031420151601514119810400026652000040010120086120048120048120048120048
600241200358991000210112003296637109736257001040012100012000030010100002000010425026573324434648801200231200471200471121583112527600103002020000100006002020000100001200471200471150021109104001010000100000102000002200000182000022031440141601814119810400026602000040010120048120048120048120036120036
600241200478991001110011200329663710972425700134001210001200003001010000200001042397457332443465234120011120047120047112158311252760010300202000010000600202000010000120047120047115002110910400101000010000010200000220000002000022031420121601215119822400026652000040010120048120048120048120048120048
60024120035899100021011200209397510973625700134001010001200003001010000200001042502657326663465234120023120047120047112158311251560010300202000010000600202000010000120035120047115002110910400101000010000010200000220000002000022031440131601116119810400026652000040010120048120036120048120048120048
60024120047899110060011200329663710973625700134001210001200003001010000200001042502657332443465234120167120047120047112158311252760010300202000010000600202000010000120094120047215002110910400101000010000010200000020000002000022031420161601313119822400026652000040010120048120048120048120039120048

Test 4: throughput

Count: 8

Code:

  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)92inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1602055340740011000811025339137720251601001001600001001600005002339919053378534065340233325333360160100200160000200160000534025340711802011009901001008000080000110016002119431600581232611600006059018151101161153400131351600001005340753386534035340753423
1602045340239910101821035336607019251601001001600001001600005002334815053368534045338233326333366160100200160000200160000535585340911802011009901001008000080000010016001919016005803060160039605901905110116115339913051600001005340453404534035340353503
16020453381400101009110353388077192516010010016000010016000050023399190533575340253402333253333601601002001600002001600005340353402118020110099010010080000800000100160020204316005810221160000601943190511011611533990051600001005340353404534045349153382
160204534034001100067002533672971925160100100160390100160000500232668305337853381534033332633336016010020016000020016000053382534021180201100990100100800008000001001600191943160060012611600406159431925110116115339901351600001005340453403534035340353411
16020453403400100006610353388270192516010010016000010016000050023335440533785340253403333043333601601002001600002001600005340353402118020110099010010080000800000100160019204316005813061160040615801915110116115337913051600001005340453403534035340353411
160204533814001101085003533883702125160100100160000100160000500233354405337853421533843330433336016010020016000020016000053403534021180201100990100100800008000001001600202143160058121641600406159431905110116115340001351600001005340353403534045340453413
160204534024001010021103533873002025160100100160000100160000500232235505337753403534023330433336116010020016000020016000053402534031180201100990100100800008000001001600202043160058120211600406159019151101161153399131351600001005340353403534035340453411
160204534054001110067103533663072025160243100160000100160000500233481505337753402534033332633336116010020016000020016000053403534021180201100990100100800008000001001600202001600591106416004060194519151101161153399131351600001005338253403534045338253395
16020453402400110006710353391377129251606201001600001001600005002333373053356534025340333326333360160100200160000200160000534035340211802011009901001008000080000010016002020431600580306016003961194319051101161153378131351600001005341553417534035340353413
16020453403399111117410353387397182516010010016000010016000050023433060533565340253403333033333611601002001600002001600005340253381118020110099010010080000800001100160019204316005911061160000605901915110116115340013001600001005338253404534045340353412

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6674

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0e0f181e1f22243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)a5ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
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