Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 8B)

Test 1: uops

Code:

  ld1 { v0.8b, v1.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)0e0f1e22243a3f464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
62005285392141100000141052292812700234581000100010005000200160852818428470310100020001000282672842111610011000100001000010010041000212139861027572393476052199143315382110403728040145281239913684100010002829228246284402837628433
6200428617214000000021050652819801234031000100010005000400160842810728473310100020001000285002846711610011000100001000210000001001211138531029971563382044196893397382011433528057147021242713699100010002845828517284242853528415
6200428251213100000031050022831410234211000100010005000000160832809228471310100020021000284172822611610011000100001000010000001000000140011012368603348141196863400382116403727999143001249813964100010002839028580283482842328360
620042850721400000000105172280940123379100010001000500050016083280872843131010002000100028211283201161001100010000100021001000100020213764993372243409035197553441382012424228087142471241313933100010002831328474284662840328388
6200428625213000000000051382823501235351000100010005000200160882827028294310100020001000282462839611610011000100001000210000001001112139811050672543574043198053461382013433527992146331241013378100010002846028574285662841528396
6200428634212000000001050682823310234401000100010005000700160612807728467310100020001000284872847311610011000100001000210000001000002139571019271833421038197263268382210484127888146351233513880100010002847428478284582844428352
6200428565213000000021050502819300235251000100010005000209160722808828321310100020001000280262838411610011000100001000210010011000002138671025473243500039199173447382014333828027141741232513991100010002842628311284072831328452
620042847621210000002105193281630123364100010001000500070016081281032861031010002000100028406284221161001100010000100001000000100020213848971672073437037197753397381716383328004144351241614223100010002832328471283272857128401
6200428460213100000061052132822111234671000100010005000210160592816028517310100020001000285012839711610011000100001000210000021000112139381005172903577039196833293381814394028070145511233413565100010002846928436284802850728295
6200428247213100000020050222822400233701000100010005007000160882815228394310100020001000282592824911610011000100001000210000001001110138621024871343384041197323462382114463928102141451250413674100010002837628360284062835128440

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b, v1.8b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0060

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
602051200519000000000010100012003611949510945925601034010210001100003010010000100001079633573622861182850120027120051120051111896311241750100302002000010000602001000010000120051120051115020110099100401001000010000010010000011000000010000100032104108441196564000210109100001000040100120052120052120052120036120052
602041201048990000000010100012003611949510944325601034010210001100003010010000100001079984573613261182850120027120051120051111881311237450100302002000010000602001000010000120051120051115020110099100401001000010000010010000011000010010000110032104108441196564000210109100001000040100120052120052120052120052120052
60204120051900000000001688100012003611949510945925601034010210001100003010010000100001079396573632461175990120027120035120051111896311241750100302002000010000602001000010000120051120051115020110099100401001000010000010010000011000010010000110032104108441196564000210109100001000040100120052120052120052120052120052
602041200518990000000010100012003611949510945925601034010010001100003010010000100551079288573642061175991120011120035120051111896311237450100302002000010000602001000010000120059120051115020110099100401001000010000010010000001000000010000110032104108441196564000210109100001000040100120052120052120052120036120052
6020412010389900000000157388000012014211949510946225601004010910001100003010010000100001079561573613261182850120027120051120035111881311237450100302002000010000602001000010000120051120051115020110099100401001000010000010010000011000000010000110032104108441196564000210100100001000040100120052120052120036120052120036
60204120051899000000001010001200361195031095232560100401061000110000301001000010000107955257360846118285012001112005112003511189631124175010030200200001000060200100001000012005112005111502011009910040100100001000001001000000100000001000011003210410844119656400021009100001000040100120036120052120052120036120036
6020412005190000110000101001122091120401110214712604474032510045100543393311362111831145982579621661678400121555122688122742112361415113711565203473122654113936923011465111201227221227082415020110099100401001000010000110010034211003120915121004311004107163731414119656400021009100001000040100120052120052120036120036120052
60204123243921215100323142252816100412308212084711025988060480403511006110060343521162211583116065558066856191876012225412312412302811256551011396658139358522370811873711441191511823123414123498381502011009910040100100001000001001005340100542012825410049110035581221884119658400021000100001000040100120053120052120052120246121589
6020412091691361100026233319184810001200361194951094612560103401001000110000301001000010000107955257360846118285012173012121612162211222717911306053267326302149410645643961021410000120051120051115020110099100401001000010000010010000001000034310000110032107153771196564000010109100001000040100120052120052120052120052120052
60204120162899000011001010001200361194951094432560100401021000010000301001000010000107955257352936118285012002712005112003511189631124175010030200200001000060200100001000012003512005111502011009910040100100001000001001000001100001001000011003210413544119695400020109100001000040100120052120052120054120052120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
600251200479000000110000100120032119483109458256001340012100001000030010100001000010798095735293612558111200111200471200471119153112444500103002020000100006002010000100001200351200351150021109104001010000100001101000001100000012100001100031403995511965040002608100001000040010120048120051120051120036120051
6002412004289900000100700001200321194831094582560013400101000110000300101000010000107984557352936125581112002612005012005011191831124475001030020200001000060020100001000012004712004711500211091040010100001000001010000011000000186100000100031405944311965040002065100001000040010120036120036120107120075120052
60024120068899000000000000012003211948910945825600134001210001100003001010000100001079845573603561255811120026120035120050111918311244750010300202000010000600201000010000120050120047115002110910400101000010000010100000110000109100000100031405944311965040002068100001000040010120051120036120051120051120064
6002412043790000000046100001200351194831094582560013400101000010000300101000010000107984557360356125581112001112005012005011191531124475001030020200001006660020100001000012005012004711500211091040010100001000001010000001000000165100001100031404994411966840002968100001000040010120051120045120051120051120051
60024120036899000000000000012003511948310944325600104001210001100003001010000100001079845573603561255811120026120050120047111918311244750010300202000010000600201000010000120050120047115002110910400101000010000010100000110000009100000100031403944411966840002960100001000040010120051120048120036120048120036
600241200518990000000010000120081119483109458256001340012100011000030010100001000010797695736035612558111200111200471200351119033112444500103002020000100006002010000100001200501200351150021109104001010000100000101000000100000015100001100031783993311966840002968100001000040010120051120036120051120051120051
600241200788990000000000100120020119483109458256001340012100011000030010100001000010798455735293612558111200111200351200501119183112444500103002020000100006002010000100001200351200471150021109104001010000100000101000001100000012100001101031403943611966840002900100001000040010120051120048120051120051120051
6002412006489900000000700001200351194891094432560010400121000010000300101000010000107984557360356124344112002612005012005011191831124375001030020200001000060020100001000012005012004711500211091040010100001000001010000011000000144100001100031402993411966840002965100001000040010120051120051120051120051120036
600241200359010000000018601001200351194831094432560013400101000110000300101000010000107984557360356125581112008212004712005011191831124475001030020200001000060020100001000012004712004711500211091040010100001000001010000011000030105100001000031405993211965040000968100001000040010120051120048120036120051120036
600241200588990000110000000120036119489109458256001340012100011000030010100001000010798455736035612558111200261200501200351119181711244750010300202000010000600201000010000120050120035115002110910400101000010000110100000110000000100000100031403994311966540000068100001000040010120051120051120048120051120051

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b, v1.8b }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0060

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60205120041900101000000200011200421195151094672560103401041000210000301001000010000107936857365186119172112004612004112005711189731124105010030200200001000060200100001000012004112005711502011009910040100100001000001001000321100020011000011112003211212123119672400040012100001000040100120061120061120058120061120061
602041200608991000000002000012004211951510946425601064010210002100003010010000100001079423573559361191721120033120041120060111897311241350100302002000010000602001000010000120057120057115020110099100401001000010000010010002201000411110000010100032112121221196514000213100100001000040100120042120058120058120066120061
6020412004189910001000010100120026119515109449256010640104100011000030100100001000010793685736518611932811200341200581200601118973112413501003020020000100006020010000100001200601200571150201100991004010010000100000100100023110001001100001111100321131212211966940004131312100001000040100120058120061120042120061120061
602041200608991010100001010012004511951510946425601034010410002100003010010000100001079368573651861175181120036120041120060111906311241550100302002000010000602001000010000120060120041115020110099100401001000010000010010001311000132110000011110032113121221196724000413012100001000040100120061120058120042120042120042
602041200418991000000002010012004511951510946725601064010210002100003010010000100001079423573651861191721120033120060120041111897311241350100302002000010000602001000010000120060120041115020110099100401001000010000010010002211000301110000111110033502100221196694000213012100001000040100120058120061120058120061120042
60204120060899101010000101001200451195151094492560106401041000210000301001000010000107942357365186119328112003612004112004111190331124155010030200200001000060200100001000012004112004111502011009910040100100001000001001000120100027022100000101100321131213311967240004009100001000040100120061120061120042120061120153
6020412005789910100000010100120026119512109449256010640104100011000030100100001000010793685735593611932811200331200411200571119063112413501003020020000100006020010000100001200571200571150201100991004010010000100000100100022010003011100001111000321121213311966940004131012100001000040100120061120061120061120061120061
6020412004289910100000020101120045119530109467256010640104100021000030100100001000010793685736518611917211200361200571200571119063112413501003020020000100006020010000100001200411200411150201100991004010010000100000100100012010001001100001111100321121213211966940004131012100001000040100120042120042120042120061120061
6020412004190010101000020100120026119515109464256010640104100011000030100100001000010822925736518611751811200171200601200601118973112415501003020020000100006020010000100001200571200571150201100991004010010000100000100100012110002700110000111100032113121221196514001213109100001000040100120061120061120063120061120061
602041200418991010100002010012004511953010946725601064010410002100003010010000100001079368573559361191721120036120041120057111903311241050100302002000010000602001000010000120060120057115020110099100401001000010000010010001111000101110000111120032113121231196514000201312100001000040100120042120042120058120061120058

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)03l2 tlb miss data (0b)0e0f18191e1f22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
600251200478990110060100120079119480109455256001340012100011000030010100001000010798095735888612434401120023012004712004711191503112444500103002020000100006002010000100001200471200471150021109104001010000100000101000001100000001000011010314031151111967140002665100001000040010120048120036120048120048120048
60024120047899010001010012003211948010945525600104001010001100003001010000100001079809573588861255810112001101200471200351119150311243750010300202000010000600201000010000120047120047115002110910400101000010000010100000110000000100001110031401991111966540002660100001000040010120048120048120036120048120048
60024120047899010004010012003211948910945525600104001210001100003001010000100001079769573588861243440112002301200471200351119150311244450010300202000010000600201000010000120047120047115002110910400101000010000010100000110000000100001000031401941111966540002665100001000040010120048120048120048120036120036
60024120047899011001000012003211948010945525600104001210001100003001010000100001079809573588861255810112002301200471200471119030311244450010300202000010000600201000010000120047120047115002110910400101000010000010100000110000000100000000031401941111966540002600100001000040010120048120048120048120089120039
60024120047899001000010012002011948010945525600134001210001100003001010000100001079769573588861255810112002301200471200471119030311244450010300202000010000600201000010000120047120047115002110910400101000010000010100000110000000100001000031401991111965040000060100001000040010120048120048120036120048120048
60024120047899000001000012003211948010944325600134001210000100003001010000100001079809573588861256830112002801200471200541119150311244450010300202000010000600201000010000120047120047115002110910400101000010000010100000110000000100001000031402991111966540002665100001000040010120048120048120048120048120048
60024120047899000000010012003211948010945525600134001210001100003001010000100001079809573588861243440112002301200471200471119150311244450010300202000010000600201000010000120035120047115002110910400101000010000010100000010000000100001100031401991111966540002665100001000040010120036120048120048120048120048
60024120047899000001010012003211948010945525600134001210001100003001010000100001079809573588861255810012001101200351200351119150311244450010300202000010000600201000010000120047120047115002110910400101000010000010100000110000000100001100031401991111966540002665100001000040010120048120048120048120048120048
6002412004789900000101001200321194801094432560013400121000110000300101000010000107980957358886124344011200230120047120047111903031124445001030020200001000060020100001000012004712003511500211091040010100001000001010025001003202898041002811000386633434312161140163660100001000040010122581122636122047122459122548
60024120047900000252525212288100122566120412110166806603384021210041100523367211371110861147250579351461700240112236501229951223561126100486113937575453501522672116626967211494115421230941229112615002110910400101000010000010100520010051001115381005311000346923462212226040218065100001000040010122962122458121403120050120048

Test 4: throughput

Count: 8

Code:

  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)030f1e223a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5b6bbl1d cache miss ld nonspec (bf)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602052673020004411267122101372580100100800001008000050011687540267062672726731665436685801002001600002008000026727267272180201100991001008000080000010080000438003903880039613905110216222670401410780000800001002672826881268042680626732
1602042673120004511266922111825801001008000010080000500117488702670626731267316654366898010020016000020080000267312672711802011009910010080000800000100800194380039038800386155445110216222672801414780000800001002672826794268622673726732
1602042673120004511267160121212580100100800001008000050011797260267062673126731665436697801002001600002008000026727267271180201100991001008000080000010080000438003903880039613944511021622267280010480000800001002681226878267362685926732
1602042673120004501266922111925801001008000010080000500116875402670626727267316654366898010020016000020080000267312670711802011009910010080000800000100800004480038038800386138435110216222672801414780000800001002673226924267412673726732
1602042673120004401267202121172580100100800001008000050011687540267022673126731665436689801002001600002008000026731267071180201100991001008000080000010080000438003800800386038435110216222672801414780000800001002672826852268252681026728
1602042673120004401267162112325801001008000010080000500116908502670226727267316650366858010020016000020080000267072672711802011009910010080000800000100800004380039039800006138445110216222672801014480000800001002672826880268042687126728
1602042672720004401267162112425801001008000010080000500117488702670626731267276654366858010020016000020080000267312670711802011009910010080000800000100800004380039038800380139445110216222672801414780000800001002672826905267832685526732
160204267312000440126692011222258010010080000100800005001169085026706267312673166303668980100200160000200800002672726727118020110099100100800008000001008000043800003080000613805110216222672801414480000800001002672826832268522673826749
16020426731200044012671620121258010010080000100800005001168627026706267312672766542766898010020016000020080000267312672711802011009910010080000800000100800004480038338800006138445110216222672801410780000800001002672826728267942672826741
1602042674020000112671621119258010010080000100800005001174887026706267272673166543668580100200160000200800002673126727118020110099100100800008000001008000008003913880000603844511021622267280010780000800001002672826905267812673426728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03090e0f1e223a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160025267312001000012671221124125800101080000108000050116875402670626707267316677036711800102016000020800002673126727118002110910108000080000110800004308003800388000061394305020616642672401078000080000102673226732268832679326732
160024267312000004401267160121219258001010800001080000501168627026682267272673166770367118001020160000208000026731267271180021109101080000800000108000043080039003980039613944050205164526728141448000080000102671426728267392673426732
1600242673120000045012671621121258001010800001080000501174628026706267312673166530367118001020160000208000026707267071180021109101080000800000108000044080000000800386104405020416442670401048000080000102673126716267372672926728
16002426727200000450126713212122325800101080000108000050117342702670626707267316676036711800102016000020800002673226727118002110910108000080000010800004308003902398003961044050204164526724141408000080000102674226746267322673426732
16002426731200000450126712212121625800101080000108000050117488712670626731267316676036711800102016000020800002673126707118002110910108000080000010800004308000000388003861044050205165526704141478000080000102737226742267392673226708
1600242673120000044012671621121258001010800001080000501174887026682267312673166760367118001020160000208000026731267071180021109101080000800000108000043080038003880038613843050204164426728141408000080000102683026732267382672826708
160024267312000004401266922112425800101080000108000050116862702670226707267276676036711800102016000020800002672726707118002110910108000080000010800004308003800080038613943050204164426724101008000080000102688826730267412674126728
160025267272010000012671621024258001010800001080000501174887026706267392672766720367118001020160000208000026731267271180021109101080000800001108000044080038003880038613843050204164426728141478000080000102671126740267412672926708
160024267312000000012671221123258001010800001080000501169085026706267312673166530367078001020160000208000026727267071180021109101080000800000108000043080038003880038613944050204164426724141078000080000102673726739267372672826732
1600242673120000044012671621126258001010800001080000501174887126702267312673166730367118001020160000208000026731267071180021109101080000800000108000043080038014180040613844050205165326728141478000080000102673426735272142673626736