Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 8H)

Test 1: uops

Code:

  ld1 { v0.8h, v1.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)0e0f1e22243a3f43464951schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)f5f6f7f8fd
620052867721325221161051102813802023177200020002000100006160702797528329310200020002000282062834911610011000100002000002002102200242613871956370493129138019796336638161152502784714541123441359120002827828588283542829428334
6200428447210192500800480828128022232672000200020001000081607927968285623102000200020002825728053116100110001000020000420020022002020138951019370663383125419888332238211649462797614218121721376420002823128268282092827628287
6200428274213222300410511928228000230862000200020001000041608028153282643102000200020002846728311116100110001000020000020021002002022138861047569773356124919659328638181355462787414374121001376120002828828298283612850928324
620042844221419201140051342812020223223200020002000100006160992810728142310200020002000283232829811610011000100002000002000002200042013677103887013336010531966233513819651552804015206122601445220002831228196282742824428221
620042836521224200000050302807100223293200020002000100003160522797828633310200020002000282102831611610011000100002000042002002200242413400995170213303125519626336638191062542807714469123981392520002819728627282262823328327
6200428318212231900600481728159000232302000200020001000071607028115282383102000200020002837628238116100110001000020000020000022002026137381031169733243145219699340738171356532788914557122821379920002871628350284422831128657
6200428259212232400000505528024000230872000200020001000061606328018282863102000200020002832328490116100110001000120000420020022002406139451000570903409114919619346238171352512791614056123101378120002828028247282772817828561
620042836621222200061052142800802023162200020002000100002160692828728193310200020002000283402841911610011000100002000062002002200040013769101637195321765019565338038131053552788014333123391464520002831828350281612825728285
620042832321125210040048812803600223268200020002000100004160712807328222310200020002000282762834711610011000100002000002002002200042413874102517104324995119773348538171739392796414539121061365920002826128665283042834528334
6200428333212172000600518128012000231582000200020001000051607327997281943102000200020002829328237116100110001000020000620020022000400139281002870483135135820007316038151247532802815525125831417720002843828274283282880928345

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h, v1.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0061

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f181e22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
6020512003589900010001011200209671610975225701064010210002200003010010000200001042587357329563465800112003712006112005711213016112768601003029620124100316039420126100001200611200601150201100991004010010000100001100200032220003012520000222210032102161111983440002100132000040100120064120044120058120134120062
6020412004189911100040011200429672210978525701064010410001200003010010000200001042761357329563465800012003312004112006311215031125196010030200200001000060200200001000012004412004111502011009910040100100001000011002000322200021321220000222210032101161111983440004010132000040100120062120062120058120125120058
602041200618991110002002120046967561097512570106401041000420000301001000020000104263855733916346533601200171200411200611121493112519601003020020000100006020020068100001200611200571150201100991004010010000100000100200022020002001220000220210032391161111983440004100132000040100120062120042120042120110120042
602041200578991110004000120042967221097502570106401021000220000301001000020000104276135732956346533601200371200611200611121493112519601003020020000100006020020000100001200601200411150201100991004010010000100000100200043220002000220000220210132101161111983440004101492000040100120062120058120058120151120062
60204120061899110000160121200269676110975025701064010210002200003010010000200001042761357339163465800012003712005712006111214531125196010030200200001000060200200001000012006112006111502011009910040100100001000001002000222200030002200002222000321011611119834400041014132000040100120042120058120087120082120062
6020412004189911000040021200269672210974925701064010210002200003010010000200001042761357337243465800012001712005712006111214931125196010030200200001003460200200001000012011612006411502011009910040100100001000001002000342200020012200002202200321011611119814400021410132000040100120042120058120058120160120062
602041200418991001004012120046967221097532570106401041000220000301001000020000104276135733724346580011200311200351200551121233112513601003020020000100006020020000100001200351200511150201100991004010010000100000100200000020003010520000222200032101161111983040004010132000040100120042120062120058120126120062
602041200578991100004012120042967541097462570103401021000220000301001000020000104258735732956346580011200331200411200601121293112519601003020020000100006020020000100001200611200571150201100991004010010000100000100200022020003020220000222210032101161111983440002140132000040100120042120062120058120141120042
602041200418991100004010120026967221097542570106401021000220000301001000020000104272655733724346580001200331200571200611121493112519601003020020000100006020020000100001200611200411150201100991004010010000100000100200033220003001220000222200032101161111981440002010132000040100120042120062120058120097120042
6020412006189910100040111200429672210975325701034010410002200003010010000200001042761357339163465336012003712005712005711212931125196010030200200001000060200200001000012006112004111502011009910040100100001000001002000232200020008200042222000321011611119830400041410132000040100120062120042120058120164120062

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f181e1f22243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
600251200578991111104010112004296647109746257001340012100022000030010100002000010425896573372434655240120017012005712004111216831125216001030020200001000060020200001000012008612005711500211091040010100001000001020003522000401022000022221003140517086119820400021010132000040010120042120058120058120058120058
60024120057899100100401011200269663110973025700164001210002200003001010000200001042450457339163465524012003701200421200571121523112541600103002020000100006002020000100001200571200411150021109104001010000100000102000342200020002200000202000314071606711981640004140132000040010120042120058120058120058120042
6002412005789910100080001120026966471097302570016400121000120000300101000020000104258965733724346552401200370120041120057112152311253760010300202000010000600202000010000120057120057115002110910400101000010000010200033220002001220000020210031406160861198324000414092000040010120042120042120058120042120058
6002412005789911110040001120026966471097502570016400141000120000300101000020000104258965732956346564001200170120057120057112168311253760010300202000010000600202000010000120041120057115002110910400101000010000010200042220003010220000222200031403160861198324000201002000040010120058120042120062120058120058
60024120041899101000110101120042966471097502570016400141000220000300101000020000104258965733724346552401200170120041120041112152311253760010300202000010000600202000010000120061120041115002110910400101000010000010200022220003000220000222200031404160541198324000201092000040010120042120058120058120058120058
60024120061899100000400011200269664710974625700164001210002200003001010000200001042589657337243465060012001701200571200411121683112540600103002020000100006002020000100001200571200571150021109104001010000100000102000222200030022200002222200314031604411983240004101092000040010120042120042120058120058120058
60024120057899111000401011200269664710975025700164001410002200003001010000200001042589657337243465524012003301200571200571121683112539600103002020000100006002020000100001200571200571150021109104001010000100000102000230200020102200002222101314061608711983640004141492000040010120061120058120042120058120058
6002412008689911000020001120042966471097302570016400121000120000300101000020000104245045733724346506001200370120057120063112152311254160010300202000010000600202000010000120401120057115002210910400101000010000010200032220003012220000222200031405160341198324000401402000040010120058120042120058120058120042
600241200578991000002000112004696631109746257001640014100022000030010100002000010425896573295634655240120033012005712005711216831125376001030020200001000060020200001000012006712005811500211091040010100001000001020003222000200222000022221003140416034119836400040092000040010120058120042120058120058120062
60024120057900100000201001200429665110975025700134001410001200003001010000200001042589657339163465524012001701200611200411121723112541600103002020000100006002020000100001201331200681150021109104001010000100000102000230200030002200002202200314071604411983240004010132000040010120058120062120042120058120058

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h, v1.8h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
60205120051899000000002010021200269672610975025701064010410002200003010010000200001042761357339163465800012003701200611200611121493112499601003020020000100006020020000100001200981200701150201100991004010010000100000100200000220000300200002020000032101161111981440004140132000040100120042120058120062120062120058
60204120057899100100004000021200269672610975025701034010210002200003010010000200001042761357339163465800112007701200611200571121493112499601003020020000100006020020000100001200411200571150201100991004010010000100000100200033220003012200002222000032101161111983040004141092000040100120042120062120062120058120058
6020412005790010000000340000212004696726109750257010640104100022000030100100002000010427265573295634658001120033012004112006111212931125196010030200200001000060200200001000012004112006111502011009910040100100001000001002000230200031022000022020000321011611119830400041414132000040100120060120058120042120058120062
602041200618991101000040000112004696726109750257010640104100012000030100100002000010425873573295634658001120033012004112005711214931124996010030200200001012760200200001000012006112005711502011009910040100100001000001002000230200020052000002220000321011611119834400041410132000040100120058120042120058120058120058
602041200578991001000122000021200269750010985188701064011310008200003010010000200001042761357339163465800012003701200611200611121523112527601003020020250100006020020062100311202371204063150201100991004010010000100000100200022220002002200002222100032101161111983440004141492000040100120042120062120062120062120063
6020412006189910000000160000212004696706109746257010640102100022000030100100002000010425873573391634658000120119012006212005711220110112643601003020020124100326038620126100321203721201573150201100991004010010000100000100200022220002105200002202100032101161211983040004014132000040100120062120062120042120058120062
6020412006289910010000401000120046967061097302570103401041000220000301001000020000104258735733916346580001200370120061120061112149311251560100305862024810127609482000010000120061120057115020110099100401001000010000010020004222000310520000022200003210116111198344000401402000040100120062120066120062120062120042
60204120062899110100004000001200469672610974625701064010410002200003010010000200001042761357329563465800012003701200411200411121493112499601003020020000100006020020000100001200571200571150201100991004010010000100000100200023020002012200002202200032101161111983440002101002000040100120042120058120062120061120042
60204120061899111010004010021200269670610973025701034010210002200003010010000200001042761357337243465336012003701200411200411121493112499601003020020000101286020020000100001200571200571150201100991004010010000100000100200033020002005200002222000032101161111981440002141402000040100120062120066120042120062120042
602041200618991001000013010021200469672210975025701064010410002200003010010000200001042726557339163465916012003701200611200571121493112499601003020020000100006020020000100331200611200571150201100991004010010000100000100200023020004102200002222000032101161111983440002014132000040100120062120062120042120062120062

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0e0f191e22233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
6002512004789900010210012002096641109724257001040012100012000030010100002000010423974573343634652341120027312014512004711221831125316001030120200001000060020200001000012005112004711500211091040010100001000001020000022000000020000200031401516099119822400020652000040010120036120052120052120052120052
600241200478990000021001201119664110974025700134001210001200003001010000200001042397457326663465234112002301200511200511121463112531600103002020000100006002020000100001200471200471150021109104001010000100000102000000200000002000000003140716077119822400020052000040010120099120036120052120052120052
6002412003589900000564101120020966421097412570010400121000020000300101000020000104253745733436346523411200110120051120051112158311252760010300202000010000600202000010000120035120047115002110910400101000010000010200000020000000200002200314071628811986640002101002000040010120036120052120048120052120036
60024120035899000006101120036966371097362570010400121000020000300101000020000104253745733244346488011200110120051120074112162311253760010300202000010000600202000010000120051120035115002110910400101000010000010200000220000000200002200314081608811982640000101002000040010120056120048120036120052120036
60024120051899000000001120036939751097402570010400101000120000300101000020000104239745733436346488011200660120051120047112162251125276001030020200641000060020200001003312004712017211500211091040010100001000001020000022000200020000220031408160771198264000210652000040010120052120052120052120036120052
60024120047899000009231011200689397510972425700204001210001200003001010000200001042397457334363465234112001101200351200511121623112534600103002020000100006002020000100001200351201151150021109104001010000100000102000002200000002000002003140816088119826400026002000040010120052120052120052120052120048
60024120051899000002101120032966411097402570013400121000120000300101000020000104253745732666346535011200230120051120035112162311252760010300202000010000600202000010000120051120047115002110910400101000010000010200000220000670320000220031409160121211987740002101002000040010120036120036120052120036120052
60024120035899000000100120036966411097242570013400121000020000300101000020000104250265733244346578111200110120051120051112162311252760010300202000010000600202000010000120051120035115002110910400101000010000010200000020000000200002200314081608911982640000101002000040010120048120052120036120036120036
6002412005189900000610112003696641109740257001340012100012000030103100002000010425374573343634653501120011012003612005711216231125286001030020200001000060208200001000012008312003511500211091040010100001000001020000022000069032000022003140816078119826400020692000040010120052120052120052120052120116
6002412004089900000210112003696641109740357001340012100012000030010100002000010425374573266634652341120011312003512005111215830112523600103002020000100006002020000100001200511200471150021109104001010000100000102000002200000002000022003140816087119826400020092000040010120052120048120052120036120036

Test 4: throughput

Count: 8

Code:

  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)03090e0f181e223a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
16020553401400100162015338321102516010010016000010016000050022998400533695337453374333253333321601002001600002001600005357153414118020110099100100800008000001001600000430160038003816003861394305110116115339401001600001005337553399533995339953399
16020453398400000044115335921121625160100100160000100160000500235246805335353374533983332033335616010020016000020016000053561534451180201100991001008000080000110016000004301600381039160038603944051101161153395101001600001005339553399533995339953375
1602045339440000000115338301119251601001001600001001600005002336264053362535565339633590333361160456200160000200160000535515340121802011009910010080000800000100160000244125160038042506160038613944051101161153391141441600001005340353399533755337553399
160204533744000000440153383210192516010010016000010016000050023522750533695339453394333213333561601002001600002001600005361853392118020110099100100800008000001001600000430160039003916016961394405110116115339114071600001005340353399533995339953379
160204533984000000560053383012102516010010016000010016000050023362640533735340253398333043333321601002001600002001600005362653505118020110099100100800008000001001600000430160039103816000001394305110116115339501471600001005339953375533955339953399
1602045339840000004511533592120192516010010016000010016000050023339620533735337453398333213333561601002001600002001600005340953374118020110099100100800008000001001600000430160038003916003801394405110116115339101401600001005339953375533755339953399
160204533983990000440153383211192516010010016000010016000050023328970533695337453374332963333321601002001600002001600005348553404118020110099100100800008000001001600000430160038003916003801394405110116115339514001600001005339953399533995339553399
1602045339839900004401533830120192516010010016000010016000050023362640533695339853398333203333521601002001600002001600005338653397118020110099100100800008000001001600000443416003970016000061384405110116115337101471600001005339953399533795340053399
16020453398400000045005338321019251601001001600001001600005002332897053369533745337433296333356160100200160000200160000534165400111802011009910010080000800000100160000043016003800381600386139005110116115339501401600001005337553399533995337553399
160204533944000000441153359011192516010010016000010016000050023362640533735339853398333203333561601002001600002001600005349753409118020110099100100800008000001001600000430160038004216003800380051101161153395141471600001005339953375533995337553398

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6674

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
160025533924000000010041010153374018181225160010101600001016000050233254953364533895338933319333369160010201600002016000053389533891180021109101080000800001101600000390160035003516003561353905020219162253371064160000105339553390533955337553375
16002453389400000000004101015337431818122516001010160000101600005023325495336453389533893331933336916001020160000201600005339953400118002110910108000080000110160000039016000000016000001353905020182162253390002160000105339053375533755339453379
16002453394400000000000000153359018012251600101016000010160000502332084533645338953389333343333691600102016000020160000533985340011800211091010800008000001016000003901601670088816003500393905020182165253371062160000105339753394533945339453394
160024533934000000000053000153359218012251600101016000010160000502332549533495338953389333193333691600102016000020160000533895338911800211091010800008000001016000003901600350001600396103905020182162253386662160000105337553375533945339153375
16002453393400000000004101015337821802251600101016000010160000502367024533535339353396333413333541600102016000020160576534625338411800211091010800008000011016000000016016700320316000061353905037182252653371060160000105339453390533795339053390
160024533894000000000045010253378218181525160010101600001016000050233383153349533965337433319333369160010201600002016000053393533931180021109101080000800000101600000390160035103516003561353905020182162253386662160000105339053390533905339053394
16002453393400000000003000005337821818122516001010160000101600005023320845336453393533893333833335416001020160000201600005339953389118002110910108000080000010160000039016000000351605596139005020212166253371062160000105339553375533905339053375
1600245339439900000000001015337401800251600101016000010160000502332084533645337453389333343333541600102016000020160000533745338911800211091010800008000001016000000016003500351600356135005020216162653386600160000105337553375533905339053390
160024533894000000100041000053374212012251600101016000010160000502349345533495338953389333193333541600102016000020160000533745337411800211091010800008000001016000000016000000016003500039050201821663533761002160000105384253386534035340953390
1600245338940000001040120001533742181812251600101016000010160000502332549533675337453374333373333541600102016000020160000533805339911800211091010800008000011016000000016003500016000061353905020182162253371660160000105337553390533905337553375