Firestorm: LD1 (multiple, 3 regs, 16B) measurements

Code:

  ld1 { v0.16b, v1.16b, v2.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
63005	28526	214	29	28	0	1	1	8	1	5073	28303	2	3	0	23266	3000	3000	3000	15000	7	16159	28156	28355	3	10	3000	3000	3000	28470	28305	1	1	61001	1000	1000	0	3000	0	3004	0	0	3004	3	0	0	6	13192	9688	7162	3289	11	91	19665	3311	3813	14	64	65	27941	14617	12209	13731	3000	28674	28429	28534	28428	28501
63004	28291	213	28	29	0	1	1	0	0	4879	28239	2	0	3	23226	3000	3000	3000	15000	8	16151	28025	28399	3	10	3000	3000	3000	28248	28179	1	1	61001	1000	1000	0	3000	6	3004	1	4	3000	0	0	7	9	13314	10198	7170	3208	14	62	19718	3247	3819	11	67	70	27977	14650	12186	13671	3000	28467	28469	28598	28621	28325
63004	28379	214	32	28	0	1	1	9	0	5134	28201	2	2	3	23255	3000	3000	3000	15000	6	16199	28055	28484	3	10	3000	3000	3000	28377	28204	1	1	61001	1000	1000	0	3000	9	3004	0	3	3004	5	0	7	6	13785	9411	7193	3338	15	69	19657	3258	3815	12	64	59	27929	15110	12267	13753	3000	28490	28626	28449	28306	28562
63004	28529	212	24	26	0	1	1	0	0	5045	28172	0	0	3	23373	3000	3000	3000	15000	3	16158	28045	28391	3	10	3000	3000	3000	28420	28471	1	1	61001	1000	1000	0	3000	6	3007	0	4	3000	0	0	3	9	13717	10104	7159	3456	8	65	19825	3320	3812	16	69	64	27895	14478	12562	13610	3000	28417	28515	28401	28239	28375
63004	28389	212	29	25	0	0	0	6	0	5200	28221	2	3	0	23243	3000	3000	3000	15000	4	16147	28137	28485	3	10	3000	3000	3000	28456	28233	1	1	61001	1000	1000	0	3000	9	3004	0	7	3007	4	0	0	9	13612	10080	7033	3372	13	64	19594	3279	3812	22	62	59	28146	14518	12177	14208	3000	28318	28601	28461	28453	28315
63004	28340	212	29	24	0	0	0	0	0	5144	28093	2	3	2	23442	3000	3000	3000	15000	6	16170	28110	28680	3	10	3000	3000	3000	28371	28291	1	1	61001	1000	1000	0	3000	9	3000	0	7	3003	4	0	1	6	13730	10158	7178	3400	15	66	19803	3301	3812	12	53	61	28011	14943	12406	13703	3000	28351	28301	28481	28224	28351
63004	28275	212	34	29	0	0	0	10	0	5136	28218	0	0	3	23290	3000	3000	3000	15002	4	16158	27980	28262	3	10	3000	3000	3000	28333	28276	1	1	61001	1000	1000	0	3000	9	3004	0	3	3001	5	1	4	9	13467	10046	7094	3371	14	69	19863	3319	3809	13	57	59	28031	14451	12127	13425	3000	28138	28372	28355	28404	28360
63004	28210	213	29	27	0	1	0	13	1	5066	28078	2	2	3	23206	3000	3000	3000	15000	5	16151	28023	28364	3	10	3000	3000	3000	28405	28351	1	1	61001	1000	1000	0	3000	9	3004	0	0	3007	4	0	3	6	13942	10162	7096	3267	15	63	19684	3222	3809	14	54	55	27877	14434	12217	13693	3000	28334	28516	28313	28365	28383
63004	28383	213	32	31	0	0	0	11	0	5016	28138	2	2	3	23192	3000	3000	3000	15000	4	16140	28198	28382	3	10	3000	3000	3000	28174	28252	1	1	61001	1000	1000	0	3000	9	3007	0	0	3007	5	0	7	6	13693	10258	7205	3395	8	53	19623	3315	3813	8	66	65	27896	14721	12526	13785	3000	28438	28472	28532	28390	28331
63004	28556	213	33	28	0	1	0	13	0	5006	28098	2	3	3	23102	3000	3000	3000	15000	4	16159	28026	28357	3	10	3000	3000	3000	28392	28253	1	1	61001	1000	1000	0	3000	9	3004	0	0	3004	3	1	7	6	13558	10298	7171	3394	13	65	20090	3302	3812	13	57	65	27981	14338	12003	13732	3000	28213	28479	28319	28393	28303

Count: 8

Code:

  ld1 { v0.16b, v1.16b, v2.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80070	599	0	0	0	0	0	0	0	44	0	0	0	0	80046	0	1	0	19	25	240100	100	240000	100	240017	500	3503030	1	80015	80065	80065	49993	6	50017	240116	200	240024	200	240024	80040	80061	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	43	0	240040	0	0	0	39	240038	6	0	41	0	0	0	1	1	1	5116	0	16	0	0	80058	0	14	0	7	240000	100	80041	80066	80066	80066	80041
240204	80062	600	0	0	0	0	0	0	0	44	0	0	0	1	80050	2	1	1	19	25	240100	100	240000	100	240016	500	3504188	0	80040	80064	80064	49968	6	49992	240115	200	240024	200	240024	80065	80061	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	43	0	240000	0	1	0	54	240039	6	1	59	44	0	0	1	1	1	5116	0	16	0	0	80063	0	0	14	4	240000	100	80063	80062	80372	80278	80041
240204	80216	602	1	1	0	0	0	0	0	78	0	0	0	0	80050	0	0	12	21	25	240100	100	240000	100	240014	500	3518162	1	80044	80065	80065	49969	6	50013	240116	200	240024	200	240024	80065	80061	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	0	0	240000	0	0	0	0	240039	5	0	40	44	0	0	1	1	1	5116	0	16	0	0	80058	0	13	13	0	240000	100	80070	80070	80066	80075	80071
240204	80068	599	0	0	1	0	0	0	0	21	0	0	0	1	80046	2	1	0	0	25	240100	100	240000	100	240000	500	3551453	1	80015	80065	80040	49967	3	50023	240100	200	240000	200	240000	80069	80061	3	1	80201	100	99	100	100	80000	80000	0	100	240000	0	0	30	240000	0	0	2	1033	240039	0	1	0	44	0	1	0	0	0	5110	1	16	1	1	80062	0	14	14	7	240000	100	80070	80062	80066	80069	80066
240204	80040	602	0	0	0	1	0	0	0	72	0	0	0	1	80054	2	0	12	1	25	240100	100	240000	100	240000	500	3510014	1	80036	80044	80065	49967	3	50027	240100	200	240000	200	240000	80069	80065	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	0	0	240038	0	0	0	42	240039	0	1	41	44	0	0	0	0	0	5110	1	16	1	1	80066	0	0	0	0	240000	100	80076	80065	80062	80066	80041
240204	80040	599	0	0	0	1	0	0	0	79	0	0	0	0	80049	0	1	0	16	25	240100	100	240000	100	240000	500	3506992	1	80015	80065	80065	49963	3	50019	240100	200	240000	200	240000	80064	80061	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	43	0	240000	0	0	0	6	240040	6	1	0	0	0	0	0	0	0	5110	1	16	1	1	80062	0	0	0	7	240000	100	80066	80066	80066	80066	80066
240204	80065	599	0	0	0	0	0	0	0	0	0	0	0	1	80049	2	1	1	20	25	240100	100	240000	100	240000	500	3542390	1	80015	80040	80040	49963	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	43	0	240040	0	0	0	0	240000	0	1	39	0	0	0	0	0	0	5110	1	16	1	1	80062	0	0	14	7	240000	100	80041	80066	80066	80065	80065
240204	80061	602	1	0	0	0	1	0	0	126	0	0	0	1	80025	0	1	1	20	25	240100	100	240000	100	240000	500	3519840	1	80039	80065	80065	49984	3	50019	240100	200	240000	200	240000	80040	80061	1	1	80201	100	99	100	100	80000	80000	0	100	240021	20	43	0	240039	0	0	0	38	240000	0	1	59	0	0	0	0	0	0	5110	1	16	1	1	80062	0	13	13	7	240000	100	80065	80041	80066	80066	80066
240204	80040	599	0	0	0	0	0	0	0	44	0	0	0	1	80050	2	0	1	0	25	240100	100	240000	100	240000	500	3505448	1	80040	80040	80061	49988	3	49998	240100	200	240000	200	240000	80061	80061	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	43	0	240000	0	0	0	0	240039	0	0	40	0	0	0	0	0	0	5110	1	16	1	1	80037	0	14	14	7	240000	100	80062	80066	80041	80041	80066
240204	80066	599	0	0	0	0	0	0	0	45	1	0	0	1	80025	0	12	12	19	25	240100	100	240000	100	240000	500	3518543	0	80041	80040	80040	49963	3	50023	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	1	100	240000	0	0	0	240000	0	0	0	40	240039	6	1	0	44	0	0	0	0	0	5110	1	16	1	1	80062	0	0	10	7	240000	100	80066	80066	80065	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80071	600	1	0	0	1	1	1	0	0	67	0	1	0	0	80054	3	9	0	20	25	240010	10	240000	10	240000	50	3527112	0	80045	80070	80069	49993	3	50049	240010	20	240000	20	240000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	1	10	240019	19	43	240060	1	75	1	62	240039	5	1	60	43	19	1	0	5020	20	16	0	6	13	80045	13	0	5	240000	10	80070	80049	80048	80071	80048
240024	80348	600	1	0	1	1	0	0	0	0	66	0	0	0	0	80032	0	7	9	19	25	240010	10	240000	10	240000	50	3501575	0	80023	80070	80446	50037	3	50049	240010	20	240000	20	240000	80070	80070	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	19	43	240059	2	50	2	60	240000	0	1	19	0	19	0	0	5020	6	16	0	13	6	80066	13	13	0	240000	10	80070	80049	80070	80071	80196
240024	80069	599	1	0	1	1	0	0	0	0	21	0	0	0	1	80036	0	7	7	19	25	240010	10	240000	10	240000	50	3521582	0	80045	80048	80048	50015	3	50050	240010	20	240000	20	240000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	20	43	240019	1	1	1	21	240040	0	0	59	0	18	1	0	5020	13	16	0	13	8	80070	13	13	5	240000	10	80070	80070	80048	80048	80302
240024	80070	599	1	0	1	0	0	0	0	0	21	0	0	0	0	80054	3	0	7	0	25	240010	10	240000	10	240000	50	3509465	1	80023	80047	80070	50014	3	50027	240010	20	240000	20	240000	80047	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240020	19	43	240060	1	5	1	63	240041	0	0	19	43	19	0	0	5020	8	16	0	7	4	80066	0	13	0	240000	10	80071	80048	80070	80070	80662
240024	80048	599	1	0	1	1	0	0	2	0	100	0	0	0	2	80054	2	0	7	20	25	240010	10	240000	10	240000	50	3509465	1	80045	80072	80070	50015	3	50050	240010	20	240000	20	240000	80069	80069	1	1	80021	10	9	1	10	10	80000	80000	0	10	240019	19	43	240060	1	58	1	62	240000	5	1	19	0	19	0	0	5020	6	16	1	4	5	80046	13	0	5	240000	10	80074	80071	80070	80070	80186
240024	80069	599	1	0	1	1	0	0	0	0	67	0	1	0	0	80055	2	0	7	20	25	240010	10	240000	10	240000	50	3501575	1	80022	80069	80069	50014	3	50049	240207	20	240000	20	240000	80202	80075	1	1	80021	10	9	0	10	10	80000	80000	0	10	240021	20	43	240060	1	0	1	287	240040	0	0	59	0	19	0	0	5020	10	16	0	6	5	80067	13	13	5	240000	10	80048	80070	80070	80070	80209
240024	80047	600	1	1	0	1	0	0	0	0	67	0	0	0	2	80032	3	7	7	19	25	240010	10	240000	10	240000	50	3500176	1	80045	80070	80070	50015	3	50028	240010	20	240000	20	240000	80069	80047	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	20	43	240058	1	4	1	21	240041	5	1	19	0	19	0	0	5020	6	16	0	6	5	80066	13	13	5	240000	10	80070	80070	80071	80070	80212
240024	80070	600	1	0	1	0	0	0	0	0	67	0	0	0	2	80057	3	7	0	19	25	240010	10	240000	10	240000	50	3511500	1	80022	80070	80070	49993	3	50049	240010	20	240000	20	240000	80073	80047	1	1	80021	10	9	0	10	10	80000	80000	0	10	240020	19	43	240060	0	2	1	61	240041	5	1	19	43	19	1	0	5020	6	16	0	5	6	80066	13	0	5	240000	10	80048	80048	80048	80049	80206
240024	80070	599	1	0	1	1	0	0	0	0	67	0	0	0	1	80032	3	0	9	41	25	240010	10	240000	10	240000	50	3523545	1	80044	80084	80048	50015	3	50028	240010	20	240000	20	240000	80048	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240020	21	0	240059	0	47	1	23	240041	5	1	19	43	19	1	0	5020	7	16	0	7	7	80067	13	0	0	240000	10	80071	80071	80048	80048	80664
240024	80071	600	1	1	0	1	0	0	0	0	222	0	0	0	3	80054	0	0	7	19	25	240010	10	240000	10	240000	50	3521582	0	80022	80069	80070	50015	3	50050	240010	20	240000	20	240000	80069	80047	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	19	43	240060	1	28	1	21	240040	5	1	60	43	19	0	0	5020	6	16	1	4	5	80044	13	0	5	240000	10	80071	80070	80071	80048	80166

LD1 (multiple, 3 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations