Firestorm: LD1 (multiple, 3 regs, 1D) measurements

Code:

  ld1 { v0.1d, v1.1d, v2.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	28628	214	12	18	0	1	4	0	0	0	5297	28309	2	2	0	22942	2000	2000	2000	10000	10	0	0	16189	27936	28147	3	10	2000	3000	2000	27954	28046	1	1	61001	1000	1000	0	2000	4	2000	1	4	2000	2	0	4	14121	10482	7299	3570	6	43	19588	3407	3809	7	40	34	27866	15235	12627	13856	2000	1000	28174	28007	28200	28134	28080
63004	28176	211	14	15	0	1	0	0	0	0	5192	27893	2	2	2	23479	2000	2000	2000	10000	7	1	0	16143	28001	27997	3	10	2000	3000	2000	28001	28508	1	1	61001	1000	1000	0	2000	4	2004	0	12	2000	4	0	4	13996	9852	7243	3495	3	35	19856	3282	3807	10	38	34	28033	14801	12138	12992	2000	1000	28004	28071	27988	28107	28348
63004	28215	211	15	10	0	1	0	1	0	0	5274	28057	2	2	2	23360	2000	2000	2000	10000	2	0	0	16212	27893	28108	3	10	2000	3000	2000	28069	28088	1	1	61001	1000	1000	0	2000	4	2000	0	4	2003	2	0	4	13935	10508	7105	3542	7	39	19469	3408	3817	10	37	36	27770	13975	12057	13188	2000	1000	28090	28078	28180	28241	28129
63004	28512	214	14	11	0	1	10	1	0	0	5311	28004	2	0	2	23234	2000	2000	2000	10000	1	1	8	16180	27828	28107	3	10	2000	3000	2000	28403	27896	1	1	61001	1000	1000	0	2000	4	2000	0	4	2004	2	4	4	14042	10544	7048	3501	6	32	20014	3480	3818	8	35	35	27886	14047	12034	13360	2000	1000	28142	28303	28104	28236	28068
63004	28071	211	12	12	0	1	4	0	0	0	5297	27833	2	2	0	23163	2000	2000	2000	10000	0	0	8	16187	28072	28536	3	10	2000	3000	2000	28036	28519	1	1	61001	1000	1000	0	2000	4	2002	0	4	2000	2	0	0	13798	10241	7237	3469	5	40	19434	3501	3811	14	32	35	27862	13647	12763	13507	2000	1000	28090	28113	28056	28219	28161
63004	28563	213	8	10	0	1	6	0	0	0	5225	28227	2	2	0	23450	2000	2000	2000	10000	10	1	0	16160	28092	28155	3	10	2000	3000	2000	28066	28145	1	1	61001	1000	1000	0	2000	4	2004	0	138	2000	2	2	0	14186	9976	7056	3427	5	33	19438	3377	3810	12	43	36	27724	13811	11993	13277	2000	1000	28173	28055	28165	28144	28139
63004	27997	210	15	11	0	1	6	0	0	0	5268	27962	0	0	2	22983	2000	2000	2000	10000	3	0	0	16405	27913	28089	3	10	2000	3000	2000	28011	28248	1	1	61001	1000	1000	0	2000	4	2004	0	4	2004	2	4	4	13967	10289	7260	3519	4	44	19893	3389	3816	12	37	35	27848	13962	11942	13321	2000	1000	28060	28338	28350	28365	28118
63004	28157	210	16	11	0	1	66	0	0	0	5276	27874	2	0	2	23400	2000	2000	2000	10000	0	0	0	16161	27957	28044	3	10	2000	3000	2000	27979	28061	1	1	61001	1000	1000	0	2000	4	2002	0	0	2004	2	4	4	13996	10350	7336	3557	7	39	19420	3508	3815	14	34	35	27818	14974	12351	13163	2000	1000	28160	27957	28053	28565	28055
63004	28461	211	9	10	0	1	0	1	0	0	5150	27907	0	0	2	23023	2000	2000	2000	10000	2	0	8	16170	27916	28157	3	10	2000	3000	2000	28004	27952	1	1	61001	1000	1000	0	2000	0	2002	0	4	2002	4	4	4	13465	9845	7350	3297	6	37	19299	3343	3810	13	35	38	27728	13992	12111	13083	2000	1000	28076	28019	28462	28006	27962
63004	28409	211	6	10	0	1	6	0	0	0	5234	27868	2	2	2	22918	2000	2000	2000	10000	3	1	8	16184	27965	28502	3	10	2000	3000	2000	28011	28189	1	1	61001	1000	1000	0	2000	0	2004	0	4	2004	0	0	6	14026	9805	7275	3315	4	35	19864	3438	3819	12	32	36	27826	15309	12284	13266	2000	1000	27988	28333	28603	28056	28431

Count: 8

Code:

  ld1 { v0.1d, v1.1d, v2.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	53391	400	1	1	0	1	0	0	0	21	1	0	2	53366	2	0	18	0	25	160100	100	160000	100	160000	500	2336625	1	53374	53381	53399	23322	3	23357	160100	200	240000	200	160000	53398	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	0	0	160057	1	0	0	59	160038	6	1	56	42	19	2	5110	1	16	1	1	53395	9	9	2	160000	80000	100	53399	53400	53400	53382	53489
240204	53399	400	1	1	0	0	1	0	0	21	0	0	1	53383	0	18	18	22	25	160100	100	160000	100	160000	500	2326082	1	53356	53399	53398	23322	3	23356	160100	200	240000	200	160000	53399	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160021	19	42	0	160019	1	0	0	59	160000	6	1	56	42	19	0	5110	1	16	1	1	53396	9	9	2	160000	80000	100	53382	53382	53382	53400	53400
240204	53399	400	1	1	0	0	0	0	0	65	1	0	2	53373	2	18	18	16	25	160100	100	160000	100	160000	500	2343231	1	53374	53399	53398	23321	3	23357	160100	200	240000	200	160000	53398	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160019	20	42	0	160058	0	0	1	59	160038	6	1	57	42	19	0	5110	1	16	1	1	53378	0	9	0	160000	80000	100	53400	53382	53400	53399	53399
240204	53399	400	1	1	0	1	1	0	0	21	0	0	0	53366	2	18	18	45	25	160100	100	160000	100	160000	500	2336089	1	53383	53399	53400	23321	3	23357	160100	200	240000	200	160000	53400	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	0	0	160057	1	0	0	62	160038	0	0	57	0	19	2	5110	1	16	1	1	53396	9	0	2	160000	80000	100	53382	53382	53400	53382	53399
240204	53381	399	1	0	0	0	0	0	0	21	0	0	3	53383	2	18	0	0	25	160100	100	160000	100	160000	500	2334036	1	53374	53381	53398	23321	3	23357	160100	200	240000	200	160000	53398	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	42	0	160058	2	1	2	21	160038	6	1	57	42	19	0	5110	1	16	1	1	53396	9	0	2	160000	80000	100	53400	53382	53399	53382	53400
240204	53399	400	1	0	0	0	0	0	0	21	0	0	3	53383	1	0	18	0	25	160100	100	160000	100	160000	500	2334036	1	53374	53399	53381	23322	3	23356	160100	200	240000	200	160000	53399	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160020	20	42	0	160057	1	0	1	21	160000	6	0	19	42	19	0	5110	1	16	1	1	53395	9	0	2	160000	80000	100	53399	53399	53382	53400	53399
240204	53381	400	1	1	0	0	1	0	0	65	0	0	3	53384	2	18	0	15	25	160100	100	160000	100	160000	500	2336625	1	53381	53399	53381	23321	3	23357	160100	200	240000	200	160000	53381	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160020	20	42	0	160019	1	0	1	23	160000	6	1	57	0	19	1	5110	1	16	1	1	53396	0	9	2	160000	80000	100	53400	53382	53399	53382	53382
240204	53381	399	1	1	0	1	1	0	0	65	0	0	3	53366	2	18	18	16	25	160100	100	160000	100	160000	500	2353389	1	53397	53381	53399	23304	3	23339	160100	200	240000	200	160000	53381	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160021	19	0	0	160057	0	0	0	59	160000	6	0	57	42	19	1	5110	1	16	1	1	53395	9	9	2	160000	80000	100	53382	53400	53387	53400	53399
240204	53399	400	1	1	0	0	0	0	0	65	0	0	3	53383	2	0	18	15	25	160230	100	160000	100	160000	500	2343231	1	53374	53398	53381	23304	3	23339	160100	200	240000	200	160000	53399	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160020	20	42	0	160019	0	0	0	59	160038	6	1	57	42	19	1	5110	1	16	1	1	53395	9	9	2	160000	80000	100	53407	53400	53386	53401	53404
240204	53389	400	1	0	0	1	1	0	0	66	0	0	3	53383	0	18	18	16	25	160100	100	160000	100	160000	500	2354212	1	53373	53399	53398	23321	3	23357	160100	200	240000	200	160000	53398	53398	1	1	80201	100	99	100	100	80000	80000	1	100	160020	19	0	0	160057	1	0	0	59	160000	6	1	19	36	19	1	5110	1	16	1	1	53395	9	9	0	160000	80000	100	53570	53382	53400	53382	53382

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	53397	400	0	0	1	0	0	0	0	0	0	66	0	1	0	0	2	53387	2	7	0	1	25	160010	10	160000	10	160000	50	2347387	0	1	53356	0	53402	53402	23348	3	23382	160010	20	240000	20	160000	53402	53403	1	1	80021	10	9	10	10	80000	80000	0	10	160019	19	43	0	160058	1	0	1	61	160040	6	1	58	0	19	0	5020	17	16	7	13	53391	0	10	10	4	160000	80000	10	53395	53395	53375	53554	53395
240024	53394	400	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	53379	2	0	12	16	25	160010	10	160000	10	160000	50	2358180	0	1	53369	0	53394	53394	23319	3	23374	160010	20	240000	20	160000	53394	53394	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	43	0	160039	0	0	0	39	160000	6	1	39	0	0	0	5020	8	16	7	13	53391	0	10	0	4	160000	80000	10	53395	53395	53395	53395	53395
240024	53394	400	0	0	0	0	0	0	0	0	0	45	0	1	0	0	0	53379	2	12	0	16	25	160010	10	160000	10	160000	50	2352959	0	1	53378	0	53403	53403	23348	3	23382	160010	20	240000	20	160000	53402	53381	1	1	80021	10	9	10	10	80000	80000	0	10	160019	20	43	0	160019	1	0	1	63	160040	6	1	59	43	19	0	5236	11	133	9	13	55245	0	0	13	5	160000	80000	10	55550	55407	55405	55379	55395
240024	55398	415	1	0	0	0	0	0	0	13	13	1878	1232	1	0	0	2	55387	3	7	7	999	400	161701	11	161820	12	162314	50	2409247	0	1	55221	0	55542	55716	23339	3	23374	160010	20	240000	20	160000	53394	53394	1	1	80021	10	9	10	10	80000	80000	0	10	161692	2	43	403	161081	0	0	0	9078	161729	6	1	58	43	19	3	5151	16	138	6	13	55269	1	13	13	5	160000	80000	10	55566	53714	55263	55516	54379
240024	55859	417	1	2	0	0	0	0	1	16	11	2274	1408	1	0	0	4	54768	2	7	0	837	518	162090	12	162210	12	162848	62	2430416	0	1	56350	0	57525	57598	25414	214	25110	164945	20	246629	20	164426	56624	56330	27	1	80021	10	9	10	10	80000	80000	0	10	162885	22	43	691	162919	0	0	0	22873	162379	6	1	58	0	19	0	5401	13	260	14	18	56256	1	13	13	0	160000	80000	10	56784	56488	57854	56317	55686
240024	55857	444	1	0	0	1	0	0	0	0	0	66	0	1	0	0	3	53388	3	7	0	88	25	160010	10	160000	10	160000	50	2339140	0	1	53369	0	53394	53394	23352	3	23374	160010	20	240000	20	160000	53402	53375	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	43	0	160039	0	0	0	42	160000	6	1	39	43	0	0	5020	7	16	6	8	53371	0	10	10	4	160000	80000	10	53395	53395	53396	53395	53395
240024	53403	413	0	1	0	0	0	1	1	17	4	48	0	0	0	0	0	53379	0	12	0	16	25	160010	12	160000	10	160000	50	2353377	1	1	53366	0	53390	53382	23328	18	23577	160010	20	240000	20	160000	53374	53389	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	39	0	160035	0	0	0	0	160035	6	1	35	39	0	0	5020	5	16	9	5	53386	0	6	6	2	160000	80000	10	53375	53390	53390	53375	53390
240024	53389	400	0	0	0	0	0	0	0	0	0	41	0	0	0	1	1	53374	3	18	18	12	25	160010	10	160000	10	160000	50	2341510	4	1	53364	0	53389	53389	23334	3	23369	160010	20	240000	20	160000	53389	53374	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	39	0	160035	0	0	0	35	160035	0	1	35	0	0	0	5020	9	16	7	9	53386	0	6	6	2	160000	80000	10	53390	53390	53390	53375	53375
240024	53389	400	0	0	0	0	0	1	0	0	0	41	0	0	0	1	1	53359	2	18	0	0	25	160010	10	160000	10	160196	50	2341776	4	1	53364	0	53389	53389	23334	3	23369	160010	20	240000	20	160000	53389	53389	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	39	0	160035	0	0	0	35	160000	0	1	0	39	0	0	5020	7	16	6	7	53386	0	6	6	2	160000	80000	10	53375	53393	53375	53390	53390
240024	53389	400	0	0	0	0	0	1	0	1	0	0	0	0	0	1	1	53378	2	18	0	15	25	160010	10	160000	10	160000	50	2341776	4	1	53515	0	53374	53374	23334	3	23369	160010	20	240000	20	160000	53389	53374	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	0	160035	0	0	0	35	160035	6	1	36	0	0	0	5020	7	16	8	13	53386	0	6	6	2	160000	80000	10	53375	53390	53375	53390	53390

LD1 (multiple, 3 regs, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations