Firestorm: LD1 (multiple, 3 regs, 2D) measurements

Code:

  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
63005	29446	221	25	25	0	0	33	1	4697	28849	0	0	0	24036	3000	3000	3000	15000	0	16262	28702	29252	3	10	3000	3000	3000	29080	29166	1	1	61001	1000	1000	0	3000	9	3001	0	1	3004	5	1	4	9	0	13245	9125	6964	3163	4	77	20624	3225	3825	8	55	52	28398	15362	13703	15518	3000	29370	29263	29274	29190	29371
63004	29402	219	16	15	0	1	6	1	4558	28949	0	0	3	24171	3000	3000	3000	15001	3	16184	28735	29261	3	10	3000	3000	3000	29166	29123	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	1	4	9	0	12811	9479	6858	3035	5	55	20739	3330	3819	17	53	55	28388	16239	13698	15698	3000	29290	29373	29251	29299	29306
63004	29302	220	15	17	0	0	9	0	4557	28948	0	0	0	24007	3000	3000	3000	15000	0	16173	28590	29213	3	10	3000	3000	3000	29090	29119	1	1	61001	1000	1000	0	3000	6	3001	0	1	3004	5	0	4	6	0	12765	9514	6827	3035	6	48	20602	3118	3821	16	55	60	28312	16398	13549	15193	3000	29259	29274	29333	29264	29308
63004	29238	219	22	19	0	0	6	1	4773	28936	0	0	0	24086	3000	3000	3000	15000	0	16240	28565	29289	3	10	3000	3000	3000	29143	29096	1	1	61001	1000	1000	0	3000	3	3004	0	1	3001	5	1	1	6	0	12941	9028	6805	3073	8	45	20545	3122	3822	19	53	51	28331	16360	13713	15870	3000	29287	29219	29277	29196	29254
63004	29217	219	15	19	0	0	9	1	4603	28930	0	0	0	24044	3000	3000	3000	15001	0	16176	28662	29292	3	10	3000	3000	3000	29167	29193	1	1	61001	1000	1000	0	3000	6	3001	0	1	3005	5	1	1	6	0	12778	9089	6807	3157	11	53	20698	3212	3823	10	54	54	28758	16458	13624	15503	3000	29314	29275	29412	29368	29290
63004	29320	219	21	24	0	0	9	1	5002	28855	0	0	0	24169	3000	3000	3000	15000	0	16267	28657	29170	3	10	3000	3000	3000	29126	29099	1	1	61001	1000	1000	0	3000	6	3001	0	4	3004	5	1	1	9	0	12872	9075	6819	2988	10	56	20687	3060	3823	11	53	49	28403	16384	13617	15736	3000	29293	29398	29450	29319	29443
63004	29342	219	18	23	0	0	1	0	4878	28874	0	0	0	24063	3000	3000	3000	15003	1	16232	28849	29365	3	10	3000	3000	3000	29191	29243	1	1	61001	1000	1000	0	3000	6	3003	0	1	3002	5	1	4	9	0	12879	9405	6791	3056	7	55	20588	3065	3828	14	57	47	28402	16195	13666	15455	3000	29295	29219	29314	29166	29416
63004	29458	220	21	16	0	0	9	0	4555	28857	0	0	0	24152	3000	3000	3000	15002	3	16156	28623	29233	3	10	3000	3000	3000	29220	29194	1	1	61001	1000	1000	0	3000	9	3003	0	4	3003	5	1	1	6	0	13117	9104	6830	3154	7	53	20599	3053	3823	15	54	55	28419	16467	13748	15429	3000	29270	29352	29234	29295	29349
63004	29328	220	18	20	0	0	7	1	4557	28849	0	0	2	24122	3000	3000	3000	15000	0	16277	28705	29295	3	10	3000	3000	3000	29214	29102	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	0	1	9	0	12866	9100	6816	3026	8	50	20706	3041	3820	14	53	54	28351	16482	13534	15484	3000	29206	29259	29238	29330	29257
63004	29451	219	21	26	0	0	1	0	4664	28893	0	0	0	24197	3000	3000	3000	15000	0	16153	28676	29329	3	10	3000	3000	3000	29081	29238	1	1	61001	1000	1000	0	3000	9	3005	0	1	3001	5	0	1	6	0	12868	9232	6839	3082	8	52	20613	3137	3815	11	56	57	28430	16396	13642	15530	3000	29257	29299	29275	29224	29394

Count: 8

Code:

  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80071	599	1	1	1	0	0	1	0	68	0	1	0	2	80055	3	7	7	19	25	240100	100	240000	100	240000	500	3504361	0	80150	0	80048	80048	49992	15	50005	240100	200	240000	200	240000	80061	80061	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240040	0	0	0	39	240039	5	1	0	43	0	0	0	5110	2	16	2	2	80062	0	10	10	7	240000	100	80066	80066	80041	80072	80066
240204	80064	600	0	0	0	0	0	0	0	53	0	0	0	1	80050	2	1	0	20	25	240100	100	240000	100	240000	500	3537804	0	80042	0	80065	80065	49988	3	50019	240100	200	240000	200	240000	80040	80063	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	0	0	240000	0	0	0	38	240038	6	0	0	44	0	0	0	5110	2	16	2	2	80062	0	14	10	7	240000	100	80066	80066	80066	80062	80041
240204	80065	599	0	0	0	0	0	0	0	44	0	0	0	0	80025	2	0	1	20	25	240100	100	240000	100	240000	500	3495436	1	80037	0	80040	80040	49988	3	49998	240100	200	240000	200	240000	80064	80040	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240000	0	1	0	38	240038	5	0	39	44	0	0	0	5110	2	16	2	2	80063	2	10	10	0	240000	100	80066	80062	80066	80041	80062
240204	80064	599	0	0	0	0	0	0	0	0	0	0	0	1	80046	0	1	12	0	25	240100	100	240000	100	240000	500	3519717	0	80061	0	80070	80070	49971	3	50028	240100	200	240000	200	240216	80069	80048	1	1	80201	100	99	0	100	100	80000	80000	0	100	240020	19	43	0	240019	1	0	1	21	240000	0	1	59	43	19	0	0	5110	2	16	2	2	80067	0	0	13	0	240000	100	80070	80070	80071	80070	80049
240204	80070	600	1	1	0	0	0	0	0	67	0	0	0	0	80055	2	0	7	20	25	240100	100	240000	100	240000	500	3503429	0	80053	0	80048	80048	49970	3	50028	240100	200	240000	200	240000	80069	80069	2	1	80201	100	99	0	100	100	80000	80000	0	100	240020	20	43	0	240059	0	1	0	63	240041	0	1	59	43	19	0	0	5110	2	16	2	2	80066	0	13	13	5	240000	100	80070	80050	80071	80049	80070
240204	80069	600	1	0	1	0	0	0	0	21	0	1	0	3	80055	3	0	0	20	25	240100	100	240000	100	240000	500	3486289	1	80176	0	80050	80048	49992	3	50006	240100	200	240000	200	240000	80047	80070	1	1	80201	100	99	0	100	100	80000	80000	0	100	240021	19	43	0	240060	0	0	1	62	240041	0	1	60	43	19	2	0	5110	2	16	2	2	80044	0	13	13	5	240000	100	80049	80071	80070	80049	80049
240204	80069	600	1	0	0	1	0	0	0	21	0	0	1	2	80055	0	0	7	20	25	240100	100	240000	100	240000	500	3486289	1	80059	0	80069	80048	49970	3	50028	240100	200	240000	200	240000	80069	80048	1	1	80201	100	99	0	100	100	80000	80000	0	100	240019	20	43	0	240019	0	0	1	61	240041	5	1	59	43	19	1	0	5110	2	16	2	2	80067	0	0	13	5	240000	100	80071	80070	80049	80071	80070
240204	80048	599	1	0	1	1	0	0	0	67	0	0	0	3	80054	2	0	7	20	25	240100	100	240000	100	240000	500	3501095	1	80058	0	80069	80069	49992	3	50027	240100	200	240000	200	240000	80048	80070	1	1	80201	100	99	0	100	100	80000	80000	1	100	240020	19	43	0	240019	0	0	1	62	240040	5	1	19	43	19	1	1	5110	2	16	2	2	80045	0	0	13	5	240000	100	80049	80049	80071	80071	80079
240204	80048	599	1	1	1	1	0	0	0	66	0	0	0	3	80054	0	7	0	19	25	240100	100	240000	100	240000	500	3503429	1	80057	0	80069	80069	49970	3	50006	240100	200	240000	200	240000	80070	80070	1	1	80201	100	99	0	100	100	80000	80000	0	100	240019	19	0	0	240059	1	0	0	62	240000	5	1	60	43	18	0	0	5110	2	16	2	2	80066	0	13	13	5	240000	100	80070	80070	80071	80071	80049
240204	80069	600	1	1	0	0	0	1	0	67	0	0	0	0	80033	3	9	7	19	25	240100	100	240000	100	240000	500	3520953	1	80057	0	80048	80048	49992	3	50027	240100	200	240000	200	240000	80069	80069	1	1	80201	100	99	0	100	100	80000	80000	0	100	240021	19	0	0	240060	1	0	2	62	240000	5	0	60	43	19	0	0	5110	2	16	2	2	80067	0	0	13	5	240000	100	80048	80070	80071	80070	80070

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80398	599	0	0	0	0	0	1	0	0	80069	2	12	12	19	51	240010	10	240000	10	240000	50	3538494	0	80036	0	80068	80071	50119	3	50021	240010	20	240000	20	240000	80061	80041	1	1	80021	10	9	10	10	80000	80000	0	10	240000	43	0	240040	1	0	62	240040	5	1	40	43	5020	0	0	5	16	4	6	80058	0	14	0	4	240000	10	80042	80066	80062	80062	80061
240024	80070	600	0	0	0	0	45	0	0	0	80026	2	12	0	0	25	240010	10	240000	10	240000	50	3528609	0	80036	0	80061	80061	50006	3	50021	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	1	10	240000	43	0	240040	0	0	39	240040	5	1	40	0	5020	0	0	6	16	2	4	80058	0	10	10	4	240000	10	80042	80065	80042	80062	80042
240024	80061	599	0	0	0	0	45	1	0	0	80046	2	0	12	16	25	240010	10	240000	10	240000	50	3523026	0	80016	0	80061	80061	50006	3	50040	240010	20	240192	20	240000	80041	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	0	240000	1	0	40	240039	5	1	0	43	5020	0	0	5	16	5	2	80038	0	10	10	4	240000	10	80062	80042	80042	80066	80066
240024	80068	600	0	1	0	0	54	1	0	1	80046	2	12	12	20	25	240010	10	240000	10	240000	50	3521785	0	80036	0	80061	80065	50006	3	50041	240010	20	240000	20	240000	80061	80061	1	1	80022	10	9	10	10	80000	80000	0	10	240000	43	0	240000	0	0	40	240039	5	1	40	43	5020	0	0	2	16	2	4	80038	0	14	10	4	240000	10	80065	80062	80042	80042	80042
240024	80362	600	0	0	0	0	46	0	0	1	80026	2	0	1	16	25	240010	10	240000	10	240000	50	3522117	0	80036	0	80065	80065	50010	3	50041	240010	20	240000	20	240000	80061	80041	1	1	80021	10	9	10	10	80000	80000	0	10	240000	43	0	240040	0	0	40	240039	5	1	40	0	5020	0	0	2	16	4	6	80058	0	10	0	4	240000	10	80073	80064	80042	80062	80042
240024	80347	601	0	0	0	0	45	1	0	1	80055	2	12	1	20	25	240010	10	240000	10	240000	50	3510227	0	80036	0	80061	80061	50006	3	50041	240010	20	240000	20	240000	80061	80041	1	1	80021	10	9	10	10	80000	80000	0	10	240000	43	0	240040	0	0	40	240039	5	1	0	44	5020	0	0	4	16	4	3	80057	0	10	10	4	240000	10	80066	80042	80062	80062	80042
240024	80061	600	0	0	0	0	45	1	0	0	80046	2	1	1	0	25	240010	10	240000	10	240000	50	3522380	0	80040	3	80065	80065	49986	3	50021	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	43	0	240000	0	0	40	240040	0	1	40	43	5020	0	0	2	16	3	4	80058	0	10	10	0	240000	10	80062	80042	80042	80062	80062
240024	80358	600	0	0	0	0	0	0	0	1	80046	2	12	12	0	25	240010	10	240000	11	240000	50	3511263	0	80016	0	80065	80041	50006	3	50041	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	43	0	240039	0	0	40	240040	6	1	40	0	5020	0	0	4	16	5	5	80057	0	10	10	0	240000	10	80061	80062	80062	80062	80066
240024	80371	601	1	1	0	0	45	0	0	1	80046	2	0	12	16	25	240010	10	240000	10	240000	50	3490485	0	80036	0	80061	80061	49986	3	50041	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	0	240000	0	0	286	240040	5	0	0	0	5036	0	0	6	16	6	4	80057	0	10	10	4	240000	10	80042	80042	80042	80042	80062
240024	80356	601	0	0	0	1	0	0	0	0	80053	2	12	12	16	25	240010	10	240000	10	240000	50	3531036	0	80016	0	80061	80065	49986	3	50045	240010	20	240000	20	240000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	240000	43	131	240039	0	0	40	240039	0	1	40	43	5020	0	0	4	16	4	2	80058	0	0	10	4	240000	10	80062	80062	80062	80066	80063

LD1 (multiple, 3 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations