Firestorm: LD1 (multiple, 3 regs, 2S) measurements

Code:

  ld1 { v0.2s, v1.2s, v2.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	09	0e	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	29340	219	7	1	0	5	1	0	4524	28823	0	0	0	24163	2000	2000	2000	10000	7	16177	28591	29212	3	10	2000	3000	2000	29134	29132	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	6	0	0	4	12982	9313	6891	3081	3	74	20656	3109	3814	16	54	56	28349	16062	13589	15339	2000	1000	29297	29357	29302	29399	29342
63004	29374	220	5	0	0	10	1	0	4662	28862	0	0	0	24257	2000	2000	2000	10000	5	16175	28611	29242	3	10	2000	3000	2000	29163	29066	1	1	61001	1000	1000	0	2000	4	2000	0	3	2000	4	0	0	4	12866	9546	6898	3139	0	59	20623	3448	3815	15	54	56	28509	16424	13036	15570	2000	1000	29268	29411	29411	29257	29385
63004	29353	219	4	0	0	4	1	0	4517	28786	0	2	0	24202	2000	2000	2000	10000	10	16164	28789	29301	3	10	2000	3000	2000	29182	29119	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	0	4	13098	9177	6920	3087	3	58	20661	3092	3816	12	57	68	28338	16206	13561	15877	2000	1000	29381	29186	29297	29258	29301
63004	29246	220	5	0	0	4	1	0	4526	29047	0	0	1	24190	2000	2000	2000	10000	7	16185	28610	29306	3	10	2000	3000	2000	29080	29231	1	1	61002	1000	1000	0	2000	4	2000	0	0	2000	4	0	0	6	13111	9264	6915	3146	1	57	20584	3048	3809	13	55	58	28356	16274	13752	15386	2000	1000	29242	29252	29288	29256	29313
63004	29331	219	3	0	0	2	1	0	4708	28841	0	0	0	24091	2000	2000	2000	10000	8	16168	28730	29301	3	10	2000	3000	2000	29219	29215	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	0	4	13126	9070	6924	3087	0	59	20596	3027	3812	7	54	54	28406	16435	13727	15755	2000	1000	29249	29239	29278	29283	29330
63004	29366	220	2	0	0	54	1	0	4530	28850	0	2	0	24243	2000	2000	2000	10001	5	16179	28674	29263	3	10	2000	3000	2000	29151	29128	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	0	4	12942	8999	6887	3116	1	57	20593	3070	3815	13	61	58	28376	16164	13894	15697	2000	1000	29345	29256	29285	29280	29293
63004	29334	221	7	0	0	5	1	0	4538	28825	0	0	1	24270	2000	2000	2000	10000	0	16160	28935	29210	3	10	2000	3000	2000	29086	29149	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	6	0	0	4	12980	9035	6814	3144	0	58	20571	3106	3811	13	62	65	28334	16469	13811	15673	2000	1000	29383	29256	29295	29311	29335
63004	29383	220	6	0	0	0	1	0	4612	28911	0	0	0	24205	2000	2000	2000	10000	1	16148	28672	29340	3	10	2000	3000	2000	29247	29176	1	1	61001	1000	1000	0	2000	4	2000	0	1	2000	4	0	0	4	13060	9145	6884	3074	2	50	20645	3055	3816	10	59	52	28537	16144	13532	15523	2000	1000	29355	29274	29362	29242	29299
63004	29386	220	6	0	0	0	1	0	4636	28870	0	0	2	24193	2000	2000	2000	10000	3	16182	28876	29319	3	10	2000	3000	2000	29172	29187	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	0	4	12894	9172	6819	3149	0	60	20636	3088	3816	13	57	53	28315	16186	13624	15428	2000	1000	29323	29114	29305	29331	29179
63004	29339	219	3	0	0	4	1	0	4882	28813	0	0	0	24118	2000	2000	2000	10000	7	16159	28643	29304	3	10	2000	3000	2000	29144	29090	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	0	6	13100	9185	6932	3142	0	64	20738	3100	3811	10	61	54	28477	16336	13650	15671	2000	1000	29369	29318	29311	29326	29429

Count: 8

Code:

  ld1 { v0.2s, v1.2s, v2.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	53400	400	1	1	1	0	0	65	1	0	0	53366	2	18	18	0	25	160100	100	160000	100	160018	500	2336168	0	53374	53399	53381	23325	7	23607	160117	200	240040	200	160021	53381	53381	1	1	80201	100	99	100	100	80000	80000	1	100	160020	20	42	160057	0	0	0	59	160038	6	1	57	42	19	1	1	1	1	5117	1	16	1	1	53378	0	0	2	160000	80000	100	53399	53382	53400	53400	53400
240204	53399	400	1	0	1	0	0	65	1	0	2	53366	0	18	18	16	25	160100	100	160000	100	160017	500	2334261	1	53356	53398	53381	23325	8	23590	160115	200	240032	200	160021	53398	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160021	20	42	160057	1	0	0	59	160000	6	1	57	42	19	1	1	1	1	5117	1	16	1	1	53378	9	0	0	160000	80000	100	53399	53382	53400	53382	53400
240204	53381	400	1	0	0	0	0	65	0	0	3	53366	0	18	18	16	25	160100	100	160000	100	160015	500	2334114	1	53374	53381	53381	23324	8	23350	160117	200	240040	200	160027	53398	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160020	19	0	160057	1	0	1	58	160038	6	0	57	0	19	0	1	1	1	5117	1	16	1	1	53396	9	9	0	160000	80000	100	53400	53400	53382	53400	53399
240204	53381	399	1	0	1	0	0	65	0	0	2	53384	2	18	0	16	25	160100	100	160000	100	160016	500	2358311	0	53374	53414	53385	23324	8	23378	160117	200	240032	200	160021	53381	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160019	21	41	160058	1	1	1	59	160038	6	1	19	42	19	0	1	1	1	5117	1	16	1	1	53396	9	9	2	160000	80000	100	53400	53400	53400	53382	53399
240204	53398	400	1	1	0	0	0	65	0	0	2	53384	0	0	18	0	25	160100	100	160000	100	160013	500	2358163	1	53374	53398	53398	23325	8	23625	160113	200	240032	200	160021	53381	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160020	19	0	160057	1	0	0	59	160038	0	1	57	42	19	2	1	1	1	5117	1	16	1	1	53378	9	9	2	160000	80000	100	53382	53399	53382	53400	53382
240204	53381	399	1	1	1	0	0	65	1	0	2	53383	0	18	18	16	25	160100	100	160130	100	160016	500	2339757	0	53356	53399	53398	23325	7	23627	160117	200	240032	200	160027	53399	53381	1	1	80201	100	99	100	100	80000	80000	0	100	160019	20	0	160019	0	0	1	59	160038	6	1	57	42	19	0	1	1	1	5117	1	16	1	1	53395	0	0	2	160000	80000	100	53400	53382	53382	53400	53583
240204	53398	400	1	1	1	0	0	21	1	0	2	53385	2	18	18	1	25	160100	100	160000	100	160016	500	2358307	0	53374	53399	53399	23325	8	23582	160114	200	240040	200	160021	53383	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160021	20	42	160019	0	0	0	21	160038	6	1	57	0	19	1	1	1	1	5117	1	16	1	1	53396	9	0	0	160000	80000	100	53382	53382	53405	53400	53399
240204	53399	400	1	1	1	0	0	65	0	0	0	53383	2	0	0	16	25	160100	100	160000	100	160016	500	2334114	0	53374	53381	53398	23324	8	23601	160117	200	240040	200	160027	53399	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160019	21	0	160057	1	1	1	59	160000	0	0	57	42	19	1	1	1	1	5117	1	16	1	1	53378	9	9	2	160000	80000	100	53382	53399	53382	53399	53399
240204	53401	400	1	1	1	0	0	64	0	0	2	53384	2	18	18	16	25	160100	100	160000	100	160018	500	2336168	0	53374	53399	53381	23324	7	23381	160115	200	240032	200	160027	53381	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160019	20	42	160019	1	0	0	59	160038	6	1	57	42	19	0	1	1	1	5118	1	16	1	1	53378	0	9	0	160000	80000	100	53400	53382	53400	53382	53382
240204	53399	400	1	1	0	0	0	74	0	0	2	53384	1	0	18	0	25	160100	100	160000	100	160014	500	2340370	0	53465	53381	53399	23325	8	23607	160113	200	240032	200	160021	53399	53399	1	1	80201	100	99	100	100	80000	80000	1	100	160020	19	0	160057	0	0	1	59	160038	6	0	67	42	19	1	1	1	1	5117	1	16	1	1	53396	9	9	2	160000	80000	100	53400	53400	53382	53399	53382

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	53400	400	1	0	1	0	0	0	0	0	0	0	103	0	0	0	2	53366	2	18	0	1	25	160010	10	160000	10	160000	50	2353389	1	0	53356	53399	53381	23326	3	23361	160010	20	240000	20	160000	53399	53398	1	1	80021	10	9	0	10	10	80000	80000	0	10	160020	21	42	0	160019	0	0	0	21	160038	6	1	57	0	19	0	0	5020	0	0	22	16	22	22	53395	0	9	9	0	160000	80000	10	53400	53399	53400	53399	53400
240024	53399	400	1	0	0	1	0	0	0	0	0	0	104	0	1	0	3	53383	2	0	18	15	25	160010	10	160000	10	160000	50	2334036	0	0	53374	53381	53381	23343	3	23380	160010	20	240000	20	160000	53399	53398	1	1	80021	10	9	0	10	10	80000	80000	0	10	160020	20	0	0	160057	1	0	1	59	160038	6	1	19	0	19	1	0	5020	0	0	11	16	23	14	53378	0	0	9	2	160000	80000	10	53400	53382	53382	53382	53382
240024	53399	400	1	0	1	1	0	1	0	0	0	0	377	0	1	0	3	53383	2	0	18	15	25	160010	10	160000	10	160000	50	2358091	1	0	53356	53398	53381	23343	3	23394	160010	20	240000	20	160000	53399	53381	1	1	80021	10	9	0	10	10	80000	80000	0	10	160019	19	42	0	160019	0	0	0	59	160038	6	1	57	42	19	2	0	5020	0	0	26	16	24	25	53396	0	9	9	2	160000	80000	10	53400	53399	53399	53400	53382
240024	53399	400	1	0	0	1	0	2	0	0	0	0	423	0	1	0	2	53383	0	18	18	15	25	160010	10	160000	10	160000	50	2358091	1	0	53374	53399	53381	23343	3	23429	160010	20	240000	20	160000	54942	55244	13	1	80021	10	9	0	10	10	80000	80000	0	10	161845	19	42	406	161879	2	1	6	10769	161690	6	0	57	42	19	3	0	5255	0	0	45	134	20	25	55162	0	9	9	2	160000	80000	10	55582	55397	55545	55527	55558
240024	54478	414	1	2	0	2	0	0	0	0	13	14	1913	1144	1	0	4	53538	0	18	18	1	25	160010	10	160000	10	160000	50	2344930	0	0	55131	55530	55407	24456	150	24874	162504	20	243757	22	162697	55400	55666	14	1	80021	10	9	0	10	10	80000	80000	0	10	161715	19	42	397	161879	0	0	0	10717	161858	6	1	57	41	19	3	0	5253	0	0	30	142	25	29	55289	2	0	9	2	160000	80000	10	55551	55559	55494	55390	55538
240024	55536	416	1	0	2	0	0	0	0	0	23	21	3058	1936	1	0	3	56905	2	18	18	1818	696	163001	14	162990	12	163204	55	2447004	0	0	55931	56292	56177	24930	216	25473	162326	20	243758	20	162501	54784	53399	1	1	80021	10	9	0	10	10	80000	80000	1	10	160019	20	42	380	160187	2	1	2	64	161728	6	1	19	42	19	4	0	5020	0	0	13	16	26	28	53540	0	9	9	2	160000	80000	10	56008	55705	55242	55529	55848
240024	56587	439	1	2	0	2	3	2	0	0	0	0	119	0	0	0	2	56004	2	18	0	16	25	160010	10	160130	11	163382	73	2423317	0	0	55516	55847	55853	24735	180	24819	163037	20	245190	20	163078	54434	53399	1	1	80021	10	9	0	10	10	80000	80000	1	10	160020	19	0	346	160189	1	0	0	59	160038	6	1	57	40	19	1	0	5020	0	0	24	16	26	25	53691	0	0	9	2	160000	80000	10	53418	53386	53407	53407	53400
240024	53399	413	1	0	0	0	0	1	1	1	0	0	113	0	0	0	2	53390	0	7	7	0	25	160010	10	160000	10	160000	50	2334036	0	0	53378	53381	53381	23348	3	23383	160010	20	240000	20	160000	53403	53402	1	1	80021	10	9	0	10	10	80000	80000	0	10	160019	20	0	0	160059	0	0	2	61	160040	6	1	59	43	19	0	0	5020	0	0	24	16	13	23	53399	0	13	13	5	160000	80000	10	53404	53382	53404	53382	53404
240024	53381	400	1	0	1	0	0	0	0	0	0	0	94	0	0	0	2	53387	0	0	0	19	25	160010	10	160000	10	160000	50	2331246	0	0	53378	53381	53381	23326	3	23383	160010	20	240000	20	160000	53403	53402	1	1	80021	10	9	0	10	10	80000	80000	1	10	160020	20	0	0	160019	0	0	0	64	160000	6	1	59	43	19	0	0	5020	0	0	26	16	26	25	53400	0	13	13	5	160000	80000	10	53404	53404	53404	53382	53404
240024	53381	399	1	0	0	0	0	1	1	1	0	0	483	0	0	0	3	53388	3	7	7	20	25	160010	10	160000	10	160000	50	2359124	0	0	53377	53403	53403	23347	3	23382	160010	20	240000	20	160000	53657	53458	1	1	80021	10	9	0	10	10	80000	80000	1	10	160020	20	43	0	160058	0	0	2	22	160039	0	0	59	0	19	2	0	5020	0	0	20	16	24	12	53378	0	13	13	5	160000	80000	10	53403	53382	53403	53382	53404

LD1 (multiple, 3 regs, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations