Firestorm: LD1 (multiple, 3 regs, 4H) measurements

Code:

  ld1 { v0.4h, v1.4h, v2.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	29269	219	0	17	0	9	0	0	0	7	1	4589	28876	0	0	0	24071	2000	2000	2000	10005	3	16142	28565	29251	3	10	2000	3000	2000	29060	29111	1	1	61001	1000	1000	0	2000	0	4	2000	0	3	2	6	2000	4	0	6	0	0	12834	9181	6833	3059	5	43	20614	3038	3816	5	26	33	28389	16426	13781	15528	2000	1000	29201	29181	29233	29209	29328
63004	29252	219	0	9	0	8	0	0	0	7	1	4742	28887	0	2	0	24136	2000	2000	2000	10000	4	16162	28513	29277	3	10	2000	3000	2000	29107	29126	1	1	61001	1000	1000	0	2000	0	4	2000	0	6	0	0	2000	4	0	4	0	0	12882	9114	6827	3109	5	29	20603	3066	3812	9	29	28	28417	16370	13707	15625	2000	1000	29254	29288	29322	29196	29294
63004	29297	219	0	12	0	11	0	0	0	0	1	4497	28840	0	0	1	24145	2000	2000	2000	10000	5	16152	28600	29303	3	10	2000	3000	2000	29140	29107	1	1	61001	1000	1000	0	2000	0	6	2000	0	0	0	2	2000	4	0	2	0	0	12854	9207	6863	3028	5	29	20563	3083	3816	12	31	31	28418	16346	13840	15598	2000	1000	29299	29290	29289	29139	29254
63004	29267	220	0	11	0	11	0	0	0	5	1	4609	28795	0	0	0	24223	2000	2000	2000	10000	2	16156	28667	29271	3	10	2000	3000	2000	29150	29149	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	0	2000	2	0	4	0	0	12817	9261	6884	2999	7	37	20595	3117	3815	8	28	34	28456	16121	13721	15585	2000	1000	29210	29234	29242	29289	29269
63004	29306	220	0	13	0	11	0	0	0	7	1	4630	28825	0	0	0	24167	2000	2000	2000	10000	1	16133	28636	29340	3	10	2000	3000	2000	29155	29096	1	1	61001	1000	1000	0	2000	0	2	2000	0	0	0	2	2000	4	0	4	0	0	12959	9113	6813	3071	1	33	20555	3084	3816	7	31	30	28392	16515	13817	15464	2000	1000	29251	29295	29243	29217	29283
63004	29183	219	0	10	0	11	0	0	0	5	1	4568	28845	0	0	1	24234	2000	2000	2000	10000	0	16141	28633	29251	3	10	2000	3000	2000	29078	29056	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	0	2000	4	0	2	0	0	12833	9318	6820	3053	4	32	20582	3057	3815	8	30	29	28486	16495	13625	15856	2000	1000	29274	29212	29325	29274	29244
63004	29233	219	0	9	0	6	0	0	0	5	1	4579	28830	0	0	0	24212	2000	2000	2000	10000	6	16134	28632	29288	3	10	2000	3000	2000	29156	29171	1	1	61001	1000	1000	0	2000	0	4	2002	0	1	0	0	2004	4	0	2	0	0	12944	9173	6865	3061	7	29	20573	3056	3813	9	35	34	28365	16459	13732	15747	2000	1000	29241	29313	29315	29236	29256
63004	29281	218	0	15	0	11	0	0	0	5	1	4639	28846	0	0	0	24153	2000	2000	2000	10000	0	16156	28530	29171	3	10	2000	3000	2000	29165	29120	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	0	2000	4	0	2	0	0	12860	9063	6818	3055	3	34	20640	3029	3811	8	28	21	28442	16275	13556	15626	2000	1000	29268	29272	29248	29256	29258
63004	29300	220	0	12	0	16	0	0	1	5	1	4532	28905	0	1	0	24155	2000	2000	2000	10000	7	16154	28599	29229	3	10	2000	3000	2000	29082	29079	1	1	61001	1000	1000	0	2000	0	2	2000	0	1	0	2	2000	4	0	2	0	0	12824	8999	6868	3016	2	31	20612	3054	3816	10	27	25	28414	16556	13677	15534	2000	1000	29225	29217	29284	29229	29272
63004	29175	220	0	9	0	10	0	0	0	5	1	4613	28788	0	0	0	24141	2000	2000	2000	10000	3	16141	28598	29173	3	10	2000	3000	2000	29144	29132	1	1	61001	1000	1000	0	2000	0	6	2000	0	0	0	0	2000	4	0	4	0	0	12779	9089	6848	3027	5	36	20615	3179	3816	8	26	27	28390	16444	13693	15671	2000	1000	29260	29235	29241	29233	29342

Count: 8

Code:

  ld1 { v0.4h, v1.4h, v2.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	53400	400	1	0	0	1	1	45	0	1	3	53384	2	18	18	23	25	160100	100	160000	100	160000	500	2345544	1	53378	53389	53392	23319	3	23359	160100	200	240000	200	160000	53399	53402	1	1	80201	100	99	100	100	80000	80000	1	100	160000	19	42	0	160057	1	0	1	63	160038	6	0	35	39	0	0	0	5110	1	16	1	1	53396	14	1	9	2	160000	80000	100	53400	53399	53646	53433	53413
240204	53399	400	1	0	1	0	0	21	0	0	2	53366	2	18	18	83	25	160100	100	160000	100	160000	500	2336625	0	53373	53381	53399	23321	3	23357	160100	200	240000	200	160000	53398	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160020	19	0	0	160019	0	0	0	59	160038	0	0	57	42	19	1	0	5110	1	16	1	1	53395	0	0	9	0	160000	80000	100	53383	53399	53651	53406	53400
240204	53399	400	1	0	0	0	0	22	0	1	2	53383	2	0	18	140	25	160100	100	160000	100	160000	500	2336625	0	53373	53399	53399	23321	3	23356	160100	200	240000	200	160000	53381	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	42	0	160058	0	0	1	21	160038	6	1	57	42	19	1	0	5110	1	16	1	1	53378	0	9	9	2	160000	80000	100	53399	53399	53739	53398	53382
240204	53398	400	1	1	0	0	0	21	0	0	2	53383	2	18	18	38	25	160100	100	160000	100	160000	500	2337315	0	53356	53398	53399	23304	3	23357	160100	200	240000	200	160000	53399	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160020	19	0	0	160057	0	0	1	62	160038	0	1	57	42	19	1	0	5110	1	16	1	1	53396	0	9	9	2	160000	80000	100	53400	53400	53382	53382	53413
240204	53399	400	1	0	0	0	0	65	0	0	0	53384	2	18	18	5	25	160100	100	160000	100	160000	500	2358739	0	53356	53399	53401	23322	3	23356	160100	200	240000	200	160000	53381	53383	1	1	80201	100	99	100	100	80000	80000	0	100	160021	19	42	0	160057	2	0	2	21	160038	6	0	57	42	19	0	0	5110	1	16	1	1	53396	0	9	9	2	160000	80000	100	53400	53400	53654	53414	53400
240204	53399	400	1	1	1	0	0	66	0	0	3	53384	2	18	18	35	25	160100	100	160000	100	160000	500	2334201	0	53373	53399	53399	23322	3	23339	160100	200	240000	200	160000	53399	53381	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	0	0	160057	1	0	0	59	160038	6	0	57	42	19	1	0	5110	1	16	1	1	53395	0	0	9	2	160000	80000	100	53399	53400	53613	53412	53486
240204	53398	400	1	1	1	0	0	21	0	0	2	53383	1	0	18	18	25	160100	100	160000	100	160000	500	2336089	0	53373	53381	53398	23304	3	23339	160100	200	240000	200	160000	53398	53398	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	42	0	160057	0	1	0	21	160038	6	1	19	42	19	1	0	5110	1	16	1	1	53395	0	0	9	2	160000	80000	100	53382	53399	53654	53410	53399
240204	53399	400	1	1	1	0	0	65	0	0	3	53384	2	18	0	22	25	160100	100	160000	100	160000	500	2347194	0	53374	53399	53399	23322	3	23356	160100	200	240000	200	160000	53399	53399	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	0	0	160056	1	1	1	21	160038	6	1	57	42	19	1	0	5110	1	16	1	1	53395	0	0	9	2	160000	80000	100	53399	53400	53643	53409	53400
240204	53381	400	1	0	0	0	0	65	0	0	3	53384	2	0	18	91	25	160100	100	160000	100	160000	500	2334201	0	53373	53399	53399	23322	3	23357	160100	200	240000	200	160000	53399	53381	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	0	0	160057	1	0	2	59	160038	6	1	57	42	19	0	0	5110	1	16	1	1	53396	0	9	9	2	160000	80000	100	53400	53399	53656	53394	53399
240204	53381	400	1	1	1	0	0	65	0	0	3	53366	2	18	18	130	25	160100	100	160000	100	160000	500	2334201	0	53373	53381	53399	23321	3	23357	160100	200	240000	200	160000	53398	53381	1	1	80201	100	99	100	100	80000	80000	0	100	160019	19	42	0	160057	0	0	0	59	160038	6	1	57	42	19	0	0	5110	1	16	1	1	53375	0	6	6	2	160000	80000	100	53375	53400	53623	53425	53400

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6674

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	53394	400	0	1	0	0	0	0	45	0	1	0	1	53379	2	12	12	23	25	160010	10	160000	10	160000	50	2358180	0	0	53369	53395	53394	23339	3	23374	160010	20	240000	20	160000	53394	53394	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	43	0	160039	0	0	39	160039	6	1	0	43	0	5020	0	12	16	0	0	10	9	53423	0	10	0	4	160000	80000	10	53407	53404	53395	53395	53395
240024	53394	400	0	0	0	0	0	0	45	0	0	0	1	53379	0	0	12	16	25	160010	10	160000	10	160000	50	2345544	0	0	53369	53394	53394	23319	3	23374	160010	20	240000	20	160000	53374	53374	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	43	33	160039	0	0	39	160039	6	1	39	43	0	5020	0	8	16	0	0	10	8	53391	0	10	10	4	160000	80000	10	54008	53410	53395	53399	53395
240024	53394	400	0	0	0	0	0	0	45	0	1	0	1	53379	2	12	12	16	25	160010	10	160000	10	160000	50	2345544	0	0	53349	53394	53394	23339	3	23374	160010	20	240000	20	160000	53394	53394	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	43	0	160039	0	0	39	160039	6	1	39	43	0	5020	0	10	16	0	0	11	8	53391	0	10	0	4	160000	80000	10	53406	53408	53395	53395	53399
240024	53394	400	0	0	0	0	0	0	45	0	1	0	1	53379	2	12	12	16	25	160010	10	160000	10	160000	50	2358180	0	0	53369	53394	53394	23339	3	23374	160010	20	240000	20	160000	53394	53394	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	0	0	160039	0	0	0	160000	6	0	39	43	0	5020	0	9	16	0	0	8	10	53391	0	10	10	4	160000	80000	10	53405	53388	53395	53375	53411
240024	53394	399	0	0	0	0	0	0	45	0	1	0	1	53359	2	12	12	23	25	160010	10	160000	10	160000	50	2352959	0	0	53369	53394	53394	23339	3	23354	160010	20	240000	20	160000	53394	53394	1	1	80021	10	9	10	10	80000	80000	1	10	161692	0	43	377	161733	1	0	9795	161729	0	1	39	43	0	5235	0	16	133	0	0	18	14	54452	2	10	0	4	160000	80000	10	55531	55405	55448	55663	55346
240024	54602	414	0	0	0	0	13	14	1851	1232	1	0	1	55522	2	0	12	847	403	161832	11	160650	10	160000	50	2337085	0	0	53349	53394	53394	23339	3	23374	160010	20	240000	20	162500	55228	55347	14	1	80021	10	9	10	10	80000	80000	0	10	161694	0	43	400	161081	1	0	10408	161599	0	1	0	43	0	5249	1	15	142	0	0	17	17	55300	1	0	10	4	160000	80000	10	55560	55513	55405	55526	55506
240024	55859	419	0	0	0	0	17	17	2292	1496	0	0	2	56222	2	0	12	1285	521	162224	13	162340	11	163062	56	2428734	0	0	56590	56944	57072	25286	238	25432	163574	20	244905	20	163465	56142	56169	20	1	80021	10	9	10	10	80000	80000	1	10	161690	0	43	0	160039	0	0	0	160039	6	0	39	43	0	5036	0	10	52	0	0	14	14	54610	1	10	10	4	160000	80000	10	53399	53398	53437	53414	53395
240024	55350	443	0	0	0	0	17	15	2160	1408	0	0	0	53379	2	12	12	16	25	160010	10	161430	13	160000	50	2352959	0	0	53370	53395	53395	23319	3	23354	160010	20	240000	20	160000	53374	53394	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	43	0	160039	1	0	3	160039	6	1	39	43	0	5020	0	9	16	0	0	10	10	53391	0	10	10	4	160000	80000	10	55867	55847	55645	55421	56169
240024	56217	433	0	0	0	0	19	18	45	0	0	0	1	53380	2	12	12	0	25	160010	10	160000	10	160195	50	2337327	0	0	53349	53394	53394	23339	3	23374	160010	20	240000	20	160000	53394	53374	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	43	0	160000	0	0	39	160039	6	0	39	43	0	5020	0	9	16	0	1	10	8	53391	0	10	10	4	160000	80000	10	53395	53395	53395	53395	53395
240024	53394	399	0	0	0	0	0	0	0	0	1	0	1	53359	0	12	0	16	25	160010	10	160000	10	160000	50	2352959	0	0	53369	53394	53394	23339	3	23374	160010	20	240000	20	160000	53374	53394	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	43	0	160039	0	0	42	160039	0	1	39	43	0	5020	0	12	16	0	0	11	11	53384	0	10	10	7	160000	80000	10	53397	53395	53395	53395	53395

LD1 (multiple, 3 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations