Firestorm: LD1 (multiple, 3 regs, 4S) measurements

Code:

  ld1 { v0.4s, v1.4s, v2.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0e	0f	1e	1f	22	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
63005	28462	213	4	2	0	1	0	0	30	0	0	5128	28147	0	2	2	22978	3000	3000	3000	15000	3	16172	28132	28548	3	10	3000	3000	3000	28521	28124	1	1	61001	1000	1000	1	3000	6	3001	0	1	3001	5	1	4	6	13166	10336	7259	3192	1	49	19621	3231	3816	12	41	39	27915	14111	11974	12954	3000	28514	28657	28369	28447	28193
63004	27940	213	0	0	1	1	0	0	57	0	1	5161	28063	0	0	3	23597	3000	3000	3000	15000	0	16177	28005	28619	3	10	3000	3000	3000	28023	28257	1	1	61001	1000	1000	1	3000	6	3001	0	0	3001	5	1	7	6	13242	9481	7267	3370	0	35	19425	3294	3816	13	41	38	27779	13858	12125	13330	3000	28099	28167	28292	28059	28003
63004	27975	211	0	2	0	1	0	0	54	0	1	5253	28219	2	0	0	22962	3000	3000	3000	15000	1	16179	28171	28548	3	10	3000	3000	3000	27970	28488	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	1	3	6	13504	10448	7314	3449	1	37	19429	3513	3818	7	29	38	27808	13821	12846	14717	3000	28197	28515	28233	28057	28486
63004	28042	211	0	1	0	1	0	0	45	0	0	4827	27970	2	2	0	23267	3000	3000	3000	15000	3	16157	28013	28316	3	10	3000	3000	3000	28325	28012	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	1	1	6	13838	9630	7313	3195	0	43	19494	3465	3817	13	33	39	28058	14007	12810	13147	3000	28238	28486	28230	28162	28503
63004	28509	213	1	1	0	1	0	0	624	108	1	5274	28408	2	0	0	22917	3000	3000	3000	15000	1	16172	27929	28557	3	10	3000	3000	3000	28371	28089	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	1	4	6	14269	10323	7292	3464	0	30	19919	3482	3821	11	40	36	28037	15151	11987	13091	3000	28072	28355	28162	28098	28155
63004	28541	213	0	1	0	1	0	0	21	0	0	4829	27973	2	0	0	23368	3000	3000	3000	15000	0	16168	27907	28411	3	10	3000	3000	3000	28479	28177	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	1	4	6	14164	10275	7170	3303	0	30	19441	3485	3818	10	32	41	27823	14071	12761	12955	3000	28118	28308	28124	28257	28213
63004	28038	211	0	1	0	1	0	0	6	0	1	5217	27871	2	2	0	23024	3000	3000	3000	15000	1	16170	28136	28407	3	10	3000	3000	3000	28492	28072	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	1	4	6	14066	9920	7311	3500	0	42	19689	3378	3817	14	38	34	28100	15091	11848	12823	3000	28099	28455	28161	28059	28136
63004	28288	210	0	1	0	1	0	0	33	0	0	5208	28355	0	0	0	22898	3000	3000	3000	15000	1	16179	27991	28380	3	10	3000	3000	3000	28072	28098	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	1	1	6	13617	9777	7169	3370	0	38	19512	3302	3818	17	39	35	27739	13906	12785	13263	3000	28109	28076	28040	28172	28088
63004	28546	210	1	1	0	1	0	0	42	0	1	5292	28245	0	0	0	22858	3000	3000	3000	15000	1	16171	27839	28337	3	10	3000	3000	3000	28641	28129	1	1	61001	1000	1000	0	3000	6	3001	0	1	3001	5	1	4	6	14052	10277	7335	3445	0	41	19584	3463	3816	7	37	37	27829	14044	12857	14129	3000	28143	28109	28157	28062	28152
63004	28140	211	0	0	0	1	1	1	48	0	1	5060	27932	2	0	0	22955	3000	3000	3000	15000	5	16155	27864	28384	3	10	3000	3000	3000	28091	28497	1	1	61001	1000	1000	1	3000	6	3001	0	1	3001	5	1	1	6	13309	9801	7022	3329	0	40	19457	3157	3822	7	37	34	27736	13847	11996	13569	3000	28461	28090	28791	28144	28449

Count: 8

Code:

  ld1 { v0.4s, v1.4s, v2.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80056	599	1	0	0	45	1	2	80046	0	12	12	12	25	240100	100	240130	100	240000	500	3495661	0	80018	80071	80046	49984	3	50014	240100	200	240000	200	240000	80040	80056	1	1	80201	100	99	100	100	80000	80000	1	100	240000	0	240000	0	40	240053	5	1	37	40	0	0	5110	1	16	1	1	80037	10	0	4	240000	100	80065	80062	80045	80057	80062
240204	80061	600	0	0	0	0	1	2	80046	3	12	12	16	25	240100	100	240000	100	240000	500	3500303	0	80015	80072	80071	49984	3	50019	240100	200	240000	200	240000	80056	80056	1	1	80201	100	99	100	100	80000	80000	0	100	240000	40	240000	0	39	240040	5	0	37	40	0	0	5110	1	16	1	1	80037	10	0	2	240000	100	80062	80062	80062	80062	80062
240204	80056	599	0	0	0	58	0	2	80041	2	12	12	0	25	240100	100	240000	100	240000	500	3537804	0	80036	80072	80078	49984	3	50019	240100	200	240000	200	240000	80061	80040	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	240040	0	35	240040	0	0	0	40	0	0	5110	1	16	1	1	80058	10	0	4	240000	100	80057	80041	80041	80062	80062
240204	80061	600	0	0	0	0	0	0	80041	2	12	19	16	25	240100	100	240000	100	240000	500	3539192	0	80015	80087	80061	49978	3	49998	240100	200	240000	200	240000	80056	80056	1	1	80201	100	99	100	100	80000	80000	0	100	240000	40	240040	0	0	240130	6	0	0	40	0	0	5110	1	16	1	1	80054	10	6	1	240000	100	80059	80057	80057	80062	80062
240204	80061	600	0	0	0	45	1	2	80041	2	0	19	16	25	240100	100	240000	100	240000	500	3537804	0	80037	80050	80064	49983	3	50019	240100	200	240000	200	240000	80056	80057	1	1	80201	100	99	100	100	80000	80000	0	100	240000	40	240000	0	40	240040	5	1	41	40	0	0	5110	1	16	1	1	80058	10	0	1	240000	100	80062	80062	80062	80057	80041
240204	80040	600	0	0	0	96	0	0	80046	2	12	0	16	25	240100	100	240000	121	240000	500	3495436	0	80036	80064	80056	49984	3	49998	240100	200	240000	200	240000	80040	80056	1	1	80201	100	99	100	100	80000	80000	0	100	240000	43	240037	0	0	240000	5	1	37	0	0	0	5110	1	16	1	1	80040	10	10	0	240000	100	80062	80062	80062	80041	80062
240204	80061	599	0	0	0	75	0	2	80046	0	12	12	16	25	240100	100	240000	100	240000	500	3501773	0	80015	80071	80061	49984	3	50019	240100	200	240000	200	240000	80061	80056	1	1	80202	100	99	100	100	80000	80000	0	100	240000	0	240040	0	55	240000	5	0	39	39	0	0	5110	1	16	1	1	80053	0	6	4	240000	100	80062	80041	80041	80062	80041
240204	80061	600	0	0	0	45	1	1	80046	0	0	12	16	25	240100	100	240000	100	240000	500	3494681	0	80036	80074	80069	49984	3	50019	240100	200	240000	200	240000	80061	80056	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	240037	0	0	240000	5	0	0	40	0	0	5110	1	16	1	1	80058	10	6	0	240000	100	80041	80041	80058	80062	80062
240204	80040	600	0	0	0	46	0	1	80046	2	0	12	0	25	240100	100	240000	100	240000	500	3538480	0	80015	80060	80056	49984	3	50001	240100	200	240000	200	240000	80040	80056	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	240040	0	40	240000	5	0	40	40	0	0	5110	1	16	1	1	80058	10	10	4	240000	100	80041	80062	80041	80041	80062
240204	80040	599	0	0	0	45	1	2	80025	2	0	12	18	25	240100	100	240000	100	240000	500	3495436	0	80103	80052	80056	49984	3	50019	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	1	100	240000	0	240040	0	40	240040	5	1	40	40	0	0	5110	1	16	1	1	80058	10	6	4	240000	100	80041	80062	80062	80057	80062

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80071	600	1	1	1	1	1	0	67	0	0	3	80102	3	7	7	20	25	240010	10	240000	10	240000	50	3527112	1	80023	80069	80047	50206	3	50049	240010	20	240000	20	240000	80047	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	20	43	240019	0	0	0	62	240041	5	1	60	45	19	8	0	5020	1	16	1	1	80280	0	13	13	0	240000	10	80070	80070	80071	80070	80070
240024	80069	600	1	1	0	0	0	0	21	0	0	2	80032	3	7	0	0	25	240010	10	240000	10	240000	50	3521582	1	80044	80081	80069	49992	3	50027	240010	20	240000	20	240000	80070	80047	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	21	0	240060	1	1	1	61	240000	0	0	19	43	19	1	0	5020	1	16	1	1	80066	0	0	13	0	240000	10	80071	80049	80049	80070	80056
240024	80070	600	1	1	0	0	0	0	21	1	0	2	80055	2	9	7	20	25	240010	10	240000	10	240000	50	3500769	1	80045	80086	80070	49993	3	50027	240010	20	240000	20	240000	80072	80070	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	19	43	240019	0	0	0	62	240055	0	0	58	43	19	1	0	5020	1	16	1	1	80067	0	13	13	5	240000	10	80049	80070	80070	80071	80048
240024	80157	601	1	1	1	0	0	0	21	1	0	3	80054	3	0	7	20	25	240010	10	240000	10	240000	50	3533656	0	80022	80081	80071	49999	3	50027	240010	20	240000	20	240000	80047	80070	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	20	43	240060	1	0	1	21	240041	5	1	19	0	19	1	0	5020	1	16	1	1	80044	0	13	13	5	240000	10	80070	80049	80070	80071	80070
240024	80070	599	1	0	1	0	0	0	21	1	0	1	80054	2	0	7	20	25	240010	10	240000	10	240000	50	3501575	0	80023	80083	80082	49993	3	50028	240010	20	240000	20	240192	80089	80057	1	1	80021	10	9	0	10	10	80000	80000	1	10	240019	20	0	240019	1	0	0	21	240039	5	0	60	43	19	0	0	5020	1	16	1	1	80045	0	0	13	5	240000	10	80070	80074	80074	80073	80070
240024	80069	599	1	1	0	0	0	0	99	0	0	2	80032	0	7	9	19	25	240010	10	240000	10	240000	50	3500176	0	80044	80085	80070	50015	3	50028	240010	20	240000	20	240000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240021	19	43	240019	2	0	2	21	240040	6	0	60	43	19	0	0	5020	1	16	1	1	80066	0	13	13	5	240000	10	80161	80071	80071	80049	80070
240024	80070	599	1	1	0	0	0	0	21	1	0	0	80055	3	0	7	18	25	240010	10	240000	10	240000	50	3527112	1	80045	80084	80069	50014	3	50032	240010	20	240000	20	240000	80070	80070	1	1	80021	10	9	0	10	10	80000	80000	0	10	240020	20	43	240057	1	0	0	21	240041	5	0	59	44	19	1	0	5020	1	16	1	1	80066	0	13	13	5	240000	10	80070	80049	80070	80073	80071
240024	80069	605	1	0	0	0	0	0	36	0	0	1	80054	0	7	7	20	25	240010	10	240000	10	240000	50	3521582	0	80046	80083	80047	50017	3	50050	240010	20	240000	20	240000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	20	0	240057	0	0	1	21	240041	5	1	19	43	18	1	0	5020	1	16	1	1	80066	0	13	0	5	240000	10	80070	80070	80071	80070	80070
240024	80070	600	1	0	0	0	0	0	21	1	0	2	80033	3	0	7	20	25	240010	10	240000	10	240000	50	3521582	0	80045	80083	80047	50014	3	50027	240208	20	240000	20	240000	80069	80047	1	1	80021	10	9	0	10	10	80000	80000	0	10	240020	20	43	240060	1	0	1	61	240000	5	1	59	43	19	1	0	5020	1	16	1	1	80044	0	0	0	0	240000	10	80070	80070	80070	80048	80048
240024	80070	600	1	0	1	0	0	0	68	0	0	3	80033	2	0	7	1	25	240010	10	240000	10	240000	50	3501575	0	80023	80078	80069	50015	3	50049	240010	20	240000	20	240000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240019	19	43	240059	1	0	1	62	240040	0	0	60	45	19	1	0	5020	1	16	1	1	80066	0	13	13	5	240000	10	80071	80070	80070	80070	80048

LD1 (multiple, 3 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations