Firestorm: LD1 (multiple, 3 regs, 8H) measurements

Code:

  ld1 { v0.8h, v1.8h, v2.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
63005	29413	220	1	20	1	13	1	0	0	0	0	14	1	0	4614	28774	0	0	0	24082	3000	3000	3000	15002	9	16235	28655	29209	3	10	3000	3000	3000	29055	29066	1	1	61001	1000	1000	1	3005	6	9	3008	1	0	8	3001	5	1	3	0	3	1	13045	9324	6882	3047	10	49	20548	3069	3817	17	42	39	28469	16097	13757	15514	3000	29501	29282	29292	29263	29301
63004	29283	220	0	22	0	17	0	0	0	0	0	6	1	0	4636	28958	0	0	0	24148	3000	3000	3000	15000	6	16150	28599	29335	3	10	3000	3000	3000	29177	29073	1	1	61001	1000	1000	1	3000	0	0	3000	0	0	6	3000	5	1	0	9	0	0	12807	9181	6893	3104	8	40	20629	3051	3816	16	35	36	28482	16453	13542	15548	3000	29300	29203	29297	29293	29238
63004	29204	219	0	13	0	12	0	0	0	0	0	6	1	0	4579	28880	0	0	0	24017	3000	3000	3000	15000	8	16152	28659	29218	3	10	3000	3000	3000	29086	29160	1	1	61001	1000	1000	1	3000	0	9	3000	0	0	1	3004	5	1	4	9	0	0	13044	9308	6863	3134	7	36	20639	3102	3821	15	45	48	28384	16295	13617	15717	3000	29272	29260	29301	29308	29239
63004	29257	219	0	11	0	15	0	0	0	0	2	10	1	0	4487	28883	0	1	0	24106	3000	3000	3000	15000	10	16145	28623	29274	3	10	3000	3000	3000	29055	29252	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	4	3005	0	0	4	0	0	0	13042	9106	6891	3106	8	37	20607	3063	3815	17	40	41	28467	16474	13955	15418	3000	29191	29217	29259	29274	29268
63004	29298	220	0	13	0	11	0	0	0	0	0	23	0	0	4623	28783	0	0	1	24044	3000	3000	3000	15009	11	16154	28557	29233	3	10	3000	3000	3000	29150	29079	1	1	61001	1000	1000	0	3000	0	6	3004	1	0	5	3001	0	1	4	9	0	0	12741	9004	6812	3247	7	40	20639	3105	3820	15	39	41	28356	16250	13656	15320	3000	29337	29136	29242	29370	29293
63004	29326	220	0	16	0	15	0	0	0	0	0	10	0	0	4528	28771	0	0	0	24042	3000	3000	3000	15000	8	16157	28578	29289	3	10	3000	3000	3000	29144	29117	1	1	61001	1000	1000	0	3000	0	9	3004	4	0	4	3004	5	0	5	9	0	0	12784	9353	6945	3122	6	38	20598	3120	3811	14	39	40	28420	16424	13685	15623	3000	29275	29277	29265	29305	29209
63004	29302	220	0	12	0	13	0	0	0	0	0	9	0	0	4534	28848	0	3	0	24106	3000	3000	3000	15000	5	16150	28659	29300	3	10	3000	3000	3000	29023	29086	1	1	61001	1000	1000	0	3000	0	9	3004	1	0	0	3004	5	0	1	9	0	0	12819	9072	6925	3021	5	42	20648	3090	3813	14	39	41	28371	16199	13655	15414	3000	29381	29312	29338	29370	29290
63004	29343	220	0	14	0	13	0	0	0	0	0	12	0	0	4619	28835	0	0	0	24126	3000	3000	3000	15000	7	16157	28631	29189	3	10	3000	3000	3000	29121	29120	1	1	61001	1000	1000	0	3000	0	0	3000	0	0	3	3004	5	0	4	9	0	0	13248	9145	6900	3107	8	39	20649	3111	3819	12	38	38	28404	16204	13787	15452	3000	29202	29257	29208	29254	29342
63004	29284	220	0	15	0	9	0	0	0	0	0	6	1	0	4610	28909	0	1	0	24129	3000	3000	3000	15000	9	16159	28602	29256	3	10	3000	3000	3000	29097	29116	1	1	61001	1000	1000	0	3000	0	9	3001	0	0	0	3000	5	1	5	0	0	0	12782	9137	6862	3043	9	41	20558	3084	3812	11	36	46	28384	16233	13626	15588	3000	29356	29281	29335	29289	29255
63004	29350	219	0	13	0	18	0	0	0	0	0	10	0	0	4576	28767	0	0	0	24076	3000	3000	3000	15001	0	16175	28605	29274	3	10	3000	3000	3000	29155	29083	1	1	61001	1000	1000	0	3000	0	9	3000	1	0	4	3000	5	0	1	9	0	0	12807	9206	6896	3089	7	41	20653	3134	3820	14	38	44	28337	16268	13767	15598	3000	29261	29201	29411	29341	29442

Count: 8

Code:

  ld1 { v0.8h, v1.8h, v2.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80703	600	1	1	1	1	0	65	1	2	80050	2	0	18	14	25	240100	100	240000	100	240000	500	3500450	1	80023	80065	80048	49988	3	50023	240100	200	240000	200	240000	80048	80048	1	1	80201	100	99	100	100	80000	80000	1	100	240019	20	42	240057	1	0	1	66	240039	5	1	58	42	19	1	5110	4	16	1	3	80062	9	9	2	240000	100	80066	80074	80070	80070	80066
240204	80065	600	1	0	0	0	0	74	0	2	80055	2	18	0	17	25	240100	100	240000	100	240000	500	3531263	0	80050	80368	80076	50206	3	50026	240462	200	240383	200	240000	80380	80065	1	1	80201	100	99	100	100	80000	80000	1	100	240020	21	42	240059	1	0	0	63	240039	6	1	58	42	19	1	5110	3	16	4	2	80044	9	9	2	240000	100	80066	80070	80070	80066	80049
240204	80069	600	1	1	1	0	0	33	0	3	80050	2	18	18	17	25	240100	100	240000	100	240000	500	3520953	0	80044	80069	80070	49992	3	50027	240100	200	240000	200	240000	80069	80069	1	1	80201	100	99	100	100	80000	80000	0	100	240020	19	42	240056	1	1	0	60	240039	0	0	58	42	19	0	5165	2	16	4	4	80062	9	9	2	240000	100	80066	80048	80066	80049	80066
240204	80065	600	1	0	1	0	0	68	1	2	80050	3	18	18	0	25	240100	100	240000	100	240000	500	3531065	0	80040	80048	80209	49997	3	50023	240100	200	240000	200	240000	80066	80065	1	1	80201	100	99	100	100	80000	80000	0	100	240020	19	0	240019	1	0	1	21	240039	6	0	58	42	19	2	5110	3	16	3	1	80064	9	9	2	240000	100	80049	80066	80066	80066	80066
240204	80048	599	1	1	1	0	0	21	1	3	80033	2	18	18	0	25	240100	100	240000	100	240000	500	3523674	0	80040	80047	80065	49988	3	50023	240100	200	240000	200	240000	80048	80065	1	1	80201	100	99	100	100	80000	80000	0	100	240019	20	42	240058	1	0	0	60	240038	5	1	59	42	19	2	5110	1	16	3	3	80062	9	9	2	240000	100	80067	80069	80066	80067	80048
240204	80048	599	1	1	1	0	0	65	1	3	80060	2	18	0	49	25	240100	100	240000	100	240000	500	3500271	0	80040	80065	80065	49988	3	50023	240100	200	240000	200	240000	80065	80047	1	1	80201	100	99	100	100	80000	80000	0	100	240021	20	42	240057	1	0	2	60	240039	0	1	58	42	19	1	5110	3	16	1	3	80062	9	9	2	240000	100	80066	80066	80068	80066	80049
240204	80065	599	1	1	0	0	0	65	1	3	80050	2	18	18	16	25	240100	100	240000	100	240000	500	3523674	0	80040	80068	80066	49988	3	50023	240100	200	240000	200	240000	80065	80065	1	1	80201	100	99	100	100	80000	80000	0	100	240020	20	42	240059	1	0	1	60	240039	5	1	58	42	19	0	5110	2	16	2	4	80062	9	0	2	240000	100	80066	80049	80066	80066	80066
240204	80065	600	1	1	1	0	0	21	0	3	80050	2	0	18	16	25	240100	100	240000	100	240000	500	3472516	0	80040	80065	80065	49988	3	50006	240100	200	240000	200	240000	80065	80065	1	1	80201	100	99	100	100	80000	80000	0	100	240020	19	0	240058	1	1	1	66	240040	5	0	19	42	19	0	5110	1	16	3	5	80063	9	0	2	240000	100	80049	80066	80050	80049	80066
240204	80068	599	1	0	1	0	0	65	0	3	80050	1	18	18	16	25	240100	100	240000	100	240000	500	3501095	0	80040	80065	80065	49988	3	50023	240100	200	240000	200	240000	80065	80065	1	1	80201	100	99	100	100	80000	80000	1	100	240019	20	42	240058	1	1	0	58	240039	5	0	58	0	19	1	5110	2	16	1	3	80062	9	9	2	240000	100	80066	80048	80049	80066	80066
240204	80065	599	1	1	1	0	0	65	0	3	80053	2	18	0	17	25	240100	100	240000	100	240000	500	3513588	0	80040	80065	80065	49989	3	50023	240100	200	240000	200	240000	80065	80065	1	1	80201	100	99	100	100	80000	80000	0	100	240021	21	41	240059	1	0	2	60	240038	5	1	19	42	19	2	5110	3	16	3	2	80062	9	9	2	240000	100	80066	80049	80049	80066	80066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80072	599	0	0	0	720	0	1	0	1	80046	2	12	12	16	25	240010	10	240000	10	240000	50	3521982	1	80036	0	80061	80061	50006	3	50041	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240040	0	39	240040	5	1	40	44	0	5020	8	16	7	5	80058	0	10	0	0	240000	10	80068	80062	80061	80062	80062
240024	80061	599	0	0	0	45	0	1	0	1	80046	2	12	12	16	25	240010	10	240000	10	240000	50	3517947	1	80040	0	80041	80041	50006	3	50021	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240040	0	40	240040	5	1	41	0	0	5020	5	16	6	6	80038	0	10	10	4	240000	10	80062	80061	80062	80042	80062
240024	80060	600	1	0	0	45	0	1	0	0	80046	2	12	0	16	25	240010	10	240000	10	240000	50	3521982	1	80036	0	80061	80061	50006	3	50021	240010	20	240000	20	240000	80061	80066	1	1	80021	10	9	10	10	80000	80000	1	10	240000	0	43	0	240040	0	0	240040	0	1	40	0	0	5020	5	16	7	5	80058	0	10	10	4	240000	10	80062	80065	80042	80062	80062
240024	80061	599	0	0	0	45	0	1	0	1	80046	2	12	12	16	25	240010	10	240000	10	240000	50	3537918	1	80036	0	80061	80061	50006	3	50041	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	0	0	240040	0	40	240040	5	1	40	43	0	5020	7	16	6	4	80058	0	10	10	4	240000	10	80062	80062	80042	80062	80062
240024	80061	599	0	0	0	46	0	0	0	1	80133	2	12	12	16	25	240010	10	240000	10	240000	50	3522236	1	80036	0	80113	80061	50006	3	50041	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240000	0	39	240040	5	1	40	43	0	5020	7	16	6	4	80058	0	10	10	4	240000	10	80061	80062	80062	80062	80249
240024	80041	599	0	0	0	45	0	1	0	1	80046	0	12	12	16	25	240010	10	240000	10	240000	50	3522236	1	80036	0	80061	80061	50006	3	50021	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240040	0	40	240040	6	0	40	43	0	5020	7	16	7	5	80057	0	10	10	0	240000	10	80042	80062	80062	80062	80062
240024	80041	600	0	0	0	46	0	0	0	1	80045	2	12	12	0	25	240010	10	240000	10	240000	50	3522236	1	80035	0	80061	80061	50006	3	50021	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240040	0	40	240040	5	0	40	43	0	5020	4	16	6	4	80058	0	10	10	4	240000	10	80062	80064	80065	80061	80061
240024	80061	600	0	0	0	45	0	1	0	1	80046	2	12	12	16	25	240010	10	240000	10	240000	50	3522236	1	80016	0	80061	80061	50006	3	50041	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240039	0	41	240039	0	0	40	43	0	5020	7	17	5	7	80061	0	10	10	4	240000	10	80061	80062	80062	80062	80062
240024	80061	600	0	0	0	45	0	1	0	1	80049	2	12	0	93	25	240140	10	240520	10	240000	60	3537918	1	80035	0	80061	80194	50106	3	50160	240010	20	240381	20	240000	80041	80061	2	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240041	0	40	240040	5	1	40	43	0	5020	8	16	4	6	80057	0	10	0	4	240000	10	80042	80062	80062	80062	80062
240024	80041	599	0	0	0	0	0	1	0	1	80026	2	12	12	2	25	240010	10	240000	10	240000	50	3517947	0	80036	0	80061	80061	50006	3	50041	240010	20	240000	20	240000	80061	80061	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240000	0	0	240040	5	1	40	43	0	5035	7	16	7	5	80061	0	10	10	0	240000	10	82459	83372	83386	83060	83383

LD1 (multiple, 3 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations