Firestorm: LD1 (multiple, 4 regs, 16B) measurements

Code:

  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
64005	29462	220	14	1	1	0	0	0	0	12	0	0	4552	29115	0	0	0	23378	4000	4000	4000	20705	6	16957	28760	29312	3	10	4000	4000	4000	29142	29324	1	1	61001	1000	1000	0	4000	0	12	4007	0	0	8	4000	5	1	8	12	0	0	12655	9017	6841	3155	5	84	20289	3092	3813	20	63	59	28477	16584	13436	15263	4000	29355	29415	29493	29388	29437
64004	29433	220	4	0	0	1	0	0	0	0	0	0	4575	29133	2	4	0	23346	4000	4000	4000	20708	8	16917	28763	29506	3	10	4000	4000	4000	29161	29262	1	1	61001	1000	1000	0	4000	0	0	4007	0	0	10	4000	0	1	8	0	0	0	12838	9011	6814	3126	2	63	20423	3031	3810	15	60	58	28410	16348	13430	15344	4000	29414	29381	29346	29426	29394
64004	29356	219	4	0	0	1	0	0	0	13	1	0	4603	29137	0	0	0	23384	4000	4000	4000	20713	6	16957	28708	29390	3	10	4000	4000	4000	29129	29221	1	1	61001	1000	1000	0	4000	0	12	4006	0	2	2	4006	6	1	6	12	0	0	12809	8934	6846	3120	3	62	20449	3118	3812	17	60	59	28417	16563	13374	15217	4000	29307	29383	29393	29425	29356
64004	29403	220	6	0	0	0	0	0	0	0	1	0	4470	29315	0	0	1	23380	4000	4000	4000	20719	8	16940	28676	29381	12	48	4000	4000	4000	29252	29228	1	1	61001	1000	1000	0	4000	0	12	4007	0	0	8	4007	6	1	7	8	4	0	12974	9108	6861	3103	2	68	20395	3148	3812	10	60	66	28409	16315	13380	14873	4000	29412	29383	29402	29417	29417
64004	29276	220	6	0	0	1	0	0	0	14	0	0	4562	29489	0	1	0	23415	4000	4000	4000	20714	7	16936	28714	29401	3	10	4000	4000	4000	29313	29206	2	1	61001	1000	1000	1	4004	4	12	4007	0	2	473	4000	5	1	7	0	9	0	12764	9080	6834	3099	3	70	20446	3078	3813	17	65	59	28482	16363	13597	15046	4000	29464	29541	29445	29368	29482
64004	29502	220	7	0	0	1	0	0	0	12	0	0	4539	29126	0	0	0	23389	4000	4000	4000	20859	6	16938	28705	29447	3	10	4000	4004	4000	29334	29346	3	1	61001	1000	1000	0	4000	0	12	4002	0	0	0	4008	0	1	8	12	0	0	12746	9173	6843	3110	1	64	20470	3071	3807	13	66	61	28434	16516	13405	15027	4000	29405	29355	29318	29379	29396
64004	29421	232	4	1	1	0	0	1	0	0	0	0	4668	29372	0	0	1	23602	4000	4000	4000	20703	3	16934	28884	29517	3	10	4000	4000	4000	29202	29188	1	1	61001	1000	1000	0	4000	0	12	4008	1	0	9	4007	6	0	7	12	0	0	12733	9044	6880	3076	6	63	20222	3071	3815	15	59	59	28460	15852	13315	15215	4000	29337	29338	29380	29337	29383
64004	29441	221	4	0	0	0	0	0	0	19	0	0	4586	29129	2	0	0	23363	4000	4000	4000	20718	3	16933	28759	29449	3	10	4000	4000	4000	29233	29149	1	1	61001	1000	1000	0	4000	0	12	4007	0	0	7	4002	6	1	3	12	0	0	12778	9059	6828	3067	1	69	20380	3088	3808	18	62	64	28469	16555	13312	15277	4000	29442	29373	29436	29450	29316
64004	29360	220	5	0	0	0	0	0	0	0	0	0	4486	29107	0	4	0	23377	4000	4000	4000	20709	5	16916	28652	29341	3	10	4000	4000	4000	29207	29202	1	1	61001	1000	1000	0	4000	0	12	4006	0	0	6	4006	6	1	0	8	0	0	12872	9117	6847	3033	3	72	20347	3073	3810	14	60	60	28364	16342	13459	15142	4000	29439	29410	29464	29482	29349
64004	29380	220	3	1	0	0	0	0	0	0	0	0	4518	29106	0	3	0	23418	4000	4000	4000	20710	3	16946	28715	29320	3	10	4000	4000	4000	29198	29253	1	1	61001	1000	1000	0	4000	0	12	4007	0	0	7	4006	6	0	0	12	0	0	12802	9184	6880	3037	3	64	20399	3061	3814	13	64	61	28724	16537	13448	15192	4000	29465	29460	29348	29260	29511

Count: 8

Code:

  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	106731	800	0	1	0	0	0	0	0	0	0	1	0	0	1	106719	2	12	12	16	25	320100	100	320000	100	320017	500	4673844	0	106682	0	106727	106707	26677	6	26700	320117	200	320024	200	320024	106727	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	39	320039	6	0	39	0	0	0	0	0	5109	0	1	17	1	1	106724	0	10	10	4	320000	100	106728	106728	106728	106728	106938
320204	106727	799	0	0	0	1	0	0	0	55	0	0	0	0	1	106712	2	12	0	0	25	320100	100	320000	100	320000	500	4709628	0	106702	0	106727	106727	26675	3	26709	320100	200	320000	200	320768	106745	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	39	320039	6	1	39	43	0	0	0	0	5109	0	1	17	1	1	106724	0	10	0	4	320000	100	106708	106728	106728	106708	106708
320204	106727	799	0	0	0	0	0	0	0	45	0	0	0	0	1	106712	2	12	0	16	25	320100	100	320000	100	320000	500	4728183	0	106702	0	106727	106727	26675	3	26712	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	42	320039	0	1	39	43	0	0	0	0	5109	0	1	17	1	1	106724	0	10	10	0	320000	100	106728	106728	106708	106728	106728
320204	106727	800	0	0	0	0	0	0	0	54	0	1	0	0	1	106712	2	0	12	0	25	320100	100	320000	100	320000	500	4709628	0	106704	0	106727	106727	26675	3	26709	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	0	320039	6	1	40	43	0	0	0	0	5109	0	2	17	1	1	106724	0	10	10	4	320000	100	106728	106708	106708	106728	106728
320204	106707	799	0	0	0	0	0	0	0	45	0	1	0	0	1	106712	2	12	12	16	25	320100	100	320000	100	320000	500	4709628	0	106702	0	106707	106727	26675	3	26689	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	0	320039	1	0	40	320039	6	1	39	43	0	0	0	0	5109	0	1	17	1	1	106728	0	0	10	4	320000	100	106731	106728	106728	106728	106728
320204	106727	800	0	0	0	0	0	0	0	45	0	0	0	0	0	106712	2	12	0	16	25	320100	100	320000	100	320000	500	4709628	0	106702	0	106727	106727	26675	3	26709	320100	200	320000	200	320000	106729	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320000	0	0	39	320000	6	0	39	43	0	0	0	0	5109	0	1	17	1	1	106704	0	10	10	4	320000	100	106728	106728	106728	106708	106728
320204	106707	799	0	0	0	0	0	0	0	45	0	1	0	0	1	106692	2	12	12	0	25	320100	100	320000	100	320000	500	4728183	0	106702	0	106727	106727	26675	3	26711	320100	200	320000	200	320768	106804	106742	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	39	320039	0	1	39	43	0	0	0	0	5109	0	1	17	1	1	106704	0	10	10	4	320000	100	106728	106728	106728	106728	106728
320204	106707	799	0	0	0	0	0	0	0	45	0	0	0	0	1	106712	0	12	12	16	25	320100	100	320000	100	320000	500	4698880	1	106702	0	106727	106727	26655	3	26689	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	1	100	320000	0	43	0	320039	0	0	39	320000	6	1	39	43	0	0	0	0	5110	0	1	17	1	1	106724	0	10	10	0	320000	100	106728	106728	106728	106728	106728
320204	106727	800	0	0	0	0	0	0	0	45	0	1	0	0	1	106712	2	12	12	16	25	320100	100	320000	100	320000	500	4709628	1	106685	0	106730	106710	26655	3	26709	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	0	320000	6	1	39	0	0	0	0	0	5109	0	1	17	1	1	106724	0	10	10	0	320000	100	106728	106728	106728	106728	106708
320204	106727	799	0	0	0	1	1	0	0	45	0	1	0	0	1	106712	2	12	12	16	25	320100	100	320000	100	320000	500	4673754	1	106702	0	106707	106727	26675	3	26709	320100	200	320000	200	320000	106707	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	39	320000	0	1	39	0	0	0	1	0	5110	0	1	17	1	1	106724	0	10	10	4	320000	100	106708	106728	106708	106731	106728

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	106723	830	0	0	0	0	41	1	1	106692	2	0	18	12	25	320010	10	320000	10	320000	50	4685107	1	106903	106722	106722	26670	3	26689	320010	20	320000	20	320000	106727	106707	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	320035	0	0	0	35	320039	6	1	35	39	0	0	0	5020	14	17	0	12	14	106719	6	0	2	320000	10	106727	106728	106734	106723	106725
320024	106707	799	0	0	0	0	41	0	1	106692	3	18	18	12	25	320010	10	320000	10	320000	50	4685107	1	106697	106722	106722	26670	3	26704	320010	20	320000	20	320000	106722	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320035	0	0	0	35	320035	6	1	0	39	0	0	0	5020	12	17	0	14	15	106704	6	6	2	320000	10	106723	106723	106723	106726	106708
320024	106722	799	0	0	0	0	41	1	1	106707	2	18	18	12	25	320010	10	320000	10	320000	50	4683360	1	106682	106803	106741	26670	3	26704	320010	20	320000	20	320000	106707	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320035	0	0	0	92	320035	6	1	35	39	0	0	0	5019	9	17	0	10	14	106719	6	6	2	320000	10	106725	106723	106716	106728	106762
320024	106725	799	0	0	0	0	41	0	0	106707	0	18	18	12	25	320010	10	320000	10	320000	50	4698880	1	106697	106722	106722	26670	3	26704	320010	20	320000	20	320000	106722	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320035	0	0	0	35	320035	6	1	35	39	0	0	0	5020	14	17	0	14	14	106719	6	6	2	320000	10	106723	106723	106708	106723	106723
320024	106722	800	0	0	0	0	41	1	1	106692	2	18	18	12	25	320010	10	320000	10	320000	50	4705837	1	106697	106722	106722	26670	3	26704	320010	20	320000	20	320000	106722	106730	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320035	0	0	0	38	320036	6	1	0	39	0	0	0	5019	16	17	0	16	13	106704	0	6	2	320000	10	106723	106723	106811	106708	106708
320024	106707	799	0	0	0	0	41	1	1	106692	2	18	18	12	25	320010	10	320000	10	320000	50	4685107	1	106697	106722	106707	26670	3	26689	320010	20	320000	20	320000	106722	106711	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320035	0	0	0	0	320036	6	1	35	39	0	0	0	5020	14	17	0	14	15	106856	6	6	2	320000	10	106723	106708	106723	106723	106708
320024	106722	799	0	0	0	0	0	1	0	106710	2	0	18	12	25	320010	10	320000	10	320000	50	4705837	1	106820	106722	106722	26670	3	26689	320010	20	320000	20	320000	106722	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320000	0	0	0	0	320035	6	1	0	39	0	0	0	5020	12	17	0	13	13	106719	6	6	2	320000	10	106723	106723	106723	106727	106723
320024	106726	800	0	0	0	0	12	1	1	106707	2	18	18	5	48	320140	10	320130	10	320890	50	4668429	1	106697	106749	106726	26674	3	26708	320010	20	320000	20	320000	106722	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320036	0	1	0	41	320035	6	1	35	39	0	0	0	5020	12	17	0	15	12	106719	6	6	2	320000	10	106723	106723	106727	106727	106708
320024	106726	799	0	0	0	0	41	1	1	106707	2	18	18	14	25	320010	10	320000	10	320000	50	4722913	1	107011	106707	106722	26670	3	26704	320010	20	320000	20	320000	106722	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320035	0	0	0	35	320000	6	1	35	0	0	0	0	5020	14	17	0	12	12	106719	6	6	2	320000	10	106723	106708	106723	106723	106708
320024	106722	799	0	0	0	0	41	1	1	106707	2	18	18	11	25	320010	10	320000	10	320000	50	4702992	1	106697	106722	106707	26670	3	26689	320010	20	320000	20	320000	106707	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	39	320000	0	0	0	35	320000	6	1	35	0	0	0	1	5020	12	17	0	15	11	106719	6	0	2	320000	10	106723	106723	106708	106740	106723

LD1 (multiple, 4 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations