Firestorm: LD1 (multiple, 4 regs, 1D) measurements

Code:

  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	29268	219	0	25	0	0	17	0	0	0	17	0	1	0	0	4544	28875	0	1	2	24154	2000	2000	2000	10000	6	0	16251	28594	29306	3	10	2000	4000	2000	29096	29046	1	1	61001	1000	1000	0	2000	0	6	2002	0	0	0	0	2000	4	0	4	6	0	0	12952	9299	6848	3051	8	49	20289	3267	3815	12	51	47	28346	16460	13590	15538	2000	2000	29293	29223	29325	29289	29275
64004	29246	219	0	17	0	0	14	0	0	0	7	0	1	0	0	4657	28812	2	2	2	24096	2000	2000	2000	10000	5	0	16255	28843	29304	3	10	2000	4000	2000	29119	29178	1	1	61001	1000	1000	0	2000	0	6	2000	0	0	0	4	2000	4	0	0	6	0	0	13829	9387	6915	3084	12	41	20286	3082	3818	10	45	44	28333	16386	13590	15467	2000	2000	29346	29243	29299	29281	29306
64004	29278	219	0	25	0	0	23	0	0	0	7	0	0	0	0	4593	28869	0	2	0	24072	2000	2000	2000	10000	5	0	16255	28641	29283	3	10	2000	4000	2000	29141	29160	1	1	61001	1000	1000	0	2000	0	4	2004	0	0	0	0	2002	4	0	0	6	0	0	13045	9246	6960	3107	13	48	20346	3086	3816	17	48	44	28512	16396	13615	15403	2000	2000	29288	29216	29279	29246	29277
64004	29255	219	0	19	0	0	15	0	0	0	7	0	0	0	0	4612	29057	0	2	2	24096	2000	2000	2000	10000	0	0	16230	28556	29260	3	10	2000	4000	2000	29074	29150	1	1	61001	1000	1000	0	2000	0	6	2000	0	1	0	2	2000	4	0	2	4	0	0	12848	9815	6863	3100	14	48	20381	3081	3811	11	47	46	28401	16268	13621	14868	2000	2000	29277	29336	29277	29311	29391
64004	29261	220	0	17	0	0	22	0	0	0	7	0	0	0	0	4638	28937	2	0	0	24113	2000	2000	2000	10000	3	0	16242	28545	29247	3	10	2000	4000	2000	29106	29118	1	1	61001	1000	1000	0	2000	0	4	2004	0	0	0	2	2000	4	0	4	6	0	0	12839	9259	6886	3050	6	40	20284	3053	3817	7	41	48	28337	16182	13549	15419	2000	2000	29322	29287	29302	29322	29331
64004	29515	220	0	23	0	0	22	0	0	0	8	0	1	0	0	4684	28872	0	2	2	24051	2000	2000	2000	10000	5	0	16247	28625	29343	3	10	2000	4000	2000	29112	29107	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	0	0	2000	4	0	2	6	0	0	13042	9215	6925	3108	7	45	20259	3027	3814	8	48	49	28304	16250	13646	15341	2000	2000	29268	29247	29325	29305	29253
64004	29269	218	0	23	0	0	18	0	0	0	32	0	1	0	0	4598	28893	2	0	2	24043	2000	2000	2002	10014	0	0	16251	28540	29180	3	10	2000	4000	2000	29047	29172	1	1	61001	1000	1000	0	2000	0	6	2002	0	0	0	2	2004	4	0	3	6	0	0	13039	9411	6909	3144	10	38	20287	3088	3814	13	48	47	28719	16325	13802	15617	2000	2000	29270	29326	29273	29203	29270
64004	29236	218	0	23	0	0	19	0	0	0	8	0	0	0	0	4623	28812	2	0	2	24080	2000	2000	2000	10000	4	0	16234	28577	29406	3	10	2000	4000	2000	29213	29152	1	1	61001	1000	1000	0	2000	0	4	2004	0	0	0	2	2004	4	0	2	6	0	0	13016	9221	6884	3109	10	38	20242	3072	3810	14	42	48	28416	15395	13638	15532	2000	2000	29222	29335	29367	29387	29280
64004	29213	219	0	20	0	0	17	0	0	0	8	0	0	0	0	4640	28826	2	2	1	24077	2000	2000	2000	10000	5	0	16252	28679	29227	3	10	2000	4000	2000	29168	29043	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	0	0	2002	4	0	4	6	0	0	13095	9297	6873	3118	8	48	20287	3065	3812	16	48	45	28392	16252	13803	15557	2000	2000	29324	29321	29311	29409	29250
64004	29318	219	0	20	0	0	17	0	1	1	8	0	0	0	0	4614	28796	0	2	2	24112	2000	2000	2000	10000	5	0	16238	28581	29437	3	10	2000	4000	2000	29127	28999	5	1	61001	1000	1000	1	2000	0	4	2004	0	0	0	0	2002	4	0	0	4	0	0	13666	9334	6877	3053	7	48	20359	3094	3816	6	49	44	28454	16465	13694	15596	2000	2000	29288	29371	29283	29326	29301

Count: 8

Code:

  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	599	0	0	0	1	1	0	38	0	1	0	0	80026	2	12	12	28	160112	100	160012	100	160312	500	800929	1	80083	80041	80042	0	6	12	160116	200	320032	200	160016	80041	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160004	35	0	160036	0	35	160004	6	1	32	0	1	1	1	5116	0	16	0	0	80039	1	10	0	2	160000	160000	100	80042	80043	80042	80043	80042
320204	80041	600	0	0	0	0	0	0	38	0	0	0	2	80027	2	0	12	28	160112	100	160012	100	160016	500	800929	1	80022	80041	80041	0	6	12	160116	200	320032	200	160016	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160004	35	0	160036	0	36	160036	6	1	0	40	1	1	1	5116	0	16	0	0	80038	0	0	0	2	160000	160000	100	80042	80043	80042	80387	80042
320204	80041	599	0	0	0	0	0	0	0	0	0	0	0	80026	0	12	12	28	160112	100	160012	100	160016	500	800076	1	80022	80041	80041	0	6	12	160116	200	320032	200	160016	80041	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160004	35	0	160004	0	0	160036	6	1	32	42	1	1	1	5116	0	16	0	0	80177	0	14	0	2	160000	160000	100	80042	80043	80042	80386	80042
320204	80041	599	0	0	0	0	1	0	38	0	0	0	2	80026	2	12	12	27	160112	100	160012	100	160016	500	800633	1	80022	80041	80041	0	23	12	160116	200	320032	200	160016	80042	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160004	35	0	160036	5	0	160040	6	0	32	40	1	1	1	5116	0	16	0	0	80038	0	14	14	0	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	600	0	0	0	1	0	0	42	0	1	0	0	80027	2	0	0	27	160112	100	160012	100	160016	500	800929	1	80096	80041	80041	44	6	12	160116	200	320032	200	160016	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160004	35	0	160036	0	32	160004	6	1	36	40	1	1	1	5116	0	16	0	0	80038	0	14	14	2	160000	160000	100	80042	80042	80042	80042	80043
320204	80041	600	1	0	0	1	0	0	42	0	1	0	0	80026	2	12	12	27	160112	100	160012	100	160016	500	800453	0	80022	80041	80041	0	6	12	160116	200	320032	200	160016	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160004	35	0	160036	4	32	160040	6	0	0	0	1	1	1	5116	0	16	0	0	80038	1	10	10	0	160000	160000	100	80042	80043	80042	80042	80042
320204	80041	600	0	0	0	0	1	0	42	0	0	0	2	80025	0	12	12	25	160100	100	160000	100	160000	500	800377	1	80015	80040	80040	0	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160000	0	32	160032	6	1	0	0	0	0	0	5109	1	17	1	1	80037	1	0	10	0	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	0	0	0	0	0	0	38	0	0	0	2	80025	2	12	0	25	160100	100	160000	100	160000	500	800000	0	80015	80040	80040	0	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160000	0	3	160032	6	0	36	40	0	0	0	5109	1	17	1	1	80122	0	14	0	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	0	0	0	42	0	0	0	2	80025	0	12	15	25	160100	100	160000	100	160000	500	800000	0	80015	80040	80040	0	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	39	160036	6	1	32	40	0	0	0	5109	1	17	1	1	80037	1	14	14	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	0	0	0	38	0	1	0	2	80025	2	0	12	25	160100	100	160000	100	160000	500	800000	1	80015	80040	80040	0	3	180	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	0	160032	0	0	160000	6	1	36	40	0	0	0	5109	1	17	1	1	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80127	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80042	599	0	0	0	1	1	0	1	0	0	80025	2	5	5	3	25	160010	10	160000	10	160000	50	801383	0	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	1	10	160013	14	0	160013	0	0	1	51	160000	6	1	51	43	13	0	0	5019	9	17	0	7	5	80037	13	13	5	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	1	1	1	0	0	58	0	0	0	80025	2	5	5	3	25	160010	10	160000	10	160000	50	801383	0	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160013	14	43	160012	0	0	1	51	160000	0	1	50	0	13	1	0	5019	5	17	0	7	5	80037	0	0	5	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	1	1	0	1	0	58	1	0	2	80025	2	5	0	3	25	160010	10	160000	10	160000	50	800048	1	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160014	14	0	160051	0	0	0	12	160039	0	1	13	43	13	0	0	5019	5	17	0	7	5	80100	0	0	5	160000	160000	10	80041	80103	80041	80041	80041
320024	80040	600	1	1	1	0	0	57	1	0	2	80025	2	5	5	3	25	160010	10	160000	10	160000	50	801383	1	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	1	10	160014	12	43	160053	0	0	1	12	160039	6	1	51	0	13	0	0	5019	5	17	0	5	7	80037	0	13	5	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	1	0	1	0	0	13	0	0	2	80025	2	5	5	3	25	160010	10	160000	10	160000	50	801383	1	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160014	14	0	160054	0	0	0	52	160000	6	0	52	43	13	0	0	5019	8	17	0	5	7	80037	13	13	5	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	1	1	0	0	0	59	0	0	0	80025	0	5	5	3	25	160010	10	160000	10	160000	50	801386	0	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	1	10	160015	15	0	160052	0	0	1	13	160039	0	1	12	43	13	0	0	5019	6	17	0	7	5	80037	13	13	5	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	1	1	1	0	0	59	0	0	0	80025	0	5	0	0	25	160010	10	160000	10	160000	50	801380	0	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160015	14	43	160013	0	0	0	13	160040	6	1	52	43	12	2	0	5019	5	17	0	5	7	80037	0	13	0	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	1	1	1	0	0	57	0	0	0	80025	0	5	5	3	25	160010	10	160000	10	160000	50	800042	0	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160014	12	43	160052	0	0	0	19	160040	6	0	13	43	12	0	0	5019	5	17	0	7	5	80037	0	0	5	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	1	1	1	1	0	66	0	0	2	80025	2	0	5	3	25	160010	10	160000	10	160000	50	801383	0	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160012	13	43	160051	0	0	1	13	160039	6	0	13	43	12	1	0	5019	5	17	0	5	7	80037	13	13	0	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	1	1	0	1	1	57	0	0	0	80025	2	5	0	3	25	160010	10	160000	10	160000	50	801377	0	80015	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160014	12	43	160053	0	0	1	13	160039	0	0	52	43	12	0	0	5019	7	17	0	5	7	80037	13	13	5	160000	160000	10	80041	80041	80041	80041	80041

LD1 (multiple, 4 regs, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations