Firestorm: LD1 (multiple, 4 regs, 2D) measurements

Code:

  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
64005	28629	214	3	0	0	1	1	0	0	0	17	0	0	0	0	5264	27983	0	4	4	22121	4000	4000	4000	20706	3	1	0	16977	28051	28260	3	10	4000	4000	4000	28165	28105	1	1	61001	1000	1000	1	4006	6	8	4007	0	0	2	14	4010	6	0	4	11	0	0	14025	10398	7158	3592	2	63	19170	3501	3823	14	40	37	27780	14793	11663	12516	4000	28099	28327	28115	28150	28075
64004	28134	211	1	0	0	0	0	0	1	1	40	0	1	0	0	5251	28008	0	0	0	22015	4000	4000	4000	20708	4	1	0	16979	28088	28342	3	10	4000	4000	4000	28189	28111	1	1	61001	1000	1000	0	4000	0	8	4000	0	0	0	6	4006	5	1	3	11	0	0	13937	10471	7142	3361	1	37	19092	3475	3818	15	38	38	27742	13903	11777	13010	4000	28141	27991	28186	28165	28382
64004	28145	211	1	0	0	0	0	0	0	0	27	0	1	0	0	5187	28166	0	0	0	22051	4000	4000	4000	20737	2	0	0	16976	27957	28122	3	10	4000	4000	4000	27992	28267	1	1	61001	1000	1000	0	4000	0	0	4003	0	0	0	6	4000	4	0	6	8	0	0	13710	10408	7367	3527	0	46	19181	3416	3815	17	42	41	27821	14301	11713	12700	4000	28083	28193	28219	28273	28243
64004	28092	211	1	0	0	0	0	0	0	0	9	0	0	0	0	5204	28383	2	4	0	22171	4000	4000	4000	20709	0	0	0	16967	27886	28125	3	10	4000	4000	4000	28051	28490	1	1	61001	1000	1000	0	4000	0	0	4006	0	0	0	0	4004	0	1	4	8	0	0	14137	10188	7218	3553	0	43	19124	3519	3821	13	39	36	27873	15005	11857	12592	4000	28107	28258	28174	28290	28129
64004	28119	210	0	0	0	0	0	0	0	0	0	0	1	0	0	5260	28178	0	0	4	22224	4000	4000	4000	20711	6	0	8	16962	27971	28366	3	10	4000	4000	4000	28070	27994	1	1	61001	1000	1000	1	4000	0	0	4002	0	1	0	7	4006	6	0	6	11	0	0	13812	10453	7312	3540	0	43	19359	3405	3816	16	45	40	28076	13989	11719	12485	4000	28344	28119	28370	28203	28145
64004	28334	211	2	0	0	0	0	0	0	0	8	0	0	0	0	5160	28184	2	4	4	22123	4000	4000	4000	20702	5	0	8	16954	27933	28357	3	10	4000	4000	4000	28199	28093	1	1	61001	1000	1000	0	4000	0	8	4006	0	0	0	3	4004	5	1	9	0	0	0	13945	10382	7335	3522	0	37	19270	3488	3817	20	41	43	27866	14116	11773	12749	4000	28291	28132	28259	28247	28002
64004	28180	211	0	0	0	0	0	0	0	0	12	0	0	0	0	5297	28273	0	0	0	22138	4000	4000	4000	20730	4	0	0	16959	27932	28109	3	10	4000	4000	4000	28029	28034	1	1	61001	1000	1000	0	4000	0	8	4003	0	0	0	3	4000	6	1	4	0	0	0	14172	10337	7344	3507	0	38	19261	3438	3814	18	39	42	27755	13895	11669	12616	4000	28102	28156	28094	28100	28081
64004	28311	212	1	0	0	0	0	0	1	1	13	0	1	0	0	5316	28213	2	0	0	22092	4000	4000	4000	20741	4	0	0	16973	27912	28088	3	10	4000	4000	4000	28011	28061	1	1	61001	1000	1000	0	4000	0	8	4009	0	12	0	13	4000	0	0	0	0	0	0	13962	10160	7324	3418	0	45	19286	3402	3817	18	40	41	27843	14803	12037	12731	4000	28170	27990	28077	28015	28252
64004	27991	210	0	0	0	0	0	0	0	0	10	0	1	0	0	5298	28032	0	0	0	22224	4000	4000	4000	20705	1	1	0	16979	27915	28250	3	10	4000	4000	4000	28043	27983	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	6	4002	0	1	4	0	0	0	14128	10059	7302	3424	0	38	19032	3491	3818	17	32	36	27808	14591	11622	12647	4000	28083	28412	28261	28094	28138
64004	28191	210	1	0	0	0	0	0	0	0	10	0	0	0	0	5125	27995	0	4	4	22192	4000	4000	4000	20707	3	1	8	16965	28038	28148	3	10	4000	4000	4000	28046	28085	1	1	61001	1000	1000	0	4000	0	8	4000	0	1	0	174	4002	0	0	0	11	0	0	14236	10436	7211	3573	2	41	19115	3446	3826	15	37	38	27820	13770	11473	13355	4000	28012	28111	28224	28174	28124

Count: 8

Code:

  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.3354

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	106730	799	0	0	0	1	1	0	0	44	0	0	0	2	106699	0	7	7	0	25	320100	100	320000	100	320000	500	4674234	0	106977	0	106727	106732	26655	3	26689	320100	200	320000	200	320000	106727	106707	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	43	0	320038	0	0	0	858	320040	6	1	19	43	19	2	0	5109	2	17	1	1	106733	0	13	5	320000	100	106737	106737	106737	106737	106737
320204	106822	799	0	0	0	0	0	0	0	44	0	0	0	1	106721	0	0	0	0	25	320100	100	320000	100	320000	500	4699887	1	106706	0	106731	106731	26655	3	26689	320100	200	320000	200	320000	106731	106727	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	0	0	320038	0	0	0	42	320039	0	0	0	0	0	0	0	5109	1	17	1	1	106728	14	10	0	320000	100	106732	106708	106708	106708	106732
320204	106879	799	0	0	0	0	0	0	0	53	0	1	0	1	106716	2	0	1	19	25	320100	100	320000	100	320000	500	4699887	0	106682	0	106731	106731	26675	3	26713	320100	200	320000	200	320000	106731	106727	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	44	0	320039	0	0	0	47	320000	6	1	39	44	0	0	0	5109	1	17	1	1	106728	14	14	0	320000	100	106732	106708	106732	106708	106708
320204	106747	799	0	0	0	0	0	0	0	45	0	1	0	1	106692	2	1	1	19	25	320100	100	320000	100	320000	500	4699887	1	106682	0	106731	106731	26679	3	26713	320100	200	320000	200	320000	106731	106727	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	43	0	320038	0	0	0	116	320000	6	1	0	44	0	0	0	5109	1	17	1	1	106704	14	0	0	320000	100	106732	106728	106732	106708	106728
320204	106837	799	0	0	0	0	0	0	0	44	0	1	0	0	106716	2	0	1	19	25	320100	100	320000	100	320000	500	4705621	1	106682	0	106731	106732	26676	3	26689	320100	200	320000	200	320000	106731	106727	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	43	0	320038	0	1	0	215	320039	0	1	0	44	0	0	0	5109	1	17	1	1	106724	14	14	0	320000	100	106728	106728	106732	106732	106708
320204	106873	800	0	0	0	1	1	0	0	44	0	1	0	1	106716	2	12	0	0	25	320100	100	320000	100	320000	500	4700708	1	106683	0	106707	106707	26679	3	26713	320100	200	320000	200	320000	106707	106731	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	43	0	320038	0	0	0	161	320038	0	0	39	44	0	0	0	5109	1	17	1	1	106730	0	14	0	320000	100	106732	106732	106708	106732	106732
320204	106843	799	0	0	0	0	0	0	0	44	0	0	0	1	106692	2	0	0	19	25	320100	100	320000	100	320000	500	4699887	0	106706	0	106707	106731	26655	3	26713	320100	200	320000	200	320000	106707	106727	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	44	0	320000	0	0	0	161	320038	0	0	39	44	0	0	0	5109	1	17	1	1	106728	14	0	7	320000	100	106708	106708	106708	106728	106728
320204	106759	800	0	0	0	0	0	0	0	0	0	1	0	0	106716	2	1	1	0	25	320100	100	320000	100	320000	500	4674085	0	106706	0	106819	106707	26679	3	26689	320100	200	320000	200	320000	106707	106727	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	43	0	320038	0	60	0	51	320038	6	0	0	44	0	0	0	5109	1	17	1	1	106728	14	0	7	320000	100	106732	106732	106708	106708	106732
320204	106861	800	0	0	0	0	0	0	0	0	0	1	0	0	106712	2	0	0	0	25	320100	100	320000	100	320000	500	4705621	0	106706	0	106734	106707	26679	3	26714	320100	200	320000	200	320000	106731	106707	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	0	200	320038	0	1	40	44	0	0	0	5110	1	17	1	1	106704	14	14	4	320000	100	106735	106728	106732	106708	106712
320204	106731	799	0	0	0	1	1	0	0	44	0	0	0	0	106716	2	1	1	19	25	320100	100	320000	100	320000	500	4709628	1	106706	0	106727	106731	26679	3	26713	320100	200	320000	200	320000	106727	106707	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	43	0	320038	0	0	0	159	320000	6	0	38	44	0	0	0	5109	1	17	1	1	106728	14	7	7	320000	100	106732	106708	106740	106732	106732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	106737	799	0	0	0	1	0	25	1	0	1	106701	17	0	0	3	25	320010	10	320000	10	320000	50	4646912	0	0	0	106706	106731	106731	26663	3	26713	320010	20	320000	20	320000	106731	106716	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	58	320072	1	5	0	25	320055	6	1	25	43	0	5019	1	17	0	1	1	106728	6	6	3	320000	10	106717	106732	106717	106732	106789
320024	106731	800	0	0	0	0	0	25	1	0	1	106716	17	0	0	17	25	320010	10	320000	10	320000	50	4733691	0	1	0	106690	106716	106715	26664	3	26713	320010	20	320000	20	320000	106715	106731	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	58	320072	2	4	2	69	320054	6	1	54	0	0	5019	1	17	0	1	1	106713	0	6	0	320000	10	106716	106732	106732	106717	106732
320024	106715	799	0	0	1	0	0	60	1	0	0	106716	25	15	30	17	25	320010	10	320000	10	320000	50	4665335	0	0	0	106706	106715	106731	26680	3	26713	320010	20	320000	20	320000	106731	106731	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	58	320072	2	2	0	56	320054	0	0	54	43	0	5019	1	17	0	1	1	106713	6	0	0	320000	10	106717	106732	106732	106732	106758
320024	106722	799	1	1	1	0	0	60	0	0	0	106716	25	15	0	3	25	320010	10	320000	10	320000	50	4680202	0	0	0	106690	106731	106731	26664	3	26697	320010	20	320000	20	320000	106731	106715	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	58	320072	3	3	2	25	320025	6	1	54	0	0	5019	1	17	0	1	1	106728	0	6	3	320000	10	106717	106736	106736	106724	107327
320024	106731	799	0	0	0	0	0	60	1	0	1	106716	17	0	0	3	25	320010	10	320000	10	320000	50	4734699	0	0	0	106706	106715	106731	26679	3	26713	320010	20	320000	20	320000	106731	106731	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	58	320041	3	5	0	54	320025	0	1	55	43	0	5019	1	17	0	1	1	106712	6	0	0	320000	10	106717	106716	106732	106732	106834
320024	106731	799	0	0	0	0	0	60	0	0	0	106716	25	0	30	17	25	320010	10	320000	10	320000	50	4719678	0	0	0	106706	106731	106716	26667	3	26697	320010	20	320000	20	320000	106731	106715	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	320070	1	54	0	25	320054	0	1	25	0	0	5019	1	17	0	1	1	106713	6	6	0	320000	10	106716	106716	106716	106732	106897
320024	106723	799	1	0	0	0	0	60	0	0	1	106716	17	15	30	18	25	320010	10	320130	10	320178	50	4719877	0	0	0	106870	106825	106715	26664	3	26732	320010	20	320000	20	320000	106731	106731	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	320072	2	2	0	57	320025	0	1	24	43	0	5019	1	17	0	1	1	106728	6	0	3	320000	10	106736	106732	106717	106720	106883
320024	106722	799	1	0	0	0	0	72	1	0	0	106716	25	15	30	21	25	320010	10	320000	10	320000	50	4729505	0	0	0	106710	106720	106719	26679	3	26717	320010	20	320000	20	320000	106731	106716	1	1	80021	10	9	10	10	80000	80000	0	10	320264	0	58	320072	8	5	0	1650	320184	0	0	25	0	0	5019	1	17	0	1	1	106716	0	0	3	320000	10	106716	106720	106721	106732	106942
320024	106735	800	0	0	0	0	0	72	1	0	1	106720	25	15	30	19	25	320010	10	320000	10	320000	50	4665534	0	0	0	106706	106735	106735	26664	3	26717	320010	20	320000	20	320000	106731	106731	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	58	320057	3	0	2	875	320025	0	1	25	0	1	5019	1	17	0	1	1	106728	6	0	3	320000	10	106716	106716	106732	106716	106757
320024	106731	799	0	0	0	0	0	60	1	0	0	106701	25	15	0	3	25	320010	10	320000	10	320000	50	4733691	0	0	0	106708	106731	106715	26679	3	26713	320010	20	320000	20	320000	106716	106731	1	1	80021	10	9	10	10	80000	80000	1	10	320000	0	0	320041	0	5	1	56	320025	6	1	54	43	0	5019	1	17	0	1	1	106712	6	0	0	320000	10	106716	106732	106717	106732	106757

LD1 (multiple, 4 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations