Firestorm: LD1 (multiple, 4 regs, 2S) measurements

Code:

  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28499	213	5	2	1	0	0	0	8	0	1	0	4922	28251	0	0	0	23192	2000	2000	2000	10000	1	16249	28052	28736	3	10	2000	4000	2000	28348	28647	1	1	61001	1000	1000	1	2000	4	2004	0	2	2000	4	2	4	13165	9572	7173	3345	4	79	19555	3084	3810	17	76	72	28199	15466	12258	14979	2000	2000	28792	28302	28756	28293	28357
64004	28284	216	9	1	1	0	0	0	4	0	1	0	5023	28149	2	0	0	23146	2000	2000	2000	10000	4	16259	27996	28310	3	10	2000	4000	2000	28315	28256	1	1	61001	1000	1000	1	2000	4	2004	0	0	2000	4	0	4	13841	9281	7127	3290	4	71	19359	3083	3816	13	75	60	27952	14538	13011	14589	2000	2000	28423	28306	28691	28228	28757
64004	28321	212	8	0	1	0	0	0	4	0	0	0	5040	28150	0	0	0	23182	2000	2000	2000	10000	4	16281	28580	28419	3	10	2000	4000	2000	28722	28169	1	1	61001	1000	1000	0	2000	4	2000	0	5	2000	0	0	4	13665	10048	7106	3173	1	71	19754	3407	3814	14	73	76	28043	14848	12563	13933	2000	2000	28296	28697	28845	28397	28696
64004	28347	216	8	1	1	0	0	0	4	0	0	0	5049	28107	0	0	0	23184	2000	2000	2000	10000	4	16277	28073	28364	3	10	2000	4000	2000	28323	28315	1	1	61001	1000	1000	0	2000	4	2004	0	0	2000	4	2	4	13868	10098	7197	3360	2	64	19403	3325	3814	18	74	72	27999	14572	12205	14663	2000	2000	28458	28417	28868	28469	28343
64004	28422	216	9	1	1	0	0	0	4	0	1	0	5019	28558	0	0	0	23161	2000	2000	2000	10000	2	16272	28020	28851	3	10	2000	4000	2000	28302	28793	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	0	0	4	13626	10006	7144	3423	5	64	19361	3308	3819	8	79	71	27940	14765	13044	13815	2000	2000	28346	28338	28380	28781	28391
64004	28733	212	8	1	1	0	0	0	6	0	0	0	5117	28090	0	0	0	23269	2000	2000	2000	10000	3	16256	28296	28784	3	10	2000	4000	2000	28227	28247	1	1	61001	1000	1000	0	2000	4	2000	0	2	2004	2	0	4	13938	10094	7165	3369	0	68	19377	3278	3819	8	73	61	27929	14731	12246	13928	2000	2000	28469	28318	28358	28401	28448
64004	28423	212	10	1	1	0	0	0	0	0	0	0	5127	28438	0	2	2	23040	2000	2000	2000	10000	1	16278	27994	28389	3	10	2000	4000	2000	28251	28228	1	1	61001	1000	1000	0	2000	4	2000	0	7	2000	2	2	2	13193	10102	7242	3204	1	67	19258	3293	3814	23	64	74	27982	14553	12463	14733	2000	2000	28355	28313	28423	28371	28326
64004	28374	213	5	1	2	0	0	0	0	0	1	0	5070	28208	0	0	0	23235	2000	2000	2000	10000	1	16250	27990	28752	3	10	2000	4000	2000	28341	28281	1	1	61001	1000	1000	0	2000	4	2000	0	6	2000	4	0	4	13863	10110	7225	3370	4	70	19372	3398	3819	15	78	73	27933	15749	12198	13634	2000	2000	28356	28243	28338	28382	28343
64004	28762	216	11	1	0	0	0	0	6	0	0	0	5117	28242	0	0	0	23070	2000	2000	2000	10000	3	16268	28064	28289	3	10	2000	4000	2000	28250	28333	1	1	61001	1000	1000	1	2000	4	2002	0	4	2000	4	0	0	14064	10126	7187	3470	1	59	19412	3308	3815	15	76	72	28030	14610	12111	14492	2000	2000	28395	28351	28333	28331	28229
64004	28337	212	6	1	0	0	0	0	4	0	0	0	5161	28114	0	0	0	23102	2000	2000	2000	10000	2	16275	27978	28282	3	10	2000	4000	2000	28380	28331	1	1	61001	1000	1000	0	2000	4	2000	0	0	2000	4	0	4	13673	10259	7093	3398	2	69	19377	3177	3815	15	80	65	28158	14735	12475	13905	2000	2000	28334	28345	28819	28682	28759

Count: 8

Code:

  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	600	1	0	0	38	0	0	0	80025	0	12	12	25	160100	100	160000	100	160000	500	800853	0	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	32	160031	6	1	32	40	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80054	80041	80041	80041	80041
320204	80040	600	0	0	0	38	0	0	0	80025	2	12	12	25	160100	100	160000	100	160000	500	800377	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	32	160032	6	1	32	35	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	38	0	0	2	80025	2	12	12	25	160100	100	160000	100	160000	500	800377	0	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	32	160032	6	1	32	35	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	38	1	0	0	80025	2	12	12	25	160100	100	160000	100	160000	500	800377	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	32	160032	6	1	32	35	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	0	1	0	38	0	0	0	80025	2	12	12	25	160100	100	160000	100	160000	500	800377	0	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	32	160032	6	1	32	35	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	0	0	0	38	0	0	0	80025	2	12	12	25	160100	100	160000	100	160000	500	800377	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	32	160032	6	1	32	35	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	38	0	0	0	80025	2	12	12	25	160100	100	160000	100	160000	500	800377	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	32	160032	6	1	32	35	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	38	0	0	0	80025	2	12	12	25	160100	100	160000	100	160000	500	800377	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	32	160032	6	1	32	35	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	38	0	0	0	80025	2	12	12	25	160100	100	160000	100	160000	500	800377	1	80015	3	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	1	0	160036	6	1	32	35	0	0	5109	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	38	0	0	0	80025	2	12	12	25	160100	100	160000	100	160000	500	800374	0	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160090	6	32	160032	6	1	32	35	0	0	5130	3	17	3	3	80037	1	10	10	2	160000	160000	100	80041	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80041	599	0	0	0	0	0	0	30	0	1	0	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800219	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5019	13	17	8	7	80037	1	6	6	2	160000	160000	10	80041	80041	80041	80151	80041
320024	80040	600	0	0	0	0	0	0	30	0	0	0	1	80025	2	12	12	25	160010	10	160000	10	160000	50	800000	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	8	160024	0	0	24	160024	6	1	24	27	0	0	5019	8	17	10	11	80037	1	6	6	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	30	0	0	0	0	80025	0	12	12	25	160010	10	160000	10	160000	50	800221	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160032	6	1	24	27	0	0	5019	9	17	8	12	80037	1	6	6	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	0	0	0	0	0	0	30	0	1	0	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800222	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5019	7	17	9	9	80037	1	6	6	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	30	0	0	0	0	80025	2	0	12	25	160010	10	160000	10	160000	50	800217	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80116	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5048	9	17	10	8	80037	1	6	6	0	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	30	0	0	0	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800222	0	80015	80040	80040	0	3	22	160010	20	320180	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160082	0	0	24	160024	6	1	24	27	0	0	5019	7	17	11	9	80037	1	6	6	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	30	0	0	0	2	80025	2	16	16	25	160010	10	160000	10	160000	50	800964	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160013	13	42	0	160053	0	1	51	160038	6	1	51	42	13	0	5019	7	17	8	6	80037	0	9	9	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	1	1	1	0	0	0	57	0	1	0	2	80025	2	16	16	25	160010	10	160000	10	160000	50	800970	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5019	10	17	11	22	80037	1	6	6	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	30	0	0	0	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800219	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5019	9	17	11	9	80037	1	6	6	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	30	0	0	0	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800219	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	27	0	160024	0	0	24	160024	6	1	24	27	0	0	5019	10	17	7	10	80037	1	6	6	2	160000	160000	10	80041	80041	80041	80041	80041

LD1 (multiple, 4 regs, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations