Firestorm: LD1 (multiple, 4 regs, 4H) measurements

Code:

  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	3a	3f	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28958	215	1	19	1	18	0	1	0	0	0	44	1	4917	28176	0	0	23430	2000	2000	2000	10000	4	0	0	16256	28276	28702	3	10	2000	4000	2000	28591	28692	1	1	61001	1000	1000	0	2002	4	0	2002	0	1	1	2	2000	6	2	6	2	1	13718	10169	7002	3269	12	45	19856	3334	3816	44	42	39	28208	15054	12433	13974	2000	2000	28781	28496	28580	28488	28719
64004	28694	215	1	16	1	18	0	0	0	0	0	10	1	5000	28151	0	2	23493	2000	2000	2000	10000	5	0	0	16334	28364	28882	3	10	2000	4000	2000	28628	28599	1	1	61001	1000	1000	1	2003	3	6	2004	0	0	0	2	2002	6	4	6	2	1	13683	10188	7196	3287	11	36	19507	3369	3816	39	33	31	28289	14659	12630	14078	2000	2000	28735	28592	28494	28605	28763
64004	28656	215	1	12	0	19	1	0	0	0	0	8	0	4995	28423	0	0	23645	2000	2000	2000	10000	7	0	0	16405	28124	28575	3	10	2000	4000	2000	28705	28472	1	1	61001	1000	1000	0	2004	5	0	2004	0	0	0	2	2004	6	2	0	2	2	13498	10128	7137	3366	10	38	19625	3414	3813	41	36	32	28204	14476	12262	14133	2000	2000	28775	28788	28649	28871	28769
64004	28829	215	1	19	1	17	1	0	0	0	0	8	0	4967	28390	2	0	23370	2000	2000	2000	10001	6	0	0	16416	28367	28693	3	10	2000	4000	2000	28715	28600	1	1	61001	1000	1000	0	2004	4	6	2004	0	0	2	2	2000	4	2	6	2	1	13838	10200	7061	3391	9	39	19707	3202	3814	42	39	35	28284	14828	12716	13942	2000	2000	28859	28735	28715	28446	28731
64005	28742	215	1	16	1	17	1	0	0	0	0	3	1	5094	28390	0	0	23609	2000	2000	2000	10000	5	0	0	16429	28406	28913	3	10	2000	4000	2000	28552	28506	1	1	61001	1000	1000	0	2003	2	0	2002	0	0	2	2	2000	0	4	0	2	1	14020	10076	7106	3338	10	39	19704	3393	3815	43	40	34	28155	14944	12694	13880	2000	2000	28745	28636	28656	28564	28673
64004	28756	214	1	14	0	14	0	0	0	0	0	3	0	4939	28347	0	0	23501	2000	2000	2000	10000	3	0	9	16421	28396	28896	3	10	2000	4000	2000	28462	28512	1	1	61001	1000	1000	0	2004	3	0	2007	0	0	2	2	2000	6	2	0	2	2	13902	9945	7111	3360	12	40	19689	3417	3815	41	40	35	28125	14795	12671	14029	2000	2000	28792	28646	28708	28694	28636
64004	28690	214	1	10	1	14	1	0	0	0	0	10	1	4899	28417	0	0	23607	2000	2000	2000	10000	5	0	0	16263	28413	28651	3	10	2000	4000	2000	28437	28530	1	1	61001	1000	1000	0	2003	3	6	2002	0	0	2	2	2000	4	4	6	2	1	13758	10159	7068	3339	10	34	19864	3342	3813	40	44	32	28225	14737	12895	14080	2000	2000	28611	28448	28364	28655	28674
64004	28711	215	1	14	1	13	1	0	0	0	0	8	0	4950	28156	0	0	23319	2000	2000	2000	10000	4	0	0	16414	28252	28535	3	10	2000	4000	2000	28394	28597	1	1	61001	1000	1000	0	2003	3	0	2003	0	0	2	2	2000	4	2	6	2	2	13752	10161	7113	3305	7	40	19581	3404	3814	43	32	37	28201	15296	12929	14131	2000	2000	28832	28619	28540	28752	28824
64004	28594	215	1	14	1	14	1	0	0	0	0	6	0	5055	28259	0	0	23561	2000	2000	2000	10000	4	0	0	16405	28265	28677	3	10	2000	4000	2000	28507	28507	1	1	61001	1000	1000	0	2004	4	0	2004	0	0	2	2	2000	0	2	6	2	0	13842	10158	7147	3330	7	38	19670	3327	3810	48	42	41	28101	14456	12430	14145	2000	2000	28694	28517	28716	28438	28670
64004	28723	215	1	12	0	17	1	1	1	0	0	2	0	5039	28285	0	0	23451	2000	2000	2000	10000	0	0	0	16411	28277	28604	3	10	2000	4000	2000	28629	28650	1	1	61001	1000	1000	0	2003	3	6	2003	0	1	1	4	2000	4	2	6	2	1	13546	10044	7058	3397	11	44	19673	3294	3814	41	37	35	28301	15213	12850	14345	2000	2000	28716	28700	28475	28579	28801

Count: 8

Code:

  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	599	1	1	1	1	0	1	58	0	0	2	80026	2	5	5	3	27	160112	100	160012	100	160016	500	801463	0	80022	80041	80041	0	6	12	160116	200	320032	200	160016	80042	80041	1	1	80201	100	99	100	100	80000	80000	1	100	160019	13	43	160056	0	2	51	160043	6	1	13	43	13	1	1	1	1	5116	0	16	0	0	80039	13	0	5	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	599	1	1	0	0	1	1	61	0	0	2	80028	2	5	5	3	28	160112	100	160012	100	160016	500	801448	0	80022	80041	80041	0	6	12	160116	200	320032	200	160016	80042	80041	2	1	80201	100	99	100	100	80000	80000	0	100	160018	14	43	160018	0	0	13	160043	6	1	51	43	13	0	1	1	1	5117	0	16	0	0	80038	13	13	5	160000	160000	100	80042	80042	80042	80042	80042
320204	80041	599	1	0	0	1	0	0	12	1	0	2	80027	0	5	5	0	27	160112	100	160012	100	160016	500	800124	0	80022	80041	80041	0	6	12	160116	200	320032	200	160016	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160018	13	43	160057	0	0	55	160043	0	1	52	43	13	0	1	1	1	5117	0	16	0	0	80038	13	13	0	160000	160000	100	80043	80042	80042	80042	80042
320204	80041	599	1	0	1	1	0	0	18	0	0	2	80026	2	5	5	0	27	160112	100	160012	100	160016	500	800137	0	80022	80041	80041	0	7	12	160116	200	320032	200	160090	80041	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160017	12	0	160057	0	0	52	160043	6	1	13	0	13	1	1	1	1	5116	0	16	0	0	80038	13	13	5	160000	160000	100	80042	80042	80042	80043	80042
320204	80041	599	1	0	1	1	1	1	58	0	0	2	80026	2	0	5	3	27	160100	100	160000	100	160000	500	800042	0	80015	80040	80040	0	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	1	100	160014	14	0	160053	3	1	52	160000	6	1	52	0	13	1	0	0	0	5109	1	17	1	1	80037	0	13	5	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	1	0	0	0	0	1	57	1	0	2	80025	2	5	5	3	25	160100	100	160000	100	160000	500	801382	0	80015	80040	80040	0	3	35	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160013	14	0	160014	0	2	51	160000	0	0	52	43	13	0	0	0	0	5109	1	17	1	1	80037	0	0	5	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	1	1	1	0	0	1	57	0	0	2	80090	0	5	0	0	25	160100	100	160000	100	160000	500	801386	0	80015	80040	80040	0	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160012	14	43	160051	1	0	51	160000	0	0	12	43	13	0	0	0	0	5109	1	17	1	1	80037	13	13	0	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	1	0	1	0	1	1	13	0	0	0	80025	2	5	5	0	25	160100	100	160000	100	160000	500	801377	0	80015	80040	80040	0	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160013	14	43	160054	0	0	13	160039	0	0	13	0	13	2	0	0	0	5109	1	17	1	1	80037	0	13	5	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	1	1	1	1	1	1	720	1	0	2	80025	2	5	0	0	25	160100	100	160000	100	160000	500	800043	0	80015	80040	80040	2	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160012	14	0	160052	0	0	13	160000	0	0	13	0	13	1	0	0	0	5109	1	17	1	1	80037	0	13	5	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	1	1	1	1	0	0	58	0	0	2	80025	2	5	5	3	25	160100	100	160000	100	160000	500	800048	0	80015	80040	80040	0	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160014	13	43	160052	0	0	52	160000	0	1	52	43	12	0	0	0	0	5109	1	17	1	1	80037	13	13	0	160000	160000	100	80041	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80054	600	0	0	0	1	0	0	42	0	1	0	2	80025	2	12	12	0	25	160010	10	160000	10	160000	50	800853	4	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80102	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160036	0	0	36	160000	6	1	32	40	0	0	0	5019	4	17	2	3	80037	0	14	0	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	0	0	0	0	0	0	42	0	1	0	2	80025	2	12	12	0	25	160010	10	160000	10	160000	50	800853	4	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	40	160000	0	0	36	160036	6	1	0	35	0	0	0	5019	4	17	4	4	80037	0	10	0	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	1	0	0	42	0	0	0	2	80025	0	12	0	0	25	160010	10	160000	10	160000	50	800375	8	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160000	0	0	36	160000	0	1	32	0	0	0	0	5019	4	17	4	3	80037	0	14	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	1	1	0	42	0	1	0	2	80025	2	0	0	0	25	160010	10	160000	10	160000	50	800374	8	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	160036	0	1	0	160036	0	1	32	35	0	0	0	5019	4	17	4	3	80037	0	14	14	0	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	38	0	1	0	2	80025	2	12	12	0	25	160010	10	160000	10	160000	50	800377	7	0	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160036	0	0	36	160000	6	1	0	40	0	0	0	5019	4	17	3	4	80037	0	10	14	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	0	0	0	0	2	80025	2	12	12	0	25	160010	10	160000	10	160000	50	800000	7	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	0	32	160032	0	1	0	40	0	0	0	5019	4	17	4	4	80037	0	14	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	0	0	0	1	1	0	38	0	1	0	0	80025	2	12	12	0	25	160010	10	160000	10	160000	50	800000	8	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160036	0	0	36	160000	0	1	0	40	0	0	0	5019	3	17	4	4	80037	0	14	14	0	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	42	0	0	0	2	80025	0	12	12	0	25	160010	10	160000	10	160000	50	800374	7	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160000	0	0	39	160032	6	0	0	40	0	0	0	5019	3	17	4	4	80037	0	14	14	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	0	0	38	0	0	0	0	80025	2	12	12	0	25	160010	10	160000	10	160000	50	800374	7	1	80015	80040	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	160032	0	0	0	160032	0	1	36	40	0	0	0	5019	4	17	4	4	80037	1	14	0	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	0	0	1	0	42	0	0	0	2	80025	2	0	12	0	25	160086	10	160000	10	160000	50	800372	8	1	80015	80117	80040	0	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	160036	0	1	36	160000	0	1	36	40	0	0	0	5019	4	17	3	4	80037	0	0	10	0	160000	160000	10	80041	80041	80041	80041	80041

LD1 (multiple, 4 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations