Firestorm: LD1 (multiple, 4 regs, 4S) measurements

Code:

  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
64005	28621	215	5	1	2	0	0	8	0	1	0	4973	28070	2	4	0	22352	4000	4000	4000	20709	2	16967	28238	28723	3	10	4000	4000	4000	28274	28168	1	1	61001	1000	1000	0	4000	8	4006	0	0	0	4002	4	1	6	8	13383	10652	7080	3372	0	44	19392	3561	3807	39	37	39	28147	14283	12153	12699	4000	28312	28256	28278	28467	28428
64004	28582	215	0	0	0	1	0	8	0	1	0	4892	28157	2	0	4	22504	4000	4000	4000	20706	3	16947	27986	28488	3	10	4000	4000	4000	28280	28381	1	1	61001	1000	1000	1	4000	8	4002	0	1	2	4002	0	0	6	0	14176	10396	7120	3289	1	39	19345	3236	3813	43	46	38	27951	14051	11893	12589	4000	28320	28388	28337	28312	28847
64004	28410	212	0	0	0	0	0	8	0	0	0	5230	27988	2	0	0	22569	4000	4000	4000	20705	2	16957	27989	28253	3	10	4000	4000	4000	28687	28409	1	1	61001	1000	1000	0	4000	0	4006	0	0	4	4004	4	0	0	0	13935	10472	7158	3306	0	37	19623	3452	3807	40	40	34	27933	14014	12859	12986	4000	28740	28315	28334	28511	28527
64004	28505	213	0	0	0	0	0	0	0	0	0	4954	28055	2	0	4	22307	4000	4000	4000	20700	0	16971	27990	28409	3	10	4000	4000	4000	28477	28825	1	1	61001	1000	1000	0	4000	8	4000	0	0	6	4004	6	1	4	8	14048	10467	7091	3352	0	33	19905	3572	3814	40	36	40	28009	14112	11903	13165	4000	28340	28138	28442	28886	28385
64004	28840	212	0	0	0	0	0	0	0	0	0	5325	28398	2	0	0	22789	4000	4000	4000	20711	9	16969	28072	28529	3	10	4000	4000	4000	28659	28732	1	1	61001	1000	1000	0	4000	8	4003	0	1	6	4000	6	1	0	8	14226	9937	7101	3426	0	38	19502	3552	3812	43	44	35	28014	14276	12188	12505	4000	28862	28370	28457	28276	28429
64004	28346	213	0	0	0	0	0	8	0	0	0	5191	28130	0	4	0	22437	4000	4000	4000	20710	1	16966	28093	28395	3	10	4000	4000	4000	28292	28839	1	1	61001	1000	1000	0	4000	8	4004	0	0	2	4006	0	0	6	8	14128	9781	7089	3522	0	41	19629	3345	3814	41	35	34	27948	14665	11788	12619	4000	28366	28488	28413	28290	28461
64004	28436	216	0	0	0	0	0	8	0	0	0	5161	28020	0	0	4	22497	4000	4000	4000	20711	4	16976	28098	28487	3	10	4000	4000	4000	28312	28512	1	1	61001	1000	1000	0	4000	8	4004	0	0	2	4003	0	1	0	8	14207	10242	7092	3451	0	38	19741	3455	3810	43	40	37	28040	14282	11771	13939	4000	28920	28457	28450	28284	28800
64004	28486	216	0	0	0	0	0	8	0	1	0	4816	28058	2	4	4	22446	4000	4000	4000	20713	3	16987	28028	28537	3	10	4000	4000	4000	28501	28431	1	1	61001	1000	1000	0	4000	8	4000	0	1	0	4000	6	1	2	8	13984	10109	7139	3292	1	42	19662	3489	3813	40	40	39	28193	14667	12638	12776	4000	28296	28492	28552	28311	28489
64004	28476	217	0	0	0	0	0	8	0	0	0	4833	28258	2	4	4	22400	4000	4000	4000	20710	4	16921	28149	28442	3	10	4000	4000	4000	28831	28537	1	1	61001	1000	1000	1	4000	8	4006	0	0	2	4003	6	1	2	8	14046	10088	7155	3508	0	47	19444	3459	3806	36	37	31	28028	15208	12106	14072	4000	28243	28712	28437	28947	28662
64004	28409	213	0	0	0	0	0	8	0	0	0	5010	28082	2	0	0	22499	4000	4000	4000	20719	4	16967	28057	28367	3	10	4000	4000	4000	28695	28399	1	1	61001	1000	1000	0	4000	8	4004	0	0	6	4003	5	0	2	8	14342	10373	7183	3352	1	35	19745	3442	3809	40	40	39	28073	14431	12211	13031	4000	28333	28285	28318	28408	28466

Count: 8

Code:

  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	106730	799	0	0	0	0	0	0	0	1	0	0	106712	2	12	1	0	25	320100	100	320000	100	320000	500	4698976	0	106702	106727	106727	26675	3	26689	320100	200	320000	200	320000	106733	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	43	0	320039	0	39	320039	6	1	39	0	0	0	5110	1	17	1	1	106724	0	10	0	7	320000	100	106708	106728	106728	106708	106708
320204	106727	800	0	0	0	0	0	45	0	0	0	1	106716	0	12	0	16	25	320100	100	320000	100	320000	500	4705621	0	107115	106707	106707	26655	3	26713	320100	200	320000	200	320000	106727	106707	1	1	80201	100	99	100	100	80000	80000	1	100	320000	43	0	320039	0	39	320039	6	0	0	43	0	0	5109	1	17	1	1	106704	0	0	10	4	320000	100	106708	106728	106708	106708	106728
320204	106727	799	0	0	0	0	0	45	0	0	0	0	106712	2	1	1	16	25	320100	100	320000	100	320000	500	4709628	0	106682	106727	106727	26679	3	26689	320100	200	320000	200	320000	106727	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	43	0	320039	0	39	320039	6	1	38	44	0	0	5109	1	35	1	1	106724	0	10	14	4	320000	100	106728	107083	106869	106732	106728
320204	106707	799	0	0	0	0	0	44	0	1	0	1	106713	2	0	12	0	25	320100	100	320000	100	320000	500	4728183	0	106682	106727	106731	26655	3	26709	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	320039	0	0	320039	6	0	39	0	0	0	5109	1	17	1	1	106724	0	14	10	7	320000	100	106728	106708	106728	106728	106728
320204	106736	799	0	0	0	0	0	0	0	1	0	1	106692	0	1	12	16	25	320100	100	320000	100	320000	500	4728183	1	106702	106727	106727	26655	3	26709	320100	200	320000	200	320000	106727	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	43	0	320000	0	39	320000	0	1	39	43	0	0	5110	1	17	1	1	106724	0	0	10	7	320000	100	106708	106708	106708	106728	106708
320204	106707	799	0	0	0	0	0	45	0	1	0	1	106716	2	12	0	16	25	320100	100	320000	100	320000	500	4673754	0	106706	106727	106727	26655	3	26709	320100	200	320000	200	320000	106727	106731	1	1	80201	100	99	100	100	80000	80000	0	100	320000	43	0	320039	0	38	320000	6	1	0	43	0	0	5110	1	17	1	1	106724	0	10	10	4	320000	100	106732	106728	106732	106732	106731
320204	106731	799	0	0	0	0	0	44	0	0	0	0	106715	2	12	1	0	25	320100	100	320000	100	320000	500	4709628	1	106702	106727	106727	26675	3	26709	320100	200	320000	200	320000	106727	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	320000	0	39	320039	6	1	39	43	0	0	5109	1	17	1	1	106724	0	10	0	0	320000	100	106728	106728	106728	106732	106708
320204	106750	799	0	0	0	0	0	45	0	0	0	1	106712	2	12	12	16	25	320100	100	320000	100	320000	500	4728183	1	106706	106707	106727	26679	3	26709	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	43	0	320039	0	39	320039	0	1	39	43	0	0	5110	1	17	1	1	106728	0	10	10	7	320000	100	106870	106708	106708	106728	106708
320204	106707	799	0	0	0	0	0	45	0	1	0	1	106712	2	0	12	16	25	320100	100	320000	100	320000	500	4673754	1	106682	106727	106727	26675	3	26709	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	43	0	320039	0	39	320000	6	1	39	43	0	0	5110	1	17	1	1	106724	0	10	10	4	320000	100	106728	106728	106708	106728	106728
320204	106727	799	0	0	0	0	0	45	0	1	0	1	106712	2	12	12	16	25	320100	100	320000	100	320000	500	4709628	1	106706	106727	106730	26675	3	26709	320100	200	320000	200	320000	106707	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	43	0	320039	2	39	320039	6	1	0	0	0	0	5109	1	17	1	1	107020	0	10	10	7	320000	100	106728	106732	106728	106708	106708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.3340

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	106722	799	1	0	0	0	41	0	1	0	0	2	106712	2	0	12	12	25	320010	10	320000	10	320000	50	4685107	1	106697	106707	106722	26670	3	26689	320010	20	320000	20	320000	106731	106707	1	1	80021	10	9	10	10	80000	80000	1	10	320000	39	0	320035	0	35	320000	6	1	35	39	0	0	5020	1	17	0	1	1	106720	0	6	2	320000	10	106723	106723	106723	106723	106728
320024	106707	800	1	1	0	0	44	0	1	0	0	2	106707	3	18	12	16	25	320010	10	320000	10	320000	50	4728183	1	106702	106722	106707	26675	3	26709	320010	20	320000	20	320000	106727	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	39	0	320039	0	39	320039	6	1	35	0	0	0	5019	1	17	0	1	1	106724	10	6	0	320000	10	106904	106881	106774	106723	106708
320024	106722	799	0	0	0	0	0	0	1	0	0	2	106712	2	18	18	0	25	320010	10	320000	10	320000	50	4685107	1	106705	106707	106707	26655	3	26689	320010	20	320000	20	320000	106727	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	39	0	320039	0	39	320000	6	0	36	39	0	0	5019	1	17	0	1	1	106724	0	6	0	320000	10	106728	106723	106708	106723	106723
320024	106727	799	0	0	0	0	45	0	0	0	0	2	106712	2	12	18	16	25	320010	10	320000	10	320000	50	4673754	1	106702	106707	106707	26655	3	26709	320010	20	320000	20	320000	106722	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	39	0	320039	0	3	320000	6	1	35	0	0	0	5075	1	17	0	1	1	106724	10	0	4	320000	10	106708	106708	106708	106728	106728
320024	106722	799	0	0	0	0	0	0	0	0	0	1	106692	0	0	0	12	25	320010	10	320000	10	320000	50	4685107	1	106697	106727	106707	26675	3	26709	320010	20	320000	20	320000	106727	106707	1	1	80021	10	9	10	10	80000	80000	0	10	320000	39	0	320035	0	39	320000	6	1	35	43	0	0	5019	1	17	0	1	1	106704	10	0	2	320000	10	106723	106708	106728	106723	106708
320024	106727	799	0	0	0	0	48	0	0	0	0	0	106712	2	12	12	12	25	320010	10	320000	10	320000	50	4685107	1	106697	106707	106708	26670	3	26704	320010	20	320000	20	320000	106722	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	320000	1	0	320035	6	1	0	39	0	0	5019	1	17	0	1	1	106724	10	6	2	320000	10	106709	106728	106708	106728	106728
320024	106727	799	0	0	0	0	0	0	0	0	0	0	106710	2	0	18	14	25	320010	10	320000	10	320000	50	4709628	1	106682	106727	106727	26675	3	26704	320010	20	320000	20	320000	106727	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	0	0	320000	0	35	320035	6	0	35	39	0	0	5019	1	17	0	1	1	106724	0	6	4	320000	10	106728	106728	106711	106728	106728
320024	106707	799	0	0	0	0	45	0	0	0	0	1	106729	0	0	18	0	25	320010	10	320000	10	320000	50	4698880	1	106682	106722	106722	26670	3	26689	320010	20	320000	20	320000	106727	106722	1	1	80021	10	9	10	10	80000	80000	1	10	320000	0	0	320039	0	39	320039	0	0	39	0	0	0	5019	1	17	0	1	1	106722	6	6	2	320000	10	106723	106723	106708	106723	106723
320024	106707	799	0	1	0	0	50	0	1	0	0	1	106707	2	12	12	16	25	320010	10	320000	10	320000	50	4709628	1	106702	106727	106707	26655	3	26709	320010	20	320000	20	320000	106722	106707	1	1	80021	10	9	10	10	80000	80000	0	10	320000	39	0	320039	0	0	320035	0	1	0	0	0	0	5072	1	17	0	1	1	106724	0	0	2	320000	10	106726	106723	106708	106723	106723
320024	106722	799	1	1	0	0	41	0	1	0	0	2	106712	2	18	18	0	25	320010	10	320000	10	320000	50	4709628	1	106697	106727	106707	26675	3	26689	320010	20	320000	20	320000	106707	106722	1	1	80021	10	9	10	10	80000	80000	0	10	320000	39	0	320039	0	0	320039	6	0	39	43	0	0	5019	1	17	1	1	1	106708	0	6	4	320000	10	106708	106728	106728	106708	106728

LD1 (multiple, 4 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations