Firestorm: LD1 (multiple, 4 regs, 8B) measurements

Code:

  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 2.000

Integer unit issues: 0.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
64005	28645	213	0	19	14	0	1	1	0	0	6	0	1	0	5223	28472	0	2	2	23043	2000	2000	2000	10000	3	0	0	16235	27963	28613	3	10	2000	4000	2000	28341	28369	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	0	0	2004	4	4	4	0	0	13618	10289	7243	3437	8	61	19766	3370	3823	11	54	49	28064	14061	12504	13770	2000	2000	28154	28144	28237	28190	28224
64004	28165	213	1	14	20	0	0	0	0	0	6	0	0	0	5208	27959	0	2	0	23446	2000	2000	2000	10000	2	0	0	16304	28209	28291	3	10	2000	4000	2000	28380	28494	1	1	61001	1000	1000	0	2004	2	0	2003	0	0	2	2	2002	2	0	4	0	0	13589	9595	7248	3403	11	47	19219	3279	3817	18	39	40	27870	14103	12819	13596	2000	2000	28301	28301	28228	28321	28388
64004	28239	213	0	18	14	1	0	0	1	0	3	0	1	0	5066	28096	0	1	0	23361	2000	2000	2000	10000	5	0	0	16258	27897	28467	3	10	2000	4000	2000	28453	28140	1	1	61001	1000	1000	0	2004	3	6	2003	1	3	1	2	2000	0	2	4	0	0	13777	9806	7168	3275	6	47	19490	3274	3819	17	43	49	27977	14313	12546	14154	2000	2000	28299	28476	28560	28365	28569
64004	28314	214	0	21	19	1	0	1	0	0	17	0	1	0	4941	28240	0	2	0	23305	2000	2000	2000	10000	9	0	0	16240	27989	28495	3	10	2000	4000	2000	28252	28110	1	1	61001	1000	1000	1	2000	0	4	2002	0	0	0	0	2000	0	4	4	0	0	13902	10250	7144	3446	5	49	19131	3429	3813	15	53	52	28102	14548	12114	14286	2000	2000	28386	28155	28431	28321	28779
64004	28543	214	0	12	14	1	0	0	0	0	2	0	1	0	5162	28336	0	0	0	22968	2000	2000	2000	10000	2	0	0	16246	28000	28217	3	10	2000	4000	2000	28409	28050	1	1	61001	1000	1000	0	2002	3	4	2004	0	0	0	2	2000	2	0	4	0	0	13885	10400	7182	3330	10	49	19604	3484	3817	18	51	52	27735	14197	12073	13476	2000	2000	28572	28466	28253	28421	28500
64004	28135	211	0	18	25	0	0	0	0	0	6	0	0	0	4962	28091	0	2	0	23405	2000	2000	2000	10000	5	0	0	16246	27902	28216	3	10	2000	4000	2000	28125	28040	1	1	61001	1000	1000	0	2003	4	4	2002	0	2	2	4	2000	4	2	6	2	1	13725	10240	7185	3404	10	50	19208	3268	3811	9	43	46	28063	13983	12079	13690	2000	2000	28177	28155	28488	28177	28433
64004	28421	212	1	15	20	0	1	0	0	0	4	0	1	0	5016	27974	0	0	0	23042	2000	2000	2000	10000	9	0	0	16254	28059	28168	3	10	2000	4000	2000	28409	28511	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	2	2000	4	2	6	2	3	13943	10200	7220	3417	9	52	19530	3344	3817	16	42	44	27833	13748	12550	13623	2000	2000	28322	28227	28218	28136	28483
64004	28299	211	1	19	26	0	0	0	0	0	20	0	0	0	5145	27967	0	0	0	23000	2000	2000	2000	10000	5	0	0	16265	27985	28332	3	10	2000	4000	2000	28292	28136	1	1	61001	1000	1000	0	2004	4	4	2003	1	1	1	2	2002	2	2	0	0	0	13573	10442	7236	3424	9	45	19140	3254	3818	10	44	41	28016	14666	12461	13786	2000	2000	28152	28442	28492	28113	28194
64004	28206	211	0	22	23	0	0	0	0	0	12	0	1	0	5005	28312	2	2	2	23365	2000	2000	2000	10000	9	0	0	16280	27877	28355	3	10	2000	4000	2000	28112	28222	1	1	61001	1000	1000	0	2004	3	0	2003	0	0	2	2	2000	4	4	6	2	1	13796	10063	7169	3317	11	43	19204	3369	3813	13	47	41	28070	14128	12152	13964	2000	2000	28461	28134	28347	28321	28543
64004	28361	211	1	18	15	0	0	1	2	0	38	0	0	0	5173	28171	0	0	2	22936	2000	2000	2000	10000	4	0	0	16275	27947	28424	3	10	2000	4000	2000	28161	28040	1	1	61001	1000	1000	0	2004	4	0	2005	0	1	1	7	2000	4	2	4	2	2	13641	10074	7049	3320	9	47	19387	3298	3818	13	48	50	27851	14632	12499	13146	2000	2000	28261	28513	28305	28275	28136

Count: 8

Code:

  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]
  ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80067	599	0	0	1	0	1	1	0	0	38	0	0	0	1	80025	2	12	12	0	25	160100	100	160000	100	160000	500	800000	0	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	27	160032	0	32	160042	6	1	24	0	0	0	5109	2	17	2	2	80037	1	6	6	0	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	0	0	0	0	0	0	0	0	38	0	0	0	0	80025	2	12	12	0	25	160100	100	160000	100	160000	500	800375	0	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	1	100	160000	27	160000	0	32	160032	6	0	24	35	0	0	5109	2	17	2	2	80037	1	0	0	0	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	0	0	0	0	0	38	0	1	0	0	80025	0	12	12	0	25	160100	100	160000	100	160000	500	800377	0	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160032	0	32	160024	6	0	24	27	0	0	5109	2	17	2	3	80037	0	0	6	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	0	0	0	0	0	0	0	0	0	0	0	0	1	80025	0	12	12	0	25	160100	100	160000	100	160000	500	800222	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	27	160032	0	24	160024	6	1	0	35	0	0	5109	2	17	2	2	80037	0	10	10	0	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	600	0	0	0	0	0	0	0	0	0	0	1	0	1	80025	2	12	12	0	25	160100	100	160000	100	160000	500	800217	0	80015	0	80040	80040	3	22	160174	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160000	1	24	160024	6	1	32	0	0	0	5109	2	17	2	2	80037	1	10	6	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	0	0	0	0	0	0	0	0	38	0	0	0	0	80025	0	12	0	0	25	160100	100	160000	100	160000	500	800248	1	80015	0	80040	80040	3	22	160100	200	320592	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	27	160032	0	24	160024	6	1	24	35	0	0	5109	2	17	2	2	80037	1	10	0	0	160000	160000	100	80041	80041	80041	80041	80041
320204	80383	600	0	0	0	0	0	0	0	0	38	0	0	0	1	80025	2	0	0	0	25	160100	100	160000	100	160000	500	800216	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160000	0	32	160032	6	1	24	36	0	0	5109	2	20	2	2	80037	0	6	6	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	602	0	0	1	0	0	0	0	0	38	0	0	0	0	80025	2	12	12	0	25	160100	100	160000	100	160000	500	801620	0	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160000	0	0	160000	6	1	24	0	0	0	5109	2	17	3	2	80037	0	10	6	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80040	599	1	0	1	0	0	0	0	0	38	0	1	0	1	80025	0	0	12	0	25	160100	100	160000	100	160000	500	800377	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	35	160032	0	0	160024	6	1	0	35	0	0	5109	2	17	2	2	80037	0	10	6	2	160000	160000	100	80041	80041	80041	80041	80041
320204	80102	600	0	0	0	0	0	0	0	0	0	0	1	0	1	80025	2	0	12	0	25	160100	100	160000	100	160000	500	802291	1	80015	0	80040	80040	3	22	160100	200	320000	200	160000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	160032	2	32	160024	6	1	32	35	0	0	5109	3	17	2	2	80037	0	0	6	2	160000	160000	100	80041	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80041	600	0	0	38	1	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800377	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	61	0	32	160032	6	1	0	35	1	0	5019	0	2	17	2	4	80037	1	0	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	0	0	38	1	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800377	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	32	160000	6	0	0	35	0	0	5019	0	2	17	3	4	80037	1	10	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	0	0	38	0	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800374	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80049	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	32	160032	6	1	0	35	0	0	5019	0	2	17	3	3	80037	1	10	10	0	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	38	1	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800374	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	0	160032	6	1	0	35	0	0	5019	0	2	17	3	2	80037	1	10	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	38	1	0	80025	2	12	0	25	160010	10	160000	10	160000	50	800377	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	5	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	32	160032	6	1	32	35	0	0	5019	0	3	17	3	3	80037	1	10	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	0	0	0	1	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800000	0	80015	3	80040	80040	3	22	160010	20	320000	20	160000	80040	80051	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	32	160032	6	1	32	35	0	0	5019	4	3	17	2	3	80037	1	10	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	38	1	0	80025	2	12	0	25	160010	10	160000	10	160000	50	800000	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	32	160032	6	1	32	35	0	0	5019	0	3	17	3	3	80037	1	10	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	599	0	0	38	1	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800377	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	32	160032	6	1	32	35	0	1	5019	0	3	17	2	3	80037	1	10	10	2	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	0	1	38	1	0	80025	2	12	12	25	160010	10	160000	10	160000	50	800376	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	32	160032	6	1	32	35	0	0	5019	0	4	17	3	2	80037	0	0	10	0	160000	160000	10	80041	80041	80041	80041	80041
320024	80040	600	1	1	38	1	0	80025	2	12	12	25	160010	10	160000	10	160000	50	801080	0	80015	0	80040	80040	3	22	160010	20	320000	20	160000	80040	80040	5	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160032	0	0	32	160032	6	1	32	35	0	0	5019	0	3	17	2	3	80037	1	10	10	2	160000	160000	10	80041	80041	80041	80041	80041

LD1 (multiple, 4 regs, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations