Firestorm: LD1 (multiple, 4 regs, 8H) measurements

Code:

  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0e	0f	18	1e	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
64005	29528	220	35	1	26	0	0	0	12	0	0	4518	29097	0	1	1	23269	4000	4000	4000	20711	0	16912	28727	29271	3	10	4000	4000	4000	29101	29229	1	1	61001	1000	1000	0	4000	0	8	4003	0	1	0	2	4003	0	1	0	0	0	12962	9097	6843	3085	11	80	20285	3082	3819	13	53	55	28386	16233	13264	15038	4000	29186	29212	29213	29351	29275
64004	29310	220	24	1	23	1	1	0	9	0	0	4728	29131	0	0	0	23461	4000	4000	4000	20711	2	16986	28679	29327	3	10	4000	4000	4000	29227	29104	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	0	4002	6	0	3	8	0	13141	9197	6818	3108	10	57	20262	3063	3824	15	53	58	28420	16545	13382	15011	4000	29296	29335	29286	29361	29291
64004	29322	220	25	0	24	0	1	0	5	0	0	4557	29122	0	0	0	23409	4000	4000	4000	20701	0	16949	28829	29292	3	10	4000	4000	4000	29144	29189	1	1	61001	1000	1000	0	4000	0	8	4003	0	0	0	2	4002	5	1	3	0	0	13157	9168	6930	3182	6	58	20329	3064	3823	16	50	55	28450	16143	13219	15049	4000	29227	29355	29272	29287	29363
64004	29290	219	32	0	24	0	0	0	9	0	0	4583	29136	0	0	0	23268	4000	4000	4000	20723	0	16936	28773	29311	3	10	4000	4000	4000	29198	29105	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	8	4002	5	1	2	0	0	13118	9392	6872	3079	9	60	20336	3227	3823	10	59	62	28498	16204	13444	14990	4000	29359	29313	29341	29314	29237
64004	29335	218	28	0	21	1	1	0	0	0	0	4608	29044	0	0	0	23268	4000	4000	4000	20718	0	16961	28695	29217	3	10	4000	4000	4000	29024	29067	1	1	61001	1000	1000	0	4000	0	8	4003	0	0	0	2	4000	6	1	3	0	0	12969	9293	6862	3163	11	59	20313	3139	3817	14	60	65	28517	16156	13482	15129	4000	29320	29318	29471	29388	29370
64004	29375	219	22	0	20	0	1	0	8	0	0	4600	29175	0	0	0	23320	4000	4000	4000	20707	1	16940	28686	29298	3	10	4000	4000	4000	29204	29195	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	2	4002	6	1	0	0	0	12896	9133	6915	3131	10	61	20330	3153	3821	11	55	49	28382	16400	13442	14937	4000	29342	29299	29252	29300	29324
64004	29248	220	23	1	28	1	1	0	0	1	0	4661	29115	0	0	0	23238	4000	4000	4000	20708	0	16937	28667	29215	3	10	4000	4000	4000	29146	29151	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	3	4002	0	1	3	0	0	12904	9118	6820	3159	9	61	20206	3119	3817	14	57	58	28475	16300	13272	15073	4000	29304	29343	29375	29329	29275
64004	29264	219	24	0	20	0	1	0	5	0	0	4654	29080	0	0	0	23243	4000	4000	4000	20705	0	16945	28623	29253	3	10	4000	4000	4000	29137	29156	1	1	61001	1000	1000	0	4000	0	0	4003	0	0	0	2	4000	6	1	3	8	0	12792	9362	6801	3133	7	57	20283	3120	3817	9	60	51	28495	16096	13330	14907	4000	29236	29251	29276	29242	29385
64004	29376	220	29	0	23	1	0	0	8	0	0	4532	29158	0	4	0	23342	4000	4000	4000	20711	3	16949	28624	29326	3	10	4000	4000	4000	29192	29149	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	0	4003	5	1	0	8	0	12985	9282	6869	3042	9	58	20221	3098	3823	21	54	51	28493	16430	13224	14869	4000	29358	29297	29233	29271	29292
64004	29247	219	28	1	24	1	1	0	8	0	0	4592	29070	0	0	0	23279	4000	4000	4000	20710	0	16942	28712	29333	3	10	4000	4000	4000	29088	29176	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	5	4002	6	1	2	8	0	12914	9128	6939	3057	9	61	20232	3125	3822	20	59	55	28579	16076	13293	14887	4000	29304	29322	29262	29358	29318

Count: 8

Code:

  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	106730	800	0	0	1	0	0	0	0	0	1	0	1	106712	2	1	12	134	25	320100	100	320000	100	320018	500	4730685	0	106682	0	106707	106731	26657	6	26680	320117	200	320024	200	320024	106727	106727	1	1	80201	100	99	100	100	80000	80000	1	100	320000	0	43	0	320039	0	0	0	0	320038	6	0	39	44	0	1	1	1	5116	0	16	0	0	106728	14	10	0	320000	100	106732	106732	106708	106732	106728
320204	106731	800	0	0	0	0	0	0	44	0	0	0	1	106712	3	0	12	16	25	320100	100	320000	100	320018	500	4709717	0	106702	0	106727	106727	26657	6	26704	320119	200	320024	200	320024	106731	106727	1	1	80201	100	99	100	100	80000	80000	1	100	320000	0	0	0	320000	0	0	0	38	320000	6	1	39	44	0	1	1	1	5116	0	16	0	0	106704	0	14	0	320000	100	106728	106732	106708	106708	106830
320204	106709	800	0	0	1	1	0	0	45	0	1	0	1	106692	2	1	1	219	25	320100	100	320000	100	320018	500	4699976	1	106682	0	106731	106707	26678	6	26700	320118	200	320024	200	320024	106707	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320000	0	0	0	0	320000	6	1	39	0	0	1	1	1	5116	0	16	0	0	106704	10	10	7	320000	100	106732	106728	106732	106708	106708
320204	106731	799	0	0	0	0	0	0	56	0	0	0	1	106716	2	1	12	222	25	320100	100	320000	100	320018	500	4674177	1	106702	0	106732	106727	26681	7	26704	320118	200	320024	200	320024	106707	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320038	0	0	0	38	320038	0	1	39	43	0	1	1	1	5116	0	16	0	0	106704	10	0	0	320000	100	106708	106708	106732	107071	106736
320204	106731	799	0	0	0	0	0	0	44	0	1	0	0	106717	2	0	12	217	25	320100	100	320000	100	320017	500	4709717	0	106682	0	106731	106727	26657	6	26679	320117	200	320024	200	320024	106731	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	0	38	320039	6	0	0	0	0	1	1	1	5116	0	16	0	0	106704	0	0	0	320000	100	106732	106708	106728	106728	106728
320204	106727	799	0	0	0	0	0	0	44	0	0	0	1	106692	2	1	0	249	25	320100	100	320000	100	320018	500	4698971	1	106682	0	106727	106727	26657	6	26703	320118	200	320024	200	320024	106730	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320000	0	0	0	38	320000	6	1	0	0	0	0	0	0	5109	1	17	1	1	106724	14	10	7	320000	100	106732	106708	106708	106708	106728
320204	106731	800	0	0	0	0	0	0	44	0	0	0	1	106692	2	12	12	149	25	320100	100	320000	100	320000	500	4699887	0	106706	0	106739	106742	26679	3	26713	320100	200	320000	200	320000	106731	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320040	0	0	0	38	320038	6	1	39	44	0	0	0	0	5109	1	17	1	1	106729	14	14	7	320000	100	106732	106733	106728	106729	106812
320204	106727	800	0	0	1	0	0	0	45	0	1	0	1	106716	2	1	0	79	25	320100	100	320130	100	320000	500	4673851	1	106706	0	106707	106707	26672	3	26689	320100	200	320000	200	320000	106727	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320039	0	0	0	3	320000	6	1	39	0	0	0	0	0	5109	1	17	1	1	106728	14	14	7	320000	100	106786	106725	106741	106708	106728
320204	106707	799	0	0	0	0	0	0	0	0	1	0	1	106692	2	0	1	0	25	320100	100	320000	100	320000	500	4709628	1	106682	0	106731	106731	26675	3	26713	320100	200	320000	200	320000	106731	106727	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	43	0	320038	0	0	0	0	320000	0	1	0	43	0	0	0	0	5109	1	17	1	1	106724	0	14	7	320000	100	106790	106981	106744	106739	106708
320204	106731	799	0	0	0	0	0	0	0	0	0	0	1	106692	2	0	12	16	25	320100	100	320000	100	320000	500	4698880	1	106707	0	106731	106731	26679	3	26713	320100	200	320000	200	320000	106731	106707	1	1	80201	100	99	100	100	80000	80000	0	100	320000	0	0	0	320000	0	0	0	0	320000	6	1	0	44	0	0	0	0	5109	1	17	1	1	106724	14	14	7	320000	100	106728	106728	106708	106728	106708

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	106727	799	0	0	90	1	0	1	106712	2	12	12	16	25	320010	10	320000	10	320000	50	4709628	0	106702	106727	106732	26676	3	26709	320010	20	320000	20	320000	106727	106727	1	1	80021	10	9	10	10	80000	80000	0	10	320130	43	320039	0	42	320039	6	1	39	44	0	5019	4	17	1	1	106724	10	10	4	320000	10	106728	106732	106732	106732	106732
320024	106731	800	0	0	207	0	0	1	106869	2	12	12	16	25	320010	10	320000	10	320000	50	4728183	1	106706	106727	106727	26675	3	26709	320010	20	320000	20	320000	106731	106727	1	1	80021	10	9	10	10	80000	80000	0	10	320000	43	320039	2	42	320039	6	1	39	43	0	5019	1	17	1	1	106728	10	14	4	320000	10	106732	106728	106708	106728	106732
320024	106727	799	0	0	57	1	0	1	106712	2	1	12	18	25	320010	10	320000	10	320000	50	4683099	0	106706	106727	106727	26679	3	26709	320010	20	320000	20	320000	106727	106727	1	1	80021	10	9	10	10	80000	80000	0	10	320000	43	320039	0	39	320039	6	1	39	43	0	5019	2	17	1	1	107026	10	10	4	320000	10	106728	106728	106728	106728	106728
320024	106728	799	0	0	44	0	0	1	106712	2	12	12	16	25	320010	10	320000	10	320000	50	4728183	2	106711	106727	106727	26675	3	26709	320010	20	320000	20	320000	106727	106727	1	1	80021	10	9	10	10	80000	80000	0	10	320000	43	320039	0	39	320039	6	1	39	43	0	5019	1	17	1	1	106724	10	10	4	320000	10	106779	106728	106728	106728	106728
320024	106727	799	0	0	45	0	0	1	106712	2	12	12	16	25	320010	10	320000	10	320000	50	4709628	1	106702	106727	106727	26675	3	26709	320010	20	320000	20	320000	106727	106727	1	1	80021	10	9	10	10	80000	80000	0	10	320000	43	320039	0	39	320039	6	1	39	43	0	5019	2	17	1	1	106724	10	10	4	320000	10	106728	106728	106728	106728	106728
320024	106727	799	0	0	45	0	0	1	106712	2	12	12	16	25	320010	10	320000	10	320000	50	4728183	1	106702	106727	106727	26675	3	26709	320010	20	320000	20	320000	106727	106727	1	1	80021	10	9	10	10	80000	80000	0	10	320000	43	320039	0	39	320039	6	1	39	43	0	5019	1	17	1	2	106724	10	10	4	320000	10	106728	106728	106728	106728	106728
320024	106727	799	0	0	45	1	0	1	106712	2	12	12	18	25	320010	10	320000	10	320000	50	4709628	1	106702	106727	106727	26675	3	26709	320010	20	320000	20	320000	106727	106727	1	1	80021	10	9	10	10	80000	80000	0	10	320000	43	320039	0	39	320039	6	1	39	43	0	5019	1	17	1	1	106724	10	10	4	320000	10	106728	106728	106728	106728	106728
320024	106727	800	0	0	45	0	0	1	106715	2	12	12	16	25	320010	10	320000	10	320000	50	4728183	1	106702	106727	106727	26675	3	26709	320010	20	320000	20	320000	106727	106727	1	1	80021	10	9	10	10	80000	80000	0	10	320000	43	320000	0	39	320039	6	1	39	43	0	5019	1	17	1	1	106724	10	10	4	320000	10	106897	106728	106728	106728	106728
320024	106727	799	0	0	45	0	0	1	106716	2	12	12	16	25	320010	10	320000	10	320000	50	4709628	1	106702	106727	106727	26679	3	26709	320010	20	320000	20	320000	106731	106727	1	1	80021	10	9	10	10	80000	80000	1	10	320000	43	320039	0	39	320039	6	1	39	43	0	5019	2	17	2	2	107003	10	10	4	320000	10	106728	106735	106728	106728	106746
320024	106731	800	1	0	44	1	0	1	106712	2	12	12	16	25	320010	10	320000	10	320000	50	4709628	1	106702	106727	106727	26675	3	26709	320010	20	320000	20	320000	106727	106707	1	1	80021	10	9	10	10	80000	80000	0	10	320000	43	320039	0	39	320039	6	1	39	43	0	5020	1	17	1	1	106907	10	10	4	320000	10	106728	106728	106728	106728	106728

LD1 (multiple, 4 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations