Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 1 reg, 2S)

Test 1: uops

Code:

  ld1 { v0.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f181e223a3f43464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
61005287762233002700004047502827510223474200010001000100010005000500016159502810928732310200010002000284842850211610011000100001000001002007410010230133719464695932509672099432053805146463280461000151571260214158100010002870028597286392856528593
61004287162232512300004047482818610223659200010001000100010015000500016159242819828659310200010002000285392856511610011000100001000041002004100102301347297287006331811642100631953807185761278951000151911261913727100010002857328476284762847028492
6100428625221240280000104871280861102330020001000100010001000500050001015932280342860131020001000200028544284561161001100010000100004100200137100121301340196017006323914592092731973805145856280971000149461259313830100010002860528601285902852628557
6100428475220250190001704918281591102353720001000100010001000500050032615920280582852531020001000200028429285241161001100010000100000100200167100222321341497737020326813692091032293795176167279711000151411262414068100010002846828399285102854728695
6100428449221240270000404958281561022361420001000100010001000500050001215946280562857631020001000200028410284801161001100010000100000100100172100221301317694367020321415652092432783801196365280131000148661259113721100010002850228607285892844028510
6100428530222210290000404877281011002363420001000100010001000500050001215948282312873231020001000200028461284111161001100010001100000100202175100202001331599167031325911652096431803804205960280301000149851264514144100010002860028658286262862528680
61004285002232302110004050612824111223619200010001000100010005000500022159692810928459310200010002000286322845511610011000100001000041001002100121001361897606971320412572091531873802206463280091000151801274013902100010002860028621284232856928695
610042857322425026000010477128237110236432000100010001000100050005000615961282112879831020001000200028625285931161001100010000100000100200101100221001323496416905313110632112131693808206368281231000153441282314257100010002866728656286712865628711
6100428788223260290000404701283701122363420001000100010001000500050001715934282852868631020001000200028604286221161001100010000100000100200169100222001323495116844310214612122531923803226164280971000156001287614327100010002866928671286772872428756
6100428736223210280000104727282721002363720001000100010001000500550442116004283062882531020001001200228764286604161001100010000100124100500610100221321313793166802318114702106832693800186258280531001151791300114254100010002877228799287212886928775

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
5020512013993101010000001120037119753477010350112100011000040100100001000010621084537979458494512002912005012005011334331136996010030452100401000060200200821000012014212004721502011009910040100100001000011001000001100030027601000011003257111213119900500229081000050100120133120401120144120413120233
5020412040093200010232652640012030311967970701465012410005100064038410039101181064098454571345861921200261200501200501133013113699601003020010000100006020020000100001200501200351150202100991004010010000100001100100000010000003100001100321017611119762500029601000050100120053120051120051120052120051
502041200509300001000100012003511975325701035010010000100004010010000100001062108453797945850231200261200501200501133013113695601003020010000100006020020098100001200501200351150201100991004010010000100000100100000110000000100001100321017611119744500029081000050100120036120051120036120051120051
502041200549310001000100012003511975325701005010210001100004010010000100001062108453741245849451200261200501200501133013113698601003020010000100006020020000100001200501200501150201100991004010010000100000100100000110000100100001100321017611119759500029901000050100120051120051120036120051120051
502041200509310001100100012003711975325701035010210001100004010010000100001062108453786545849451200261200361200501133013113695601003020010000100006020020000100001200501200541150201100991004010010000100000100100000110000000100001100321017611119759500026981000050100120051120051120051120051120051
5020412005093000011001300012003211975325701035010210001100004010010000100001062117453741245859581200261200501200501133013113698601003032510000100006020020000100001200501200501150201100991004010010000100000100100000110000100100001100321017611119759500020651000050100120051120051120051120051120051
502041200359310001100100012003511975425701005010010001100004010010000100001062108453797945844731200111200501200351133013113697601003020010000100006020020000100001200501200501150201100991004010010000100000100100000110000000100000100321017611119759500009681000050100120053120048120048120036120051
502041200529310001100100012003511975025701035010210001100004010010000100001062072453797945849451200261200471200501133013113698601003020010000100006020020000100001200531200471150201100991004010010000100000100100000110000006100001100321017611119759500029981000050100120053120051120051120051120052
502041200509300001100100012003511975325701035010210001100004010010000100001062108453741245849451200261200501200501133013113683601003020010000100006020020000100001200501200501150201100991004010010000100000100100000110000103100001100321017611119813500029981000050100120051120051120036120036120052
5020412005093100010001000120020119753257010050102100011000040100100001000010621084537979458494512002612005012005011328631136996010030200100001000060200200001000012005012003511502011009910040100100001000001001000101100000031000111203256310912119914500236681000050100120236120235120315120244120137

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f23243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd0d2d5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
5002512005393100001010100001200331197302570013500121000110000400101008010000106213945388314585907012002601200501200501133243113714602333002010000100006002020000100001200351200471150021109104001010000100000101000001100000020100031010003213002728512423119998500289681000050010120234120242120331120229122214
50024120228932011010321333520011201211208224770027500401000410006402941008010077106632045444134589431012021201203021202141134031211395460901302691012210083607562008010124120229120302315002110910400101000010000110100000110000000310002101000314000208272221119768500029681000050010120052120051120051120051120051
500241200509300000000010000120032119730257001350012100011000040010100001000010621214538831458594601200260120050120050113324311371460010300201000010000600202000010000120050120047115002110910400101000010000010100000110000060010000101000314000208231422119769500029781000050010120051120051120051120051120051
500241200509300000000010000120035119694257001350012100011000040010100001000010621394538831458550711200270120050120047113321311371460010300201000010000600202000010000120047120047115002110910400101000010000010100000110000000010000101000314000218252220119769500029681000050010120048120054120051120055120098
500241200549300000000010000120035119730257001350012100011000040010100001000010621394538831458590701200110120050120050113310311371460010300201000010000600202000010000120047120050115002110910400101000010000010100000110000010010000100000314000218272320119772500029681000050010120051120051120048120051120051
500241200509300000000010000120035119731257001350012100011000040010100001000010621394538831458590701200270120050120050113324311371460010301661000010000600202000010000120050120047115002110910400101000010000010100000110000000010000101000314000218202021119769500026601000050010120051120051120051120052120048
500241200509300000000010000120035119730257001350012100011000040010100001000010621394538831458590701200260120047120047113325311371460010300201000010000600202000010000120050120047115002110910400101000010000010100000110000000010000101000314000188201324119766500029681000050010120051120048120051120051120051
500241200509310000000010000120035119731257001350012100011000040010100001000010621394538717458590701200230120050120050113324311371460010300201000010000600202000010000120050120047115002110910400101000010000010100000110000000010000101000314000218201821119769500029981000050010120048120051120051120051120051
500241200479300000000010000120032119730257001350012100011000040163100001000010621394538831458590701200110120050120050113324311371460010300201000010000600202000010000120050120047115002110910400101000010000010100000110000000010000101000314000238201521119769500029681000050010120051120051120051120051120051
500241200499310000000000010120036119730257001350012100011000040010100001000010621034538831458590701200260120050120050113327311371460010300201000010000600202000010000120050120047115002110910400101000010000010100000110000000010000101000314000228202214119766500029901000050010120140120319120127120230120228

Test 3: throughput

Count: 8

Code:

  ld1 { v0.2s }, [x6], x8
  ld1 { v0.2s }, [x6], x8
  ld1 { v0.2s }, [x6], x8
  ld1 { v0.2s }, [x6], x8
  ld1 { v0.2s }, [x6], x8
  ld1 { v0.2s }, [x6], x8
  ld1 { v0.2s }, [x6], x8
  ld1 { v0.2s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
8020580040643000102512641548100080377166605461602288014980000801008000041796553759853180304803408034369924127028016010020080160200160640800408004011802011009910010080000800000100800220148001300220088005761121700512713312803271800466680000801008064780343806458004180041
80204800406200000021181259800008002516652516010080100800008010080000417968737588230800158004080040699243699971601002008000020016000080040800401180201100991001008000080000010080000014800120160138001361101700511012511800371800009780000801008034380342803448034380041
8020480040620001101285000008002516613251603808015080025801008000041792923758824080015800408004069924369997161666200800002001601608004080340218020110099100100800008000011008006801480013000588001761111701514811711800371800009680000801008268382975826248271782575
8020482467666000005701900000800251605251601008010080000801008000041796873758824180015800408004069924369997160100200800002001600008004080040118020110099100100800008000001008000001480013000138001260111700511011711800370800009980000801008004180041800418004180041
8020480040599000000061000008002510042516010080100800008010080000417968737588240800158004080040700843699971601002008000020016000080040800401180201100991001008000080000010080484014800130324021800106191700511011711800370800009680000801008004180041800418004180041
802048004059900000004000010800251666251601008010080000801008000041796953758824080015800408004069924369997160100200800002001600008004080040118020110099100100800008000001008000001480013000128001361121700511011711800370800009680000801008004180041800418004180041
802048004059900000003400100800251663625160100801008000080100800004179687375882408001580040800406992436999716010020080000200160000800408004011802011009910010080000800000100800000178001200013800126191700511011711800371800000980000801008004180041800418004180041
802048004062000000007800000800251665251601008010080000801008000041796713758824080015800408004069924369997160100200800002001600008004080040118020110099100100800008000001008000001780012000108001261131700511011711800370800009680000801008004180041800418004180041
802048004062000000002800000800251665251601008010080000801008000041796873758824080015800408004069924369997160100200800002001600008004080040118020110099100100800008000001008000001480013000138001361131700511011711800371800009980000801008004180041800418004180041
80204800406200001100390000080025166625160100801008000080100800004179695375882408001580040800406992436999716010020080000200160000800408004011802011009910010080000800000100800000148001301013800126191700511011711800371800000080000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f5051schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
800258004062000000000210000800251666025160010800108000080010800694178613375882200800158004080040699463700201600102080000201600008004080040118002110910108000080000010800000198001400080015611621050203163380037180000131380000800108004180041800418004180041
80024800406200000110015400008002516611025160010800108000080010800004178621375882200800158004080040699463700201600102080000201601608004080040118002110910108000080000010800000218001600198001561142105020316338007618000001080000800108004180041800418004180041
8002480040620000000002100008002516611025160010800108000080010800004178597375882200800158004080040699463700201600102080000201600008004080040118002110910108000080000010800000198001620228001761021050203163380037080000131380000800108004180041800418004180041
8002480040620000000002100008002516670251600108001080000800108000041786133758822008001580040800406994637002016001020800002016000080040800401180021109101080000800000108000001980016001680017611721050202163380037180000131380000800108004180092800418004180041
8002480040620000011002200008002516653025160010800108000080010800004178621375882200800158004080040699463700201600102080000201600008004080040118002110910108000080000010800220198001600168001761170050353163380037180000131080000800108004180041800418004180041
8002480040621000000002300008002516070251600108001080000800108000041786213758823008001580040800406994637005116001020800002016000080040800401180021109101080000800000108000002180039102080037611521050203253280037180000101080000800108004180041800418004180041
800248004062001001000220000800251665025160010800388000080010800004178621375882200800158004080040699463700201600102080000201600008004080040218002110910108000080000010800000198001500148001761152105020316238003718000001080000800108004180041800418004180041
800248004062100001100210100800251667025160010800108000080010800004178621375882200800158004080040699463700201600102080000201600008004080040118002110910108000080000010800000080017001780019611721050203163280037080000131080000800108004180041800418004180041
800248004062100000000270000800251660025160010800108000080010800004178621375882301800158004080040699463700491600102080080201600008004080040118002110910108000080000010800000198001600168001661142105020316338003708000001080000800108004180041800418004180041
8002480040620000000002300008002516670251600108001080025800108000041785973758822008001580040800406994637002016001020800002016000080040800402180021109101080000800000108000002180000001780017611521050203163380037080000101480000800108004180041800418004180041