Firestorm: LD1 (multiple, post-index, 2 regs, 1D) measurements

Code:

  ld1 { v0.1d, v1.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
62005	29727	240	16	1	0	19	1	0	0	5	1	136	264	0	0	0	4681	29222	0	1	1	24513	2000	1001	1004	1001	1000	5000	5000	6	16061	28814	29578	3	10	2000	2000	3000	29539	29632	2	1	61001	1000	1000	0	1002	2	2	1002	0	2	1095	1001	2	1	3	2	0	13047	9233	6867	3120	7	51	21007	3377	3811	19	35	45	2	28868	1002	16328	13911	15431	1000	1000	1000	29719	29629	29588	29616	29641
62004	29543	238	11	1	0	19	1	0	0	0	0	5	0	0	0	0	4672	29144	0	1	0	24865	2000	1000	1000	1000	1000	5000	5001	5	16029	28930	29796	3	10	2000	2000	3000	29489	29308	1	1	61001	1000	1000	4	1000	0	3	1002	0	0	4	1003	2	1	3	0	0	13262	9612	7005	3168	4	46	20718	3318	3811	10	48	41	2	28472	1000	16303	13820	15075	1000	1000	1000	29458	29465	29481	29516	29337
62004	29349	236	18	0	1	14	0	0	0	0	0	3	0	0	0	0	4613	29007	0	0	1	24457	2000	1000	1000	1000	1000	5000	5001	4	16062	28838	29393	3	10	2000	2000	3000	29199	29192	1	1	61001	1000	1000	1	1000	0	3	1001	2	0	0	1001	2	0	2	0	1761	13151	9493	6898	3097	8	37	20705	3209	3810	15	39	42	2	28577	1000	17769	15467	16887	1000	1000	1000	30992	30874	31556	31238	29446
62004	29568	237	20	0	0	15	0	0	0	0	0	223	108	0	0	0	4742	28907	0	0	1	24342	2000	1000	1000	1000	1000	5000	5000	6	16060	28757	29578	3	10	2000	2000	3000	29218	29255	1	1	61001	1000	1000	4	1000	0	3	1001	1	0	1	1001	2	1	3	2	15	13192	9476	6911	3107	8	43	20783	3261	3813	10	39	40	2	28734	1000	16231	13710	15179	1000	1000	1000	29447	29542	29473	29531	29515
62004	29418	235	15	0	0	12	0	0	0	0	0	147	0	0	0	0	4736	29009	0	1	0	24609	2000	1000	1000	1000	1000	5000	5000	0	16052	28854	29536	3	10	2000	2002	3000	29293	29403	2	1	61001	1000	1000	4	1000	0	3	1000	0	0	0	1000	2	0	3	0	0	13267	9350	6914	3162	7	53	21141	3298	3812	14	42	48	4	28766	1000	16265	13629	15252	1000	1000	1000	29499	29376	29405	29411	29452
62004	29390	237	15	0	0	17	0	0	0	0	0	2	0	0	0	0	4770	28998	0	1	0	24384	2000	1000	1000	1000	1000	5000	5000	4	16032	28694	29445	58	268	2010	2014	3012	29850	29733	15	1	61001	1000	1000	4	1006	9	2	1012	1	0	8884	1008	2	1	3	0	0	13035	9008	6852	3051	7	40	21227	3237	3817	69	44	46	2	70148	1000	16039	13115	14302	1000	1000	1000	29250	29342	29136	29285	29395
62004	29200	241	18	0	0	21	0	0	0	0	0	4	0	0	0	0	4797	28457	0	0	0	23692	2000	1000	1000	1000	1000	5000	5000	7	16101	28213	28664	3	10	2000	2000	3000	28529	28575	1	1	61001	1000	1000	0	1000	2	0	1000	0	0	0	1000	2	0	2	0	0	13261	9389	6968	3169	7	45	20060	3312	3814	15	41	44	2	28167	1000	15517	12986	14586	1000	1000	1000	28709	28801	28721	28806	28763
62004	28745	222	16	0	0	20	0	0	0	0	0	2	0	0	1	0	4670	28338	0	0	0	23780	2000	1000	1000	1000	1000	5000	5000	16	16023	28216	28804	3	10	2000	2000	3000	28664	28490	1	1	61001	1000	1000	0	1000	0	2	1001	0	0	0	1000	0	0	2	0	0	13095	9518	6945	3155	10	43	20167	3150	3816	9	42	42	2	28193	1000	15570	12992	14268	1000	1000	1000	28678	28721	28707	28662	28597
62004	28692	223	19	0	0	14	0	0	0	0	0	2	0	0	0	0	4869	28318	0	0	0	23727	2000	1000	1000	1000	1000	5000	5001	1	16086	28301	28713	3	10	2000	2000	3000	28578	28637	1	1	61001	1000	1000	0	1004	0	3	1000	0	2	1	1000	0	0	0	0	0	13320	9414	6898	3123	13	48	20018	3173	3809	18	49	45	2	28087	1000	15447	12934	14071	1000	1000	1000	28785	28610	28732	28631	28531
62004	28768	222	17	0	0	17	0	0	0	1	0	0	0	0	0	0	4701	28409	0	0	1	23696	2000	1000	1000	1000	1001	5000	5000	10	16038	28269	28760	3	10	2000	2000	3000	28699	28671	1	1	61001	1000	1000	1	1000	0	3	1000	0	0	0	1000	2	0	2	0	0	12904	9434	6950	3088	9	43	20006	3162	3815	15	48	48	2	28096	1000	15706	12956	14317	1000	1000	1000	28786	28677	28736	28847	28777

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d, v1.1d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120053	899	1	1	0	1	0	0	0	1	0	0	0	0	0	120042	119639	25	70106	50104	10002	10000	40100	10000	10000	1061795	4546159	4574738	0	120032	120056	120041	112042	3	112447	60100	30200	20000	10000	60200	30000	10000	120056	120043	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	1	10000	1	1	1	1	0	0	3210	1	83	1	1	119759	50004	0	0	9	10000	10000	50100	120060	120057	120058	120057	120187
60204	120092	931	1	0	1	0	0	0	0	7	0	1	0	0	0	120041	119639	25	70106	50104	10002	10000	40100	10000	10000	1061795	4544633	4574699	0	120034	120059	120056	112042	3	112447	60100	30200	20000	10000	60200	30000	10000	120059	120056	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	1	4	10000	1	1	1	1	0	0	3210	1	83	1	1	119759	50004	9	6	0	10000	10000	50100	120057	120057	120057	120057	120057
60204	120056	931	1	0	1	0	0	0	0	2	0	0	0	0	0	120041	119717	25	70106	50104	10002	10000	40100	10000	10000	1062257	4546159	4574699	0	120017	120056	120056	112042	3	112432	60100	30200	20000	10000	60200	30000	10000	120056	120056	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	3	1	10002	0	2	4	10000	1	1	0	1	0	0	3210	1	83	1	1	120133	50004	9	9	0	10000	10000	50100	120057	120059	120057	120057	120057
60204	120057	931	1	1	0	0	0	0	0	2	0	0	0	0	0	120043	119642	25	70106	50104	10002	10000	40100	10000	10000	1062212	4564997	4607393	0	120017	120044	120246	112174	3	112447	60100	30200	20000	10000	60200	30000	10040	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	1	1	2859	10000	1	1	1	1	1	0	3210	1	83	1	1	119752	50002	9	0	8	10000	10000	50100	120044	120057	120150	120057	120058
60204	120041	931	1	0	0	0	0	0	1	2	0	0	0	0	0	120041	119639	25	70106	50104	10002	10000	40100	10000	10000	1062248	4544474	4573390	0	120032	120090	120056	112046	3	112447	60100	30200	20000	10040	60200	30000	10000	120057	120056	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	0	1	10000	1	1	0	1	0	0	3210	1	83	1	1	119759	50004	9	0	8	10000	10000	50100	120054	120042	120057	120054	120057
60204	120041	931	1	0	0	0	1	0	0	11	0	0	0	0	0	120042	119641	25	70103	50104	10002	10000	40100	10039	10000	1062239	4546159	4574699	0	120034	120056	120057	112046	3	112447	60100	30200	20000	10000	60200	30000	10000	120056	120056	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	1	0	7	10000	1	1	0	1	1	0	3210	1	83	1	1	119759	50004	9	6	0	10000	10000	50100	120057	120057	120057	120057	120057
60204	120056	930	1	0	0	0	0	0	0	2	0	0	0	0	0	120041	119639	49	70106	50104	10002	10000	40100	10000	10000	1062239	4546159	4574699	0	120032	120057	120041	112046	3	112448	60100	30200	20000	10000	60200	30000	10000	120149	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	3	1	10001	0	1	4	10000	1	1	1	1	0	0	3210	1	83	1	1	119759	50002	9	6	0	10000	10000	50100	120057	120057	120151	120042	120057
60204	120056	931	1	2	0	0	0	0	0	2	0	0	0	0	0	120041	119689	25	70106	50104	10002	10000	40100	10000	10000	1062239	4546159	4574699	0	120032	120056	120056	112046	3	112447	60100	30200	20000	10000	60200	30123	10000	120056	120041	1	1	50201	100	99	100	40100	10000	10000	0	100	10005	1	1	10001	1	1	1	10000	1	1	1	1	0	0	3210	1	83	1	1	119759	50004	0	9	5	10000	10000	50100	120042	120057	120057	120057	120057
60204	120059	930	1	1	1	0	0	0	0	2	0	0	0	0	0	120041	119639	25	70106	50104	10002	10000	40100	10000	10039	1061795	4544513	4573390	0	120032	120041	120056	112046	3	112447	60100	30200	20000	10000	60200	30000	10000	120053	120056	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	1	1	10000	1	1	0	1	0	0	3210	1	83	1	1	119761	50002	9	11	8	10000	10000	50100	120057	120057	120057	120057	120057
60204	120053	931	1	1	0	0	0	0	0	146	0	0	0	0	0	120026	119717	25	70106	50104	10002	10000	40100	10000	10000	1062239	4546159	4574816	0	120029	120056	120056	112046	3	112432	60100	30200	20000	10000	60448	30000	10000	120056	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	0	1	10000	1	1	1	1	4	0	3210	1	83	1	1	119752	50004	0	6	8	10000	10000	50100	120054	120057	120042	120042	120057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120057	930	0	1	1	0	0	0	0	0	0	19	0	0	0	120045	119714	25	70016	50012	10002	10000	40010	10000	10000	1062300	4551026	4582205	0	120037	120060	120060	112079	3	112478	60010	30020	20000	10042	60020	30000	10000	120060	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	1	1	10002	0	0	0	1	10000	1	1	1	1	1	0	3140	24	78	15	18	119772	50004	13	10	0	10000	10000	50010	120044	120061	120061	120061	120061
60024	120061	930	0	1	0	0	0	0	3	0	0	19	0	0	0	120045	119714	25	70013	50014	10002	10000	40010	10000	10038	1062840	4550242	4578252	0	120106	120060	120060	112082	3	112478	60010	30020	20000	10000	60020	30000	10000	120041	120057	1	1	50021	10	9	0	10	40010	10000	10000	1	10	10001	1	1	10003	0	2	0	1	10000	0	1	1	1	1	0	3140	18	78	8	23	119769	50004	10	10	12	10000	10000	50010	120061	120061	120065	120061	120058
60024	120060	930	0	1	1	0	0	0	0	0	0	1	0	0	0	120045	119714	25	70027	50014	10002	10000	40010	10000	10000	1062291	4551105	4578313	0	120036	120057	120057	112086	3	112475	60010	30020	20000	10000	60020	30000	10000	120060	120148	1	1	50021	10	9	1	10	40010	10000	10000	0	10	10003	1	1	10001	0	3	1	1	10000	1	1	1	1	1	0	3140	22	78	21	23	119769	50004	13	13	12	10000	10000	50010	120058	120158	120061	120061	120042
60024	120060	930	0	1	0	1	1	0	0	1	0	7	0	0	1	120042	119714	25	70016	50014	10002	10000	40010	10000	10000	1062291	4552940	4578329	0	120036	120060	120060	112082	3	112478	60010	30020	20098	10000	60020	30000	10000	120063	120041	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	1	1	10001	0	1	1	4	10000	1	1	1	1	0	0	3140	21	78	22	22	119769	50004	13	10	12	10000	10000	50010	120061	120061	120058	120061	120063
60024	120057	931	0	1	1	1	1	0	0	0	0	7	0	0	0	120047	119714	25	70016	50012	10002	10000	40152	10000	10000	1062408	4551450	4579954	0	120036	120060	120041	112082	3	112538	60010	30020	20000	10000	60020	30000	10000	120058	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	3	1	10003	0	0	0	4	10000	1	1	1	1	0	0	3140	20	78	24	23	119750	50004	13	10	12	10000	10000	50010	120061	120061	120061	120042	120061
60024	120057	930	0	1	1	1	1	0	0	0	0	2	0	0	0	120045	119711	25	70013	50014	10001	10000	40010	10000	10000	1062535	4549229	4578213	0	120036	120057	120060	112079	3	112478	60010	30020	20000	10000	60260	30000	10000	120041	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	1	1	10001	0	2	1	10	10000	1	1	1	1	0	0	3140	21	78	18	22	119750	50004	10	10	12	10000	10000	50010	120061	120063	120061	120061	120042
60024	120041	930	1	1	1	0	0	0	0	0	0	2	0	0	1	120045	119711	25	70016	50012	10002	10000	40152	10000	10045	1062291	4551453	4579546	0	120033	120061	120060	112082	3	112530	60010	30020	20000	10000	60020	30000	10000	120062	120061	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10001	2	1	10001	0	2	0	4	10000	0	1	1	1	0	0	3140	7	77	21	8	119750	50004	11	10	12	10000	10000	50010	120042	120062	120061	120042	120061
60024	120060	930	0	1	1	0	0	0	0	0	0	2	0	0	0	120045	119699	25	70016	50014	10002	10000	40010	10000	10000	1062525	4550893	4578351	0	120036	120057	120149	112082	3	112475	60010	30020	20000	10041	60020	30000	10000	120061	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10005	1	1	10001	0	1	0	1	10000	1	1	1	1	0	0	3140	24	78	23	23	119766	50002	10	10	12	10000	10000	50010	120061	120058	120058	120061	120061
60024	120060	931	0	1	1	0	0	0	0	0	0	26	0	0	0	120233	119833	75	70044	50014	10004	10004	40010	10040	10039	1064482	4554119	4580627	0	120110	120153	120244	112152	13	113532	65238	30384	20080	10123	60262	30486	10040	120330	120227	4	1	50021	10	9	0	10	40010	10000	10000	0	10	10003	1	0	10005	2	0	0	5561	10003	1	1	0	1	0	0	3187	23	100	10	28	119917	50024	13	13	12	10000	10000	50010	120157	120438	120247	120340	120244
60024	120240	932	0	1	0	0	2	0	0	3	0	14	0	0	1	120046	119715	25	70016	50014	10002	10000	40010	10000	10000	1062759	4550093	4578312	0	120017	120041	120060	112082	3	112478	60010	30020	20000	10000	60020	30000	10000	120060	120057	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10001	2	1	10002	0	1	0	4	10000	0	1	1	1	0	0	3140	16	78	22	21	119769	50004	13	10	12	10000	10000	50010	120061	120061	120061	120058	120061

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d, v1.1d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120051	930	0	0	0	0	0	0	0	133	0	0	0	0	120035	119633	25	70103	50114	10001	10000	40100	10000	10000	1062185	4545931	4573044	120026	120036	120050	112040	13	112441	60100	30200	20000	10000	60200	30000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	36	10000	1	0	0	0	3210	1	83	1	1	119750	50000	9	6	8	10000	10000	50100	120051	120051	120051	120051	120051
60204	120035	930	0	0	0	0	0	0	0	1	88	0	0	0	120131	119633	50	70103	50102	10001	10000	40100	10000	10000	1062185	4546045	4573044	120026	120036	120050	112040	3	112441	60100	30200	20000	10000	60200	30000	10000	120135	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	3210	1	83	1	1	119753	50002	9	6	8	10000	10000	50100	120051	120052	120051	120140	120049
60204	120050	931	0	0	1	0	0	0	0	1	0	0	0	0	120035	119634	25	70117	50100	10001	10000	40100	10000	10000	1062168	4546165	4574465	120026	120050	120050	112026	3	112441	60100	30200	20000	10000	60200	30000	10000	120035	120050	2	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10003	0	0	0	0	10000	1	0	0	0	3210	1	96	1	1	119750	50010	0	0	0	10000	10000	50100	120048	120048	120051	120051	120051
60204	120050	931	0	0	0	0	0	0	0	13	0	0	0	0	120020	119633	25	70103	50102	10001	10000	40100	10000	10000	1062185	4545931	4574465	120026	120050	120050	112077	3	112441	60100	30200	20000	10000	60200	30000	10042	120035	120050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	0	10000	1	1	0	0	3210	1	83	1	1	119753	50002	9	9	8	10000	10000	50100	120141	120051	120051	120051	120051
60204	120050	930	0	0	0	0	0	0	0	13	0	0	0	0	120036	119633	25	70103	50102	10001	10000	40100	10000	10000	1062185	4546820	4574504	120027	120050	120088	112044	3	112441	60100	30200	20000	10000	60200	30000	10000	120035	120050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	1	0	2795	10000	1	1	0	0	3210	1	83	1	1	119753	50002	9	6	0	10000	10000	50100	120051	120051	120051	120051	120051
60204	120035	930	0	1	0	0	0	0	0	12	0	0	0	0	120035	119712	25	70103	50102	10001	10002	40100	10000	10000	1062185	4545931	4574465	120026	120050	120047	112037	3	112502	60100	30200	20000	10000	60200	30000	10000	120050	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	0	10000	1	1	0	0	3210	1	83	1	1	119753	50002	9	0	0	10000	10000	50100	120054	120051	120051	120051	120051
60204	120050	930	0	0	0	1	1	0	0	133	0	0	0	0	120129	119789	76	70131	50122	10005	10006	40528	10079	10078	1068682	4547107	4581785	120178	120232	120331	112187	13	112541	60762	30321	20240	10081	60944	30363	10082	121895	122313	26	1	50201	100	99	100	40100	10000	10000	0	100	10003	0	1	10003	0	0	0	5505	10002	1	1	0	0	3746	1	86	2	2	119829	50032	9	9	8	10000	10000	50100	120225	120214	120330	120241	120139
60204	120139	932	1	0	0	0	1	2	2	397	176	0	0	0	120035	119633	25	70103	50102	10001	10000	40100	10000	10000	1062185	4545931	4574465	120026	120050	120035	112040	3	112442	60100	30200	20000	10000	60200	30000	10000	120051	120050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	1	0	0	10000	1	1	0	0	3210	1	83	1	1	119750	50002	9	6	8	10000	10000	50100	120055	120052	120051	120051	120051
60204	120050	930	0	0	0	0	1	0	0	6	0	0	0	0	120036	119715	25	70103	50100	10001	10000	40100	10000	10000	1062185	4545931	4573082	120026	120050	120050	112026	3	112441	60100	30200	20000	10000	60200	30000	10000	120050	120050	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	3	10000	1	0	0	0	3210	1	83	1	1	119753	50002	0	6	8	10000	10000	50100	120051	120051	120051	120051	120051
60204	120047	930	0	0	0	0	0	0	0	1	0	0	0	0	120035	119633	25	70100	50100	10000	10000	40100	10000	10000	1062185	4544293	4574582	120011	120050	120035	112040	3	112441	60100	30200	20000	10000	60200	30000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	3	10000	1	1	0	0	3210	1	83	1	1	119753	50002	10	8	8	10000	10000	50100	120048	120048	120051	120051	120048

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120035	964	0	1	1	0	0	0	0	70	0	0	0	0	0	120035	119702	25	70013	50012	10001	10000	40010	10000	10000	1062228	4548462	4577823	1	120026	120047	120050	112058	3	112465	60010	30020	20000	10000	60020	30000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	3	78	5	2	119759	50002	9	6	8	10000	10000	50010	120052	120048	120051	120054	120053
60024	120050	964	0	0	0	0	0	0	0	97	0	0	0	0	0	120032	119705	25	70013	50012	10001	10000	40010	10000	10000	1062264	4548576	4577823	0	120023	120050	120052	112072	3	112468	60010	30020	20000	10000	60020	30000	10000	120050	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	6	78	4	4	119759	50002	9	6	8	10000	10000	50010	120051	120051	120052	120051	120051
60024	120050	965	0	0	0	0	0	0	0	19	0	0	0	0	0	120127	119705	51	70013	50020	10001	10002	40152	10000	10000	1064480	4548538	4577823	0	120850	120329	120230	112169	35	112547	60231	30144	20080	10123	60268	30240	10082	120239	120227	8	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10005	0	0	2	69853	10004	1	1	0	3186	0	4	101	5	5	119908	50022	9	10	8	10000	10000	50010	122182	122453	122448	122330	120150
60024	120234	967	1	1	1	0	0	2	1	310	176	0	0	0	0	120216	119749	25	70013	50022	10001	10002	40010	10000	10039	1062228	4548576	4580503	0	120011	120139	120050	112104	14	112466	60232	30020	20080	10000	60020	30120	10000	120048	120140	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	5	78	4	4	119825	50002	9	0	8	10000	10000	50010	120147	120051	120051	120127	120142
60024	120050	965	0	0	0	0	0	0	1	241	0	1	0	0	0	120032	119704	25	70013	50012	10001	10000	40010	10000	10000	1062228	4547992	4577862	0	120026	120051	120054	112072	3	112468	60010	30020	20000	10000	60020	30000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	4	78	3	5	119760	50002	9	6	8	10000	10000	50010	120051	120051	120051	120051	120052
60024	120050	964	0	0	0	0	0	0	0	1	0	0	0	0	0	120035	119704	25	70013	50012	10001	10000	40010	10000	10000	1062228	4548576	4577823	0	120011	120050	120050	112072	3	112466	60010	30020	20000	10000	60020	30000	10000	120050	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	9	10002	1	1	0	3187	110	5	78	4	15	119765	50002	13	10	9	10000	10000	50010	120055	120058	120057	120056	120058
60024	120056	964	0	0	0	0	0	0	0	64	0	0	0	0	0	123177	120567	25	70013	50012	10063	10082	46267	10120	10000	1062264	4548767	4615847	0	122200	120055	120092	112077	65	112472	60010	34425	22174	10000	60020	30000	10000	120058	122630	36	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	81343	10032	1	1	0	3140	0	3	78	5	3	119763	50002	13	10	9	10000	10000	50010	120055	120055	120057	120055	120053
60024	120057	964	0	0	0	0	0	0	0	4	0	0	0	0	0	120037	121049	50	70013	50012	10001	10000	40010	10000	10000	1062273	4548845	4578017	0	120030	120143	120055	112079	14	112472	60010	30020	20080	10000	60020	30000	10000	120054	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	10015	0	1	10001	0	2	0	2808	10000	1	1	0	3140	0	4	78	3	4	119763	50002	13	10	9	10000	10000	50010	120141	120143	120055	120059	120055
60024	120053	964	0	0	1	0	0	0	1	13	88	0	0	0	0	120039	119690	25	70013	50012	10003	10002	40010	10000	10000	1064359	4550693	4578018	0	120031	120056	120051	112076	3	112471	60231	30143	20000	10000	60020	30120	10000	120037	120035	2	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	2773	10000	1	1	0	3140	0	4	86	2	4	119763	50002	13	11	12	10000	10000	50010	120060	120142	120055	120057	120061
60024	120055	965	0	0	0	0	0	1	0	25	88	0	0	0	0	120039	119705	25	70025	50022	10001	10000	40010	10000	10039	1064318	4548728	4578096	0	122369	120052	120054	112077	3	112477	60232	30020	20000	10000	60266	30120	10000	120054	120147	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	2773	10000	1	1	0	3140	0	8	85	4	2	119826	50012	13	10	13	10000	10000	50010	120058	120055	120151	120056	120058

Test 4: throughput

Count: 8

Code:

  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	43	46	49	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80040	620	0	0	0	1	0	0	0	19	0	0	0	80025	0	6	6	8	0	25	160100	80100	80000	80100	80000	4358986	3758824	1	80015	0	80040	80040	59924	3	59998	160100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80013	0	0	744	80013	6	0	9	0	0	5110	1	16	1	1	80037	1	80000	9	6	80000	80000	80100	80041	80041	80041	80095	80041
160204	80040	621	0	0	0	1	1	0	0	30	0	0	0	80025	1	6	6	6	0	25	160100	80100	80000	80100	80000	4358994	3758824	1	80015	0	80040	80040	59924	11	59998	160100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80035	0	0	2035	80000	0	0	10	17	0	5110	1	16	1	1	80037	0	80000	9	9	80000	80000	80100	80041	80096	80041	80041	80041
160204	80040	620	0	0	0	1	1	0	0	19	0	0	0	80025	1	6	6	5	0	25	160100	80100	80000	80100	80000	4359002	3758824	1	80015	0	80040	80040	59924	3	59998	160100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80013	0	0	13	80010	6	0	10	17	0	5110	2	16	1	1	80037	0	80000	0	6	80000	80000	80100	80041	80041	80041	80041	80041
160204	80040	621	0	0	0	0	0	0	0	19	88	0	0	80025	1	0	6	49	0	25	160100	80100	80000	80100	80000	4359006	3758824	1	80015	0	80040	80040	59924	3	59998	160100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80013	0	0	0	80013	6	0	0	17	0	5110	1	16	1	1	80037	1	80000	9	9	80000	80000	80100	80041	80041	80041	80041	80041
160204	80040	621	0	0	0	0	0	1	0	18	0	0	0	80025	0	6	0	5	0	25	160100	80100	80000	80100	80000	4359006	3758824	1	80015	0	80040	80040	59924	3	59998	160100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80013	0	0	13	80013	6	1	0	17	0	5110	1	25	1	1	80037	1	80000	9	9	80000	80000	80100	80041	80041	80041	80041	80041
160204	80040	620	0	0	0	1	0	0	0	18	88	0	0	80025	1	6	6	57	0	25	160100	80100	80000	80100	80000	4358998	3758824	1	80015	0	80040	80040	59924	3	59998	160100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	14	80000	0	0	12	80017	6	1	13	17	0	5110	1	16	1	1	80037	1	80000	9	9	80000	80000	80100	80041	80041	80041	80041	80041
160204	80040	620	0	0	0	1	1	0	0	19	0	0	0	80025	1	6	0	4	0	25	160100	80100	80000	80100	80000	4359018	3758824	1	80015	0	80040	80040	59924	11	59998	160100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	17	80024	1	0	18	80012	0	1	15	17	0	5110	1	16	1	1	80037	1	80000	9	6	80000	80000	80100	80041	80041	80041	80041	80041
160204	80040	621	0	0	0	1	1	0	0	19	0	0	0	80025	1	0	6	10	0	25	160100	80100	80025	80100	80000	4359014	3758824	1	80015	0	80040	80040	59924	3	59998	160100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	80022	0	0	80022	0	0	1494	80035	6	1	10	17	0	5124	1	34	1	1	80117	0	80027	9	0	80000	80000	80100	80149	80095	80150	80151	80203
160204	80096	627	1	1	1	1	1	2	2	396	88	0	0	80132	1	6	6	94	0	99	160152	80127	80050	80252	80138	4358650	3758824	1	80054	0	80094	80040	60032	128	60395	162714	200	160152	200	240456	80094	80149	3	1	80201	100	99	100	100	80000	80000	0	100	80022	2	0	80022	0	0	1515	80034	0	0	10	17	0	5125	1	25	1	1	80077	0	80055	9	6	80000	80000	80100	80041	80041	80041	80041	80041
160204	80040	620	0	0	1	1	1	0	0	19	0	0	0	80025	1	6	6	6	0	25	160100	80100	80000	80100	80000	4359002	3758824	1	80015	0	80040	80040	59924	3	59998	160100	200	160000	200	240000	80101	80040	1	1	80201	100	99	100	100	80000	80000	1	100	80000	0	14	80013	0	0	51	80015	6	1	13	0	0	5110	1	16	1	1	80037	0	80000	0	6	80000	80000	80100	80041	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	inst barrier (9c)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80148	643	1	1	0	0	0	0	0	19	0	1	0	80025	1	6	6	4	25	160010	80010	80000	80010	80000	4358417	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	1	10	80000	0	14	80010	0	0	13	80009	6	1	0	17	0	1	5020	0	3	16	4	6	4	80037	0	80000	9	6	80000	80000	80010	80041	80041	80041	80041	80041
160024	80110	644	0	0	0	0	0	0	0	40	0	1	0	80025	1	6	6	4	25	160010	80010	80000	80010	80000	4358417	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	14	80013	0	0	10	80009	6	1	10	17	0	0	5020	0	3	16	0	3	3	80037	1	80000	9	6	80000	80000	80010	80041	80041	80041	80041	80041
160024	80040	643	0	0	0	1	0	0	0	18	0	0	0	80025	1	6	6	5	25	160010	80010	80000	80010	80000	4358417	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	14	80010	0	0	9	80010	6	1	9	0	0	0	5020	0	3	16	0	3	3	80037	0	80000	9	6	80000	80000	80010	80041	80041	80041	80041	80041
160024	80040	643	0	0	0	0	0	0	0	0	0	0	0	80025	1	6	6	9	25	160010	80010	80000	80010	80000	4358417	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	14	80013	0	0	10	80000	6	1	15	17	0	0	5020	0	2	16	0	4	3	80037	1	80000	9	6	80000	80000	80010	80041	80041	80041	80041	80041
160024	80040	642	0	0	0	0	0	0	0	18	0	1	0	80025	1	6	6	0	25	160010	80010	80000	80010	80000	4358425	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	14	80000	1	0	10	80009	6	1	0	17	0	0	5020	0	3	16	0	4	2	80037	1	80000	8	7	80000	80000	80010	80041	80041	80041	80041	80041
160024	80040	643	0	0	0	0	0	0	0	19	0	0	0	80025	0	6	6	4	25	160010	80010	80000	80010	80000	4358417	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	14	80009	0	0	14	80010	6	1	10	14	0	0	5020	0	2	16	0	5	4	80037	1	80000	9	6	80000	80000	80010	80041	80041	80041	80041	80041
160024	80040	642	0	0	0	0	0	0	0	12	0	0	0	80025	1	6	6	5	25	160010	80010	80000	80010	80000	4358389	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	14	80013	0	0	0	80010	6	1	10	17	0	0	5020	0	2	16	0	3	3	80037	1	80000	9	9	80000	80000	80010	80041	80041	80041	80041	80041
160024	80040	643	0	0	0	0	0	0	0	0	0	1	0	80025	1	6	6	5	25	160010	80010	80000	80010	80000	4358409	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	14	80000	0	0	9	80012	6	1	10	17	0	0	5020	0	3	16	1	4	3	80037	0	80000	0	0	80000	80000	80010	80041	80041	80041	80041	80041
160024	80040	643	0	0	0	0	0	0	0	0	0	0	0	80025	0	6	6	10	25	160010	80010	80000	80010	80000	4358417	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	0	80010	0	0	12	80010	6	0	13	14	0	0	5020	0	8	16	0	3	3	80037	1	80000	6	6	80000	80000	80010	80041	80041	80041	80041	80041
160024	80040	643	0	0	0	0	0	0	0	15	0	0	0	80025	1	0	6	8	25	160010	80010	80000	80010	80000	4358409	3758824	80015	80040	80040	59946	3	60020	160010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	0	10	80000	80000	0	0	10	80000	0	14	80013	0	0	9	80010	6	1	13	0	0	0	5020	0	3	16	0	4	2	80037	1	80000	6	7	80000	80000	80010	80041	80041	80041	80041	80041

LD1 (multiple, post-index, 2 regs, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations