Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 2 regs, 2D)

Test 1: uops

Code:

  ld1 { v0.2d, v1.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22243a3f464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
620052929922720103010006000471228814002412530001000200010002000500010000013161062863529251310300020003000290932909311610011000100002000002000000020006020000130189430694631571332062331323809144137284411000161581355314892200010002923229148293462923129196
62004294222300000001000601047312882702242503000100020001000200050001000005160722868429205310300020003000291922916111610011000100002000002000010320006006000130429473697831190352052933033808123634284961000159611340715013200010002936129249293302925529195
6200429176235100000000060004748288380024084300010002000100020005000100000016068287102925431030002000300029119291001161001100010000200006200000002000600400012916930269123226038206363227381584041283771000163291340615044200010002911029236293432924529155
62004291612271000101000120004588287820024232300010002000100020005000100000416063286282928131030002000300029216291451161001100010000200004200000052000600600013189931969743139137205983164381853638285101000163511333415156200010002933529185292702928329346
6200429108227100000110050004697288970024155300010002000100020005000100000316070287282926231030002000300029117292051161001100010000200000200200002000402600013251938768673127235207023186381323739284821000163451368314847200010002937029216292632933929303
6200429349227000000101160004704287870024109300010002000100020005000100000116066286822921331030002000300029125291041161001100010000200236200500222002002421013129932569223098140207433176381773736283611000161511369814826200010002921929296292482930229359
620042929822711010001001400004692288882024140300010002000100020005000100000616051287182931831030002000300029162291381161001100010000200330200400152002402600013186936569723202037206573243381683730284631000163601373614935200010002935429235292512928129385
6200429255227100000110000004549288760024215300010002000100020005000100000016064285612929531030002000300029104291741161001100010000200004200000002000000400013105916468943186132205763146381573736284201000158291366214845200010002923129222292192924929171
620042913322720000011001500047682888200241333000100020001000200050001000004160462871329324310300020003000291512924611610011000100002000002000000020006006000130869303688332411332065131953817124039285361000164231374714809200010002926529310292692928529339
62004292652272000001000601046112891300242103000100020001000200050001000002160532863529243310300020003000292182910111610011000100002000002000000020000004000132099489701431780382062731513811103641284311000159491347714888200010002928829317293042929229289

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d, v1.2d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f233a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
602051200479300010100030001120036988061097402580103501021000120000401001000020000138560925735356346556612003012004712005111217131125097010030200200001000060200300001000012005112005011502011009910040100100001000001002000002200000000200000020003210216111198205000210692000050100120052120052120052120052120052
602041200479300100000011000120037986811097402580103501021000120000401001000020000138564565733002347026412002712005112014611214231124937010030200200001003260200300001000012005112005811502011009910040100100001000001002000002200000000200002020003210116111198285000210602000050100120052120052120052120052120052
60204120051930000000001400012003698759109742258010350100100002000040219100002000013858453573348434655101200271200351200481121393112509703053020020000100006020030000100001200351200471150201100991004010010000100000100200000220000010320000202000321011611119826500020602000050100120052120053120052120036120145
602041200519300000000012001120036989051097364780103501021000120000401001000020000138562785734156346553912002912005112005111214231125097010030200200001000060200300001000012014612004711502011009910040100100001000001002000002200000000200002020003210116111198245000210092000050100120048120048120053120053120052
60204120052931000000002001120036987661097402580103501021000120000401001000020000138574795734444346559712002312005112003511212331125097010030200200001000060394300001000012004712004711502011009910040100100001000001002000202200000000200002020203210116111198245000211092000050100120052120052120052120052120052
60204120051930000000002001120036987631097402580103501021000020000401001000020000138499955738786346641812002312004712004711213931125097010030200200621000060200300001000012003512005211502011009910040100100001000001002000002200000003200000020003210116111199065000210092000050100120053120057120052120048120055
602041200479310000000020011200369876310974025801035010210001200004010010000200001384999557396983472363120011120136120051112139311250970100302002000010032602003000010000120051120051115020110099100401001000010000010020000022000000002000020200032101241111982450002101092000050100120036120048120036120036120053
60204120035930000000002880112002198763109740258010350113100012000040100100002000013850459573525834661121200271200471200531121393112493703043020020000100006020030000100001200511200471150201100991004010010000100000100200000220000010020000202007321011611119824500020602000050100120052120040120056120052120048
602041200519310001003213426401120127984741098392628055550413100722005240343100312020213856021574159234702761202551204121201431122212911254370504304852006210063603943028210063120405120122315020110099100401001000010000010020054222000200044552000620200032311321211997850023101092000050100120052120054120052120048120048
6020412003593000000000200012003698763109741258010350102100012000040100100002000013858304573429834655391200231200511200511121393112509701003020020000100006020030000100001200511200471150201100991004010010000100000100200000220000000020000202000321011611119824500020602000050100120052120053120052120052120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0055

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch call (8e)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst simd store (99)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafldst x64 uop (b1)b5l1d cache miss ld nonspec (bf)c2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
600251200419640000010026880001120037965131097402580013500121000120004400101000020000138489035733436346838210120011012005312005111216291125307001030020200001000060020300001000012005112003511500211009104001010000010000010200000220000100200000020314000317321198285000201092000050010120053120052120036120036120036
600241200359640001000020000012002096476109724258001350010100012000040010100002000013848787573348434670040012001101201261200511121623112530700103002020062100006002030000100001200511200471150021100910400101000001000001020000022000000020000022031610031722119826500000692000050010120052120036120052120053120052
600241200519650000110029000011200369648010974047800135001210001200004001010000200001384878757334363467079001200270120051120051112163311253070010300202000010000600203000010000120137120035115002110091040010100000100000102000002200001032000002003140003173311982650002101092000050010120124120036120053120052120039
60024120035965000011002010001200369648010974069800635001210000200004001010000200001384878757334363467769001200270120047120047112146311251570010301162000010000600203000010000120051120048115002110091040010100000100000102000002200000002000002203140003174411981050002101092000050010120052120036120048120036120048
6002412005496400000000140000012021896480109811241804505018410003200164013010123201001386357857378943469725101201860120316120217112208231129757506330396200641012860206302821003112032112021931500211009104001010000010000010200020220006078925200040000318100824351199745002410602000050010120142120322120233120313120220
60024120223965000000311400001120036964801097362580013500121000120000400101000020000138487875733580346798200120027012005112005111216231125307001030020200001000060020300001000012003512004711500211009104001010000010000010200000020000102372000002203140005173311982650000106102000050010120048120052120048120052120078
600241200479640000000020000112002096508109724258001350012100012000040010100002000013848787573343634678150012002731200511200511121623112520700103002020000100006002030000100001200511200471150021100910400101000001000001020000022000000020000022031400031722119826500020692000050010120054120052120048120048120052
6002412005196400000000200000120020964761097242580013500121000020000400101003120000138504335735644346647100120028012005412005111216231125147001030020200001000060020300001000012005112003511500211009104001010000010000010200000220000100200000020314000317221198275000210652000050010120054120052120053120052120052
600241200519640000000020000112003696512109740258001350010100012000040010100002000013849009573343634673450012001201200511200511121623112530700103002020000100006002030000100001200541200531150021100910400101000001000011020000022000000020000022031400031722119826500021010112000050010120052120048120052120048120052
600241200519640000000020000011200369648010972425800135001210001200004001010000200001384878757334363467351001200270120052120051112162311253070010300202000010000600203000010000120051120047115002110091040010100000100000102000002200000002000002203140004173211982250002141092000050010120052120052120052120053120052

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d, v1.2d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

retire uop (01)cycle (02)03mmu table walk data (08)090e0f18191e1f22243a3f4d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
60205120047931001100170001120020987631097402580103501001000020000401001000020000138550075733388346551011200311200511200511121353112505701003020020000100006020030000100001200521200471150201100991004010010000100001002000002200001032000020003210116111198245000210692000050100120052120052120052120052120058
6020412003593100000000001120020987631097872580103501001000120000401001000020000138540475733484346551011200271200531200351121233112505701003020020000100006020030102100321200511200351150201100991004010010000100001002000002200002002000022003210124111198265000210692000050100120052120054120226120053120052
6020412005193100000013800011200779876310974025801035010210001200004010010000200001385405757334363465510112002812005112005111213931125097010030200200001000060200300001000012005412013911502011009910040100100001000010020000022000010020000220032101241111982450000101092000050100120052120052120052123635120052
60204120035931000000212504000120036989051097402580103501001000020000401001000020000138537185732666346553811200271200351201371121393112509701003020020000100326020030000100001200511200471150201100991004010010000100001002000002200000002000022003210116111198245000210602000050100120057120055120052120052120052
602041201389310000110000112003698640109740258010350102100002000040100100002000013855189573526034655101120027120142120051112140311250970100302002006410000602003000010000120052120047115020110099100401001000010000100200000020000003200002200321021611119824500000692000050100120053120054120141120052120055
6020412005193100000020001120036987631097402580121501021000120000401001000020000138560725735068346553811200271200561200511121393112562701003020020000100006020030000100001200511200471150201100991004010010000100001002000002200000022882000022003231116111198995000210692000050100120052120048120052120036120048
602041200359300000002000012003898763109740258010350102100012000040100100002000013855544573526034655101120027120051120052112139311250570100302002000010000602003009310000120047120047115020110099100401001000010000100200000220004002226200002200321011611119824500020692000050100120036120052120052120052120036
6020412005193000000020000120020988631097402580103501001000120000401001000020000138560245733914346559711200231201401200511121393112509701003020020000100316020030000100001200511200471150201100991004010010000100001002000002200001002000022003210116111198245000012692000050100120052120052120052120052120052
6020412005193100000020000120036987631097402580103501021000120000401001000020000138543135733532346553911200271200511200471121413112509701003020020000100006020030000100001200491200541150201100991004010010000100001002000002200001002000022003210116111198245000210692000050100120052120052120052120052120052
60204120051931000000200011200369876310974025801005010210001200004010010000200001385146457336283465510112003012005112004811213931125107010030200200001000060200300001000012003512005111502011009910040100100001000010020000022000020020000220032101161111982450002111092000050100120052120052120052120055120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0061

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f464d4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9abacafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? int retires (ef)f5f6f7f8fd
600251200539301131000040001120038096486109746258001650014100022000040010100002000013847633573343634655240012001701200571200571121623112536700103002020000100006002030000100001200571200471150021109104001010000100000102000232200030000220000222003140003173311983250004101002000050010120042120058120058120058120052
60024120053930100101000000012002609648610974625800135001410001200004001010000200001384948357334363465408001200330120053120041112168311253070010300202000010000600203000010000120051120053115002110910400101000010000010200023220000000022000022221314000217331198265000410692000050010120059120052120058120052120059
600241200579300001010020000120042096558109746258001050014100002000040010100002000013849483573295634654080012001701200571200411121523112530700103002020000100006002030000100001200351200531150021109104001010000100000102000230200000000220000222213140002173211983250004101092000050010120058120058120058120058120058
6002412009893111010000400011200380964861097402580016500121000120000400101000020000138494835733724346523400120023012005712005711216831125367001030020200001000060020300001000012004112005311500211091040010100001000001020002222000201005200002022131400021743119816500046692000050010120054120054120052120058120058
60024120041931100000002000212004209648610974625800165001410002200004001010000200001384948357334363465408001200330120057120041112146311252070010300202000010000600203000010000120057120053115002110910400101000010000010200003220003000002000022220314000317221198325000410692000050010120060120058120059120058120052
60024120372930100000002010112004209648610973025800135001410002200004001010000200001384948357334363465408001200330120053120057112168311253070010300202000010000600203000010000120051120041115002110910400101000010000110200032220000001022000022220314000217221198225000210652000050010120058120052120058120053120058
60024120057931000100004000212003609648010974025800165001410002200004001010000200001384878757337243465234001200330120057120057112168311253670010300202000010000600203000010000120057120053115002110910400101000010000010200020220002001022000020221316900317321198285000210692000050010120052120058120052120058120058
600241200479301001000040001120042096488109746258001350012100012000040010100002000013849019573295634650600012003301200571200351121623112532700103002020000100006002030000100001200571200571150021109104001010000100000102000032200020000020000222203140003173311983250004101092000050010120063120058120058120058120058
600241200579301100000080001120042096486109746258001650012100022000040010100002000013849483573372434654080012002701200511200571121523112536700103002020000100006002030000100001200571200471150021109104001010000100000102000320200030000220000222003140003172211983250004101092000050010120058120058120058120058120052
60024120057931100100002000012004209648610974825800135001410002200004001010000200001384948357334363465408001200330120054120057112164311253070010300202000010000600203000010000120051120057115002110910400101000010000010200022220000011022000022020314000217221198265000461092000050010120058120036120054120052120042

Test 4: throughput

Count: 8

Code:

  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
160205800416200000000072000800252121216252401008010016000080104160006202389036693901800158004080040599597599932401102001600162002400248004080040118020110099100100800008000001001600000016003100361600366132000111511701600800370800001010160000801008004180041800418004280041
16020480040621000000003800280025012121625240100801001600008010016000020264683662873180015800408004059967359998240100200160000200240000800408004011802011009910010080000800001100160000035160036003716003661364000000511011611801380800001410160000801008004180041800418004180041
16020480040620000000004200080025212121625240100801001600008010016000020133913667589180015800408004459954359998240100200160000200240000800408004011802011009910010080000800000100160000035160036103616003661314000000511011611800370800001414160000801008004180041800418004280041
1602048004062000000000540028002521201125240100801001600008010016000020267113679312180015800408004059954359998240100200160000200240000800408004011802011009910010080000800000100160000035160036003216003661364000000511011611800370800001414160000801008004180041800418004180041
16020480040621000000005400080025212121125240100801001600008010016000020333193673474180015800408004059953359998240100200160000200240000800408004111802011009910010080000800000100160000035160036003916003601324000000511011611800370800001410160000801008004180041800418004180041
16020480040620000010004200280025212121625240100801001600008010016000020164273669355180015800408004059959359998240100200160000200240000800408004011802011009910010080000800000100160000037160039003616003661324000000511011611800371800001010160000801008004180041800418004180042
1602048004062000000000420028002521212112524010080100160000801001600002039738367935218001580040800405995335999924010020016000020024000080040800411180201100991001008000080000010016000003516003600391600366104000000511011611800370800001410160000801008004180041800418004280041
16020480040620010000003800280025212121625240100801001600008010016000019835613669355180015800418004059954359998240100200160000200240000800408004011802011009910010080000800000100160000035160032103116003261323500000511011611800370800001410160000801008004180041800418004180041
16020480040620000000004201280025212121625240100801001600008010016000020165153669355180015800408004059968359998240100200160000200240000800408004011802011009910010080000800000100160000035160000204216003661333500000511011611800370800001010160000801008004280041800438004180041
16020480040620000000005400280025212121625240100801001600008010016000020402503669355180015800408004059953359998240100200160000200240000800408004111802011009910010080000800000100160000035160036103216003661324000000512511611800370800001410160000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? int retires (ef)f5f6f7f8fd
160025800406210000000004200280025212121625240010800101600008001016000020311633676791008001580040800405997636002024001020160000202400008004080040118002110910108000080000010160000035160036099034160036613640050200032153434800370800001410160000800108004180041800418004180041
16002480041621000000000540008002521212162524001080010160000800101600002039153367598800800158004080040599753600202400102016000020240000800408004011800211091010800008000001016000003516003600036160032613240050200032163212800370800001014160000800108004180041800418004180041
160024800406200000000005400280027212121625240010800101600008001016000020391533675936008001580040800405997636002024001020160000202400008004180040118002110910108000080000110160000035160036097036160036613640050200030161232800370800001414160000800108004180041800418004180041
160024800406210000000005400280025212121625240010800101600008001016000020061903672662108001580040800405997536002024001020160000202400008004080040118002110910108000080000010160000040160036050038160032613140051631032163232800370800631414160000800108004180041800418004180041
160024801576200000010013800280025212121625240010800101600008001016000020391533658059008001580040800405997536002124001020160000202400008004180040118002110910108000080000010160000035160036041036160036613235050200014161538800370800001414160000800108004180041800418004180041
16002480041620000000000420028002521212162524001080010160000800101600002039153367266200800168004080040600253600212400102016000020240000800408015711800211091010800008000001016000003716003600039160036613243050200032163232800370800001414160000800108004180041800418004180041
1600248004062000000000042002800252610162524001080010160000800101600002024786367266200800158004080040599763600202400102016000020240000800408004011800211091010800008000001016000004016003601041160032613540050200035163332800370800001414160000800108004180041800418004180041
16002480040620000000000450008002521212162524001080010160000800101600002039153367266000800158004080040599753600202400102016000020240000800408004011800211091010800008000001016000004016003600042160032613240050200035161435800370800001014160000800108004280041800418004180045
16002480040620000000000540008002521212162524001080010160000800101600002011457366618500800158004080044599753600202400102016000020240000800408004021800211091010800008000001016000004016003600039160036613140050200032161232800370800001414160000800108004180041800418004180156
160024800406200000000291420028002521213112524001080010160000800101600002024570366935500800158004080040599763600202400102016000020240000800408004011800211091010800008000001016000003516003600039160036613237250200012161335800370800001410160000800108004180041800418004180041