Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 2 regs, 4H)

Test 1: uops

Code:

  ld1 { v0.4h, v1.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f243a3f43464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6200529498237023017000003004685290800002441920001000100010001000500050000316071288552940131020002000300029277292721161001100010000100002100000010002020001318093576951320714412088032753820845382876310001636013574152831000100010002963729751299632973829824
62004297072390260190001014617604717291340102453420001000100110011000501050430216095288462944891020002000300029216292741161001100010000100052100000795100020200013389934368763087114520906335938181445482890510011635513605150861000100010003000029960297622982629809
620042972023802111920023266264046622948000024389200010001000100010005000500001160572902129690310200620003000293172939211610011000100001000121005103100020210013027933869123143104420822325938131142462848410001609213615150891000100010002919029315295092921129289
6200429184235019015000002004649291230002450520001000100010001000500050000316071288132944131020002000300029351291811161001100010000100022100000110012020001309194076925313185020594320638161242442842110001633713889149891000100010002966029488294362970429366
6200429338236118021000004004683288900002437320001000100010001000500050000116074286492934431020002000300029078291861161001100010000100002100001404100021300013140940969273159125020824317638171139452854210001824814997166461000100010003045730841308903153629362
62004293862290150130000040046662888600024527200010001000100010005000500001160862892529358310200020003000292932933311610011000100001000021001013100020200013276925169323136114920896341338121251442875910001610813442147821000100010002932429595294442940929430
620042952523601301600000000480528956000244032000100010001000100050005000011607428888295213102000200030002937329779116100110001000010000210030016551000202033861342295576945313294620914332438061343472875410001997513846153871000100010002937529433294502938129320
620042940822801701800000200462728879000244052000100010001000100050005000021606528816293533292000200030002924429114116100110001000010030210000042610002020019413334957769743160124421103332938141046472867510001633713851150921000100010002934129461293012923329379
6200429291236017017000001188046952892801024816200010001000183510005000500001216084286812936931020002000300028743285291161001100010000100002100600110002030001296092986974317495020255339838091547412848810001630013872150261000100010002937029308294642938029377
620042932922701601701110200461928915000243382000100010001000100050005000061606828634294753102000200030002916429156116100110001000010000210000001000200020132119526692631526442075032933829843422860910001616113429150581000100010002933129351294852938729423

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h, v1.4h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)18191e1f22243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
602051200539300010020001120026119633257010650104100021000040100100001000010619234545931457458201200321200501200351120433112447601003020020000100006020030147100001200501201351150201100991004010010000100001001000110100010201100001100000032101831111975950004068100001000050100120057120058120057120042120143
602041200569301000010000120041119717257010350100100001000240100100001000010617954546159457446501200261200561200561120463112471601003020020000100006020030000100001200501200481150201100991004010010000100001001000120100000124100001011100032101833111974850004968100001000050100120057120057120054120051120057
602041200569310010010000120041119633257010650104100021000040100100001000010621854545931457446501200111200561200561120403112432603193020020000100006020030000100001200561200531150201100991004010010000100001001000001100010200100001011100032101831111975150002908100001000050100120051120051120051120051120057
6020412005093100000220000120036119712257010650114100021000040100100001000010621944544293457469901200321200501200501120423112501601003020020000100006020030000100001200561200541150201100991004010010000100001001000000100010000100001110000032101961111975350004098100001000050100120058120057120059120036120130
60204120041931000001176100120041119633257010650104100021000040100100001000010621854545931457446501200321200561200561120463112447601003020020000100006020030000100001200411200532150201100991004010010000100001001000101100010004100001011100032101831111975350002998100001000050100120051120051120051120051120042
602041200509310110020000120026119724257010350102100011000040100100001000010622394546159457446501200261200561201471120463112443601003020020000100006044230000100001200501200351150201100991004010010000100001001000001100020003100001111000032101831111975950000998100001000050100120051120042120042120057120057
602041200359301000010000120045119639257010350102100011000040100100001003910617954546159457339001200321200501200351120463112447601003020020000100006020030000100001200591200471150201100991004010010000100001001000001100010001079551000210111000321018311119753500021005100001000050100120051120051120051120052120057
602041200509310010010000120020119633257010650104100021000040100100001004010621854545931457469901201091200501200351120403112447601003020020000100006020030000100001200561200541150201100991004010010000100001001000221100000012846100001111000032101831111975350004968100001000050100120057120057120057120051120057
60204120056931000001000012004111963325701065010410002100024010010000100001062185454608345730440120032120056120053112046151124476010030200200001000060200300001000012005612005311502011009910040100100001000010010002011000100011000010100000321019611119759500159108100001000050100120057120057120057120054120036
602041200579301010020000120042119734257010350102100011000040100100001000010617954546159457446501200261200561201311120463112413601003020020000100006044830000100001200501200501150201100991004010010000100001001001011100000104100001011300032101831111974850004090100001000050100120057120058120036120051120057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f233a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6002512010989900100000000012003911970825700135001210001100004001010000100001062237454861445779791200271200351200511120733112469600103002020000100006002030000100001200511200511150021109104001010000100001101000001100001001000011000314013781191197635000231109100001000050010120052120052120055120052120036
6002412005493100100000100012003911968625700135001210001100004001010000100001062237454799245780961200271200511200511120733112469600103002020000100006002030000100001200511200511150021109104001010000100000101000001100002001000011000314011781212119815500021000100001000050010120053120052120052120036120052
60024120051931000000001000120042119708257001350012100011000040010100001000010622644548690457760512003012005112003511207731124726001030020200001000060020300001000012005112005411500211091040010100001000001010000011000000010000110003140137812131197605000201012100001000050010120056120194120053120052120056
6002412003593100000000100012003611970525700135001210001100004001010000100001062264454861445780571200301200541200541120573112469600103002020000100006002030000100001200351200511150021109104001010000100000101000001100026001000011020314010781311119760500020139100001000050010120036120055120055120057120056
600241200549310000000010001200951197082570027500121000110000400101000010000106216845487284587153120030120051120054112076311246960010300202000010000600203000010000120054120145115002110910400101000010000010100000110000000100001101031401478119119761500020109100001000050010120153120055120061120055120057
600241200519300000000010001200911197082570013500121000110000400101000010038106226445487284577979120031120051120051112076311245360010300202000010000600203000010000120054120051115002110910400101000010000010100000110000000100000100031401078131111976050002101012100001000050010120055120055120055120055120055
6002412005693100010000180001200411196632570013500121000110000400101000010000106216845487284577979120030120054120145112079311246960010300202000010000602663000010000120035120051115002110910400101000010000010100000110000000100001100031401178912119764500020013100001000050010120055120055120036120055120055
600241200569300000100010001200361197084970013500121000010000400101000010000106223745486144577979120031120052120054112073311246960010300202008010000600203000010166121767120144115002110910400101000010000110100000110000000100001100031409781312119760500020109100001000050010120055120055120055120038120055
600241200359300000110010001200361197052570013500121000110000400101000010000106223745486144577979120030120054120054112076311246960010301432000010000600203000010000120054120054115002110910400101000010000010100000110000100100001100031401078129119763500020109100001000050010120055120052120147120055120055
6002412005193000000000100012003711970525700275001210001100004001010000100001062168454861445779791200301200351200541120793112472600103002020000100006002030123100001200511200541150021109104001010000100000101000001100000091000011000314013781010119763500020013100001000050010120055120055120055120055120056

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h, v1.4h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0056

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f22243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
602051200539311001000200001200411197192570103501041000410000401001000010000106223945461594574699120033120056120056112046311244760564302002000010000602003000010000120057120041115020110099100401001000010000110010001101000100260110000111120321018311119837500041168100001000050100120057120057120058120057120059
602041200569311000000140100120043119639257010650104100021000040100100001000010622394547233457481612003212005612005611204931124476010030322200001000060200300001000012005612005311502011009910040100100001000011001000111100012141000111111032101831111975950004998100001000050100120057120042120044120058120057
6020412005693011100001400001200411196362570106501041000110000401001000010000106223945473344574699120018120056120057112042311244460100302002000010000602003000010000120056120053115020110099100401001000010000110010001111000200341000011111032331831111984450004098100001000050100120042120042120054120042120057
60204120149931110000020000120026119643257010650104100021000040244100001000010622394546159457469912003212004112004111204331124476031930200200001000060200300001000012004112005311502011009910040100100001000011001000310100020241000011110032101831111975950004098100001000050100120057120054120054120054120154
60204120041930110000020000120026119717257010650114100021000040100100001000010622394546199457469912001712005612005611204631124476010030200200001000060200300001000012005612005611502011009910040100100001000001001000111100351341000011110032101831111976050004990100001000050100120059120057120057120042120128
6020412005693110100001100001200411196392570103501141000110000401001000010000106223945461984574699120032120059120041112046131124506010030200200001000060200300001000012005312005311502011009910040100100001000011001000111100011011000011110032101831111975450004969100001000050100120057120057120057120057120054
60204120041930101000020000120041119639257010650104100021000040100100001000010622394546159457469912003212004112004111208231124446010030200200001000060200301231000012005612005311502011009910040100100001000001001000211100021011000011110032101831111975950004669100001000050100120057120057120058120060120057
602041200589301100000140001120038119639257010350104100021000040100100001000010644544546159457469912008712005312004111204231124476010030200200001000060200300001000012005612005311502011009910040100100001000001001000121100020028491000011110032101831211975950004968100001000050100120057120057120057120054120057
602041200569311100000200000120041119639257010650114100021000040100100001000010622394546159457473712003212005612005711204631124476010030200200001000060200300001000012006012006421502011009910040100100001000011001000211100011011000011116032331831211984750015968100001000050100120230120506122463122196120142
6020412023593312200233981760001202331198355070129501141000510005405301004010119106350945530034575991120186120238120248112108251125516054230440203221004161176301231008112019012015041502011009910040100100001000011001000211100010111000011110032101831111976150002998100001000050100120058120054120057120057120057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
600251200519300010100010100120039119708257001350012100021000040010100001000010622644548842457760500012034312038112005311208231124776001030020200001000060020300001000012005412005111500211091040010100001000001010000011000000010000101003140001378133111976950002131012100001000050010120055120055120055120055120055
6002412003593100010000101001200391197092570013500121000110000400101000010000106226445487664577979010120011120060120054112076311247560010300202000010000600203000010000120054120055115002110910400101000010000010100000110000000100001011031400032782827119744500020012100001000050010120055120055120056120061120055
60024120035930010000001010012004511971425700135001210001100004001010000100001062264454872845782510001200371200541200541120763112472600103002020000100006002030000100001200541200511150021109104001010000100000101000021100000001000010100314000137815321197605000210109100001000050010120061120063120055120052120055
60024120054931100000001000012002011970825700135001210001100004001010000100001062336454861445779791151200301200541200541120763112475600103014020000100006002030000100001200601200571150021109104001010000100000101000000100000041000011000314000117712301197635000213130100001000050010120036120055120059120036120055
60024120060930000001002010012003911970825700275001010001100004001010000100001062291454872845779790001200301200541200541120763112474600103002020000100006002030000100001200541200522150021109104001010000100000101000001100000031000010000314000307831121197635004013139100001000050010120055120036120055120055120145
6002412005193100000000180000120039119712507001350014100011000040010100001000010622644548728457809600012003212005412006011205731124746001030020200001000060020300001000012005412003511500211091040010100001000001010000011000100010000101003140003278332911976350002131012100001000050010120055120055120055120060120036
60024120035931000000001010012003911970925700135001210001100004001010000100001062282455062645779790001200301200541200541120763112496600103016320080100006002030000100001200511200511150021109104001010000100000101000001100001001000010100314000328426301197635037901312100001000050010120055120052120061120062120145
600241200519300000000070000120045119714257001350010100031000040010100001000010621864548956458051700512003712005412008011205731124786001030020200001000060020300001000012003512005111500211091040010100001000001010001211000000010000100003140001378272711976650002131012100001000050010120061120055120148120036120055
600241200359300000000110100120040119708257001050012100011000040010100001000010622644550409457797900012001112005512005311207631124736001030020200001000060020300001000012006012005111500211091040010100001000001010000011000000110000101003140043077311111976350002131012100001000050010120055120052120053120055120145
60024120054931000000001330100120039119708257001350010100021000240010100001000010622644548728457760500012003012005412005511206431124536001030020200001000060262300001000012005412005311500211091040010100001000001010000011000001310001100003140003178301211976950000131012100001000050010120055120055120055120055120061

Test 4: throughput

Count: 8

Code:

  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f23243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160205800406210100000000000800251060251601008010080025801008000043590023758824080015800408009459924359998160100200160000200240000800408004011802011009910010080000800001100800000080000001280013619170051101161180037180000968000080000801008004180041800418004180041
160204801856210000000019880008002516062516010080813800008010080000435900637588240800158004080040599243599981601002001600002002400008004080040118020110099100100800008000001008000001480000001580013001300051101161180037080000968000080000801008004180041800418004180041
16020480040621000000014000008002516642516010080100800008010080000435901037588240800158004080040599243599981601002001600002002400008004080040118020110099100100800008000001008000001480015201280000619170051101161480037080000098000080000801008004180095800418004180041
16020480040620000000001800008002516642516010080100800008010080000435866637588240800158004080040599243599981601002001600002002400008004080040118020110099100100800008000001008000001480000001380012611000051101161180037180000968000080000801008004180041800418004180041
160204800406200000000016200008002510082516010080100800008010080000435900637588240800158004080040599243599981601002001600002022400008004080040118020110099100100800008000001008000001480013001380013619170051101161180037180000968000080000801008004180041800418004180041
16020480040620000000002801008002516662516010080100800258010080000435900237588240800158004080040599241059998160100200160000200240000800408004011802011009910010080000800000100800000148003700138001300900051103251180037180000968000080000801008004180041800418004180041
16020480040621000000001900008002516682516010080100800258010080000435900637588240800158004080040599243599981601002001600002002400008004080040118020110099100100800008000001008000001780012001380013610170051252161180037080027968000080000801008004180041800418004180041
1602048009562300000000310000800251665225160100801008000080100800004359006375882408005480040800405992435999816010020016000020024000080040800401180201100991001008000080000010080000014800130010800136110170051101161180037180000968000080000801008004180041800418004180041
16020480040621000000002201008002516652516010080100800258010080000435899037588240800158009580040599243599981601002001600002002400008004080040118020110099100100800008000001008000001780013101380000601000051102161180037180000708000080000801008004180041800418004180041
160204800406200000000019000080025166725160100801008000080100800004359002375882408001580040800405992410599981601002001600002002400008009280040118020110099100100800008000001008000001480009001380013601000051101161180037080000668000080000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f223f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160025800406210010000016018002516602516001080037800008001080000435839737588200800158004080040599463600201600102016000020240000800408009411800211091010800008000001080000014800000102598001361014050203163380037080000998000080000800108004180041800418004180041
160024800406200000000030008002516682516001080010800008001080000435770537588240800158004080040599463600201601552016000020240000800408004011800211091010800008000001080022208000000099080041619140502031633800771800271298000080000800108009680096802048009580148
160024800956210001001115117608013306692731601168003780025800868006943548023775864080054800958014959958106007116030020160152202402288009480149218002110910108000080000010800220148005701017438003260914250363253380037080000998000080000800108004180041800418004180041
1600248004062110000000190080025106025160010800108000080010800004358381375882418001580040800405994636002016001020160000202400008004080040118002110910108000080000010800000178001300023280019011017050203163380037080000098000080000800108004180041800418004180041
16002480040620000000001900800251600251600108001080000800108000043583813758824080015800408004059946360020160010201600002024000080040800401180021109101080000800000108000000800120002778000900014050203163380037080000998000080000800108004180041800418004180041
1600248004062000000000190080025160102516001080010800008001080000435836937588240800158004080040599463600201600102016000020240000800408004011800211091010800008000001080000017800130102988001961917050203163380037180000998000080000800108004180041800418004180041
160025800406200000000019008002516602516001080010800258001080276435842537587810800158004080040599463600201600102016015220240000800408004011800211091010800008000001080000014800130201408001260917050203163380037080000098000080000800108004180041800418004180041
1600248004062100000000000800251004251600108001080000800108000043583733758824080015800408004059946360020160010201600002024000080040800401180021109101080000800000108000001480034020265800096190050203163380037080027998000080000800108004180041800418004180041
160024800406200000000019008002506692516001080010800008001080000435835737588230800158004080040599463600201600102016000020240000800408004011800211091010800008000001080000008001201029180009612617050203163380077180000998000080000800108004180041800968004180041
160024800406200000100018008002506644916001080010800008001080000435840537588240800158004080040599463600201600102016000020240000800408004011800211091010800008000001080000014800000007580010601317050203163380037080000998000080000800108004180041800418004180041