Firestorm: LD1 (multiple, post-index, 2 regs, 4S) measurements

Code:

  ld1 { v0.4s, v1.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
62005	28828	223	1	24	1	1	29	0	1	1	0	0	2	0	1	0	0	4801	28401	0	0	23824	3000	1000	2000	1000	2000	5000	10000	7	16057	28302	28645	3	10	3000	2000	3000	28620	28801	1	1	61001	1000	1000	0	2003	3	0	2003	0	0	1	2	2000	0	0	2	4	2	1	0	13206	9467	6966	3210	17	68	20114	3183	3815	18	66	64	28129	1000	15668	13047	14390	2000	1000	28651	28820	28742	28710	28748
62004	28765	222	1	24	0	1	29	0	0	0	0	0	6	0	0	0	0	4668	28444	0	0	23676	3000	1000	2000	1000	2000	5000	10000	6	16058	28287	28826	3	10	3000	2000	3000	28601	28612	1	1	61001	1000	1000	0	2003	3	4	2004	0	0	0	2	2000	6	0	2	4	2	0	0	13388	9527	6952	3131	13	78	20209	3132	3818	10	65	68	28281	1000	15666	12941	14458	2000	1000	28694	28788	28794	28835	28791
62004	28804	223	1	24	0	1	28	1	0	0	0	0	3	0	0	0	0	4804	28415	0	0	23722	3000	1000	2000	1000	2000	5000	10000	5	16068	28251	28836	3	10	3000	2000	3000	28661	28488	1	1	61001	1000	1000	0	2003	3	4	2003	0	0	1	2	2000	2	0	4	0	2	2	0	13315	9344	6972	3187	12	68	20158	3215	3817	14	60	61	28174	1000	15369	12696	14155	2000	1000	28684	28834	28748	28705	28767
62004	28744	223	0	29	1	1	26	1	0	0	0	0	4	0	0	0	0	4866	28382	0	0	23641	3000	1000	2000	1000	2000	5000	10000	4	16051	28271	28730	3	10	3000	2000	3000	28635	28588	1	1	61001	1000	1000	0	2003	2	0	2003	0	0	1	2	2002	4	0	2	6	2	0	0	13260	9588	6951	3179	9	75	20077	3153	3816	15	63	60	28172	1000	15490	13144	14240	2000	1000	28744	28826	28700	28701	28672
62004	28759	223	1	31	0	1	21	0	0	0	0	0	3	0	0	0	0	4786	28378	0	0	23619	3000	1000	2000	1000	2000	5000	10000	3	16070	28286	28716	3	10	3000	2000	3000	28704	28597	1	1	61001	1000	1000	0	2003	4	4	2002	0	0	0	2	2000	0	0	2	0	2	1	0	13229	9504	6936	3144	18	64	20101	3201	3815	15	68	67	28147	1000	15203	13107	14228	2000	1000	28853	28689	28929	28810	28759
62004	28780	224	1	23	1	1	28	1	0	0	0	0	3	0	0	0	0	4801	28374	0	0	23675	3000	1000	2000	1000	2000	5000	10000	3	16043	28260	28782	3	10	3000	2000	3000	28596	28725	1	1	61001	1000	1000	0	2003	2	0	2003	0	0	0	2	2000	0	0	2	0	2	0	0	13136	9546	6974	3135	16	67	20215	3193	3813	18	60	66	28218	1000	15417	12881	14140	2000	1000	28849	28762	28859	28668	28694
62004	28866	223	1	28	1	1	27	0	0	0	0	0	3	0	1	0	0	4782	28387	0	0	23589	3000	1000	2000	1000	2000	5000	10000	7	16054	28292	28799	3	10	3000	2000	3000	28753	28744	1	1	61001	1000	1000	0	2002	3	4	2002	0	0	1	2	2000	4	0	2	4	2	1	0	13176	9605	6971	3165	11	68	20131	3137	3818	14	67	59	28124	1000	15372	13037	14530	2000	1000	28806	28742	28784	28787	28731
62004	28676	222	1	20	1	0	22	1	0	0	0	0	107	0	0	0	0	4785	28413	0	0	23711	3000	1000	2000	1000	2000	5000	10000	3	16080	28211	28795	3	10	3000	2000	3000	28604	28644	1	1	61001	1000	1000	0	2002	3	4	2004	0	0	1	2	2000	4	0	2	4	2	1	0	13235	9550	6910	3186	13	70	20104	3175	3814	16	62	66	28276	1000	15282	12784	14030	2000	1000	28721	28863	28747	28820	28762
62004	28748	222	1	26	1	1	33	0	0	0	0	0	2	0	0	0	0	4819	28436	0	0	23633	3000	1000	2000	1000	2000	5000	10000	7	16076	28260	28761	3	10	3000	2000	3000	28539	28658	1	1	61001	1000	1000	0	2003	3	0	2003	0	0	1	2	2000	0	0	2	0	2	0	0	13168	9623	6974	3165	13	69	20153	3125	3810	15	64	63	28215	1000	15319	12899	14339	2000	1000	28702	28726	28669	28683	28762
62004	28811	223	1	20	0	1	27	1	0	0	0	0	8	0	1	0	0	4900	28505	0	0	23632	3000	1000	2000	1000	2000	5000	10000	3	16073	28268	28733	3	10	3000	2000	3000	28633	28632	1	1	61001	1000	1000	0	2002	3	4	2003	0	0	1	2	2000	0	0	2	4	2	1	0	13340	9628	6931	3233	12	75	20194	3198	3816	14	68	67	28162	1000	15568	12855	14316	2000	1000	28648	28762	28790	28811	28740

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s, v1.4s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120065	932	0	0	0	0	0	0	2	0	1	0	0	0	120040	98767	109744	25	80103	50102	10001	20000	40100	10000	20000	13851582	5733532	3465654	0	120031	120055	120055	112143	3	112519	70100	30200	20000	10000	60200	30000	10000	120051	120038	1	1	50201	100	99	100	40100	10000	10000	0	100	20002	2	2	20002	0	1	5	20000	2	2	0	0	0	3210	1	16	1	1	119828	50002	14	14	13	20000	50100	120036	120056	120056	120138	120036
60204	120035	931	0	1	0	0	0	0	14	0	0	0	0	1	120040	98905	109745	25	80103	50102	10001	20000	40100	10000	20000	13854750	5732762	3465626	0	120032	120146	120055	112143	3	112513	70100	30200	20000	10032	60200	30000	10000	120055	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	20004	0	2	20000	0	0	0	20000	2	2	0	0	0	3210	1	16	1	1	119828	50002	14	13	13	20000	50100	120056	120056	120056	120036	120056
60204	120055	931	0	0	0	0	0	0	2	0	0	0	0	1	120037	98769	109744	25	80103	50102	10004	20000	40100	10000	20000	13857666	5733628	3465242	0	120031	120055	120055	112144	3	112565	70100	30200	20000	10000	60200	30000	10000	120055	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	2	0	0	0	3210	1	16	1	1	119828	50013	0	10	14	20000	50100	120056	120056	120057	120059	120036
60204	120055	931	0	0	0	0	0	0	2	0	0	0	0	1	120041	98767	109744	25	80103	50102	10001	20000	40100	10000	20000	13855329	5733916	3465626	0	120033	120055	120055	112145	3	112513	70100	30295	20000	10000	60200	30000	10000	120055	120055	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	0	20012	2	2	0	0	0	3210	1	16	1	1	119828	50002	14	14	13	20000	50100	120056	120056	120056	120056	120056
60204	120055	931	0	0	0	0	0	0	2	0	0	0	0	1	120040	98905	109744	25	80100	50100	10001	20000	40100	10000	20000	13851711	5733724	3465626	0	120031	120055	120055	112143	3	112513	70100	30200	20000	10000	60200	30000	10000	120146	120052	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	2	0	0	20000	2	2	0	0	0	3210	1	16	1	1	119829	50002	14	10	16	20000	50100	120036	120057	120056	120036	120036
60204	120057	930	0	0	0	0	0	0	2	0	0	0	0	1	120040	98767	109744	25	80103	50100	10001	20000	40100	10000	20000	13859414	5734156	3465798	0	120089	120051	120055	112143	3	112513	70100	30200	20000	10000	60200	30000	10000	120055	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	0	20000	2	2	0	0	0	3210	1	16	1	1	119833	50002	10	10	13	20000	50100	120036	120038	120036	120059	120056
60204	120035	931	0	0	0	0	0	0	2	0	0	0	0	0	120043	98808	109744	25	80103	50102	10001	20000	40100	10000	20000	13857828	5734780	3465771	0	120031	120055	120138	112139	3	112513	70100	30200	20000	10031	60200	30000	10000	120055	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	2	0	0	0	3232	1	16	1	1	119911	50002	14	10	13	20000	50100	120056	120056	120056	120056	120056
60204	120035	931	0	0	0	0	0	0	2	0	0	0	0	1	120040	98767	109744	25	80100	50113	10000	20000	40100	10000	20000	13853639	5734012	3465654	0	120011	120035	120052	112143	3	112513	70100	30200	20000	10000	60200	30000	10000	120055	120139	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	0	2	0	0	0	3210	1	16	1	1	119808	50002	14	14	0	20000	50100	120036	120056	120036	120058	120052
60204	120055	931	0	0	0	0	0	0	2	0	0	0	0	1	120040	98905	109745	25	80100	50102	10001	20000	40100	10031	20000	13862317	5733724	3465742	0	120031	120055	120056	112143	3	112513	70100	30200	20000	10000	60200	30000	10000	120055	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	20010	2	2	0	0	0	3210	1	16	1	1	119828	50002	14	14	13	20000	50100	120056	120036	120061	120052	120056
60204	120051	931	0	0	0	0	4	2	266	0	0	0	0	1	120135	98645	109789	48	80118	50122	10004	20004	40219	10031	20050	13868980	5736818	3468946	0	120113	120241	120316	112257	15	112626	70299	30394	20190	10064	60778	30093	10094	120214	120229	4	1	50201	100	99	100	40100	10000	10000	0	100	20006	2	2	20010	0	2	2295	20006	2	2	2	0	0	3251	2	32	1	2	120066	50033	14	10	13	20000	50100	120210	120234	120330	120151	120248

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120051	930	0	0	0	0	0	0	0	0	0	0	2	0	0	0	1	120037	96561	109728	25	80013	50012	10001	20000	40010	10000	20000	13848787	5733436	3465234	0	120011	120052	120051	112158	3	112530	70010	30020	20000	10000	60020	30000	10000	120051	120049	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	1	0	0	20000	2	0	2	0	0	3140	0	19	24	20	13	119810	50000	10	6	9	20000	50010	120052	120036	120116	120175	120145
60024	120051	931	0	0	0	0	1	1	0	0	0	0	132	0	0	0	0	120020	96505	109745	25	80013	50012	10001	20000	40010	10000	20000	13848787	5733436	3465234	0	120027	120144	120051	112164	3	112530	70010	30020	20000	10031	60020	30000	10031	120051	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	3	20000	2	0	2	0	0	3140	0	25	17	19	24	119906	50002	10	0	9	20000	50010	120048	120134	120105	120087	120036
60024	120051	930	0	0	0	0	0	0	0	0	1	0	2	0	0	0	1	120036	96530	109745	25	80013	50012	10001	20000	40010	10000	20000	13848787	5733436	3466979	0	120027	120051	120051	112162	3	112526	70010	30116	20000	10000	60020	30000	10033	120035	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	3161	0	23	17	23	23	121972	50000	10	0	9	20000	50010	120052	120055	120124	120165	120052
60024	120051	931	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	120036	96504	109741	25	80013	50012	10001	20000	40130	10000	20000	13848787	5732666	3465234	0	120027	120051	120051	112162	17	112530	70214	30020	20000	10000	60020	30000	10000	120052	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	3140	0	21	26	19	19	119810	50002	12	10	9	20000	50010	120149	120048	120111	120055	120129
60024	120051	931	0	0	0	0	0	0	0	0	0	0	2	88	0	0	1	120036	96519	109745	48	80013	50023	10001	20000	40010	10000	20000	13848787	5733436	3465234	0	120066	120051	120051	112158	3	112530	70010	30020	20000	10000	60020	30000	10000	120233	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	1	0	0	20000	0	0	2	0	0	3140	0	21	17	22	15	119826	50002	10	10	9	20000	50010	120052	120228	120052	120127	120052
60024	120051	931	0	0	0	0	0	0	0	0	1	0	6	0	0	0	1	120020	96505	109740	25	80010	50012	10001	20004	40010	10000	20000	13846911	5736386	3465350	0	120034	120047	120036	112162	3	112530	70010	30020	20000	10000	60020	30000	10000	120051	120136	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	2250	20000	2	0	2	0	0	3140	0	21	17	24	20	119899	50002	10	6	9	20000	50010	120052	120036	120104	120093	120052
60024	120035	930	0	0	0	0	0	0	0	0	0	0	2	0	0	0	1	120036	96476	109730	36	80031	50012	10001	20000	40010	10000	20000	13848323	5733772	3465377	0	120027	120036	120052	112162	3	112514	70010	30020	20000	10000	60020	30000	10000	120051	120047	25	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	2	6	20000	2	0	2	0	0	3140	0	24	17	21	22	119826	50002	10	10	11	20000	50010	120052	120052	120116	120085	120141
60024	120035	930	0	0	0	0	0	0	0	0	0	0	2	88	0	0	1	120036	96558	109741	46	80010	50012	10000	20000	40010	10000	20000	13846911	5733484	3464880	0	120011	120051	120051	112146	3	112530	70010	30020	20000	10000	60020	30000	10000	120137	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	1	0	3	20000	2	0	0	0	0	3140	0	23	17	20	20	119826	50002	10	10	5	20000	50010	120036	120142	120113	120078	120052
60024	120035	930	0	1	0	0	0	0	0	0	1	0	2	0	0	0	2	120036	96531	109741	25	80010	50010	10001	20000	40010	10000	20000	13854554	5733436	3465234	0	120027	120051	120051	112205	3	112530	70010	30020	20000	10000	60020	30000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20004	0	0	0	0	20000	2	0	2	0	0	3140	0	22	17	21	20	119826	50002	10	6	9	20000	50010	120052	120052	120120	120084	120142
60024	120051	931	0	0	0	0	0	0	0	0	0	0	6	88	0	0	2	120042	96485	109748	48	80016	50014	10002	20000	40010	10000	20000	13849483	5733724	3465582	0	120033	120058	120057	112209	3	112536	70010	30020	20000	10000	60020	30096	10000	120146	120057	1	1	50021	10	9	10	40010	10000	10000	0	10	20003	2	0	20003	0	0	0	5	20000	2	2	2	2	0	3140	0	13	17	24	21	119832	50004	0	10	0	20000	50010	120143	120058	120134	120426	120042

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s, v1.4s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120057	931	0	0	1	1	0	0	2	0	0	0	120036	98905	109724	25	80103	50102	10001	20000	40100	10000	20000	13848583	5733628	3467220	1	120029	120055	120035	112139	3	112515	70100	30296	20000	10000	60200	30000	10000	120055	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	3	20000	0	2	0	0	3230	1	16	1	1	119828	50002	10	10	13	20000	50100	120097	120056	120056	120056	120056
60204	120151	930	0	0	0	0	0	0	2	0	0	1	120042	98763	109744	25	80103	50102	10000	20000	40223	10000	20000	13851155	5733436	3465654	1	120031	120057	120055	112143	3	112493	70100	30200	20000	10000	60200	30000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	2	0	0	3210	1	16	1	1	119824	50012	0	14	13	20000	50100	120052	120036	120056	120052	120036
60204	120055	930	0	0	0	0	0	0	14	0	0	1	120040	98767	109797	25	80103	50102	10001	20000	40100	10000	20000	13850923	5733628	3465626	1	120027	120055	120051	112180	3	112513	70100	30200	20000	10000	60200	30093	10000	120055	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20004	0	2	20000	0	0	3	20000	2	2	0	0	3210	1	16	1	1	119828	50002	16	14	13	20000	50100	120052	120052	120056	120056	120052
60204	120035	930	0	0	0	0	0	0	2	0	0	1	120041	98767	109744	25	80103	50102	10001	20000	40220	10000	20000	13850574	5733628	3465156	1	120027	120055	120055	112123	3	112570	70100	30200	20000	10000	60200	30000	10000	120058	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	3	20000	2	2	0	0	3210	1	16	1	1	119824	50002	11	10	0	20000	50100	120052	120052	120056	120060	120036
60204	120035	930	0	1	0	0	0	0	14	0	0	1	120040	98767	109740	25	80103	50102	10001	20000	40100	10000	20000	13850923	5733628	3467259	1	120031	120053	120055	112143	3	112513	70100	30294	20000	10000	60200	30000	10000	120055	120051	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20000	0	0	0	20000	2	2	0	0	3210	1	16	1	2	119808	50002	14	0	0	20000	50100	120059	120059	120056	120056	120056
60204	122277	933	0	0	1	1	0	0	2	0	0	1	120040	98767	109744	25	80103	50102	10001	20000	40223	10000	20000	13848583	5732666	3465655	1	120031	120051	120051	112144	3	112513	70100	30200	20000	10000	60200	30000	10000	120055	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	2	0	0	3210	1	16	1	1	119828	50013	0	0	13	20000	50100	120056	120036	120056	120052	120056
60204	120057	930	0	0	0	0	0	0	2	0	0	1	120040	98768	109744	25	80103	50113	10001	20000	40100	10000	20000	13848583	5733436	3465626	1	120027	120057	120055	112143	3	112513	70100	30200	20000	10000	60200	30000	10000	120035	120055	2	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	2	0	0	20000	2	2	0	0	3210	1	16	1	1	119828	50002	14	14	13	20000	50100	120057	120056	120036	120057	120056
60204	120055	930	0	0	0	0	0	0	12	0	0	1	120036	98905	109724	25	80100	50100	10001	20000	40100	10000	20000	13856835	5732666	3465156	1	120011	120055	120056	112143	3	112513	70100	30296	20000	10000	60200	30000	10000	120055	120054	1	1	50201	100	99	100	40100	10000	10000	0	100	20006	0	2	20000	0	0	0	20000	2	2	0	0	3210	2	16	1	1	119808	50002	0	10	13	20000	50100	120056	120056	120056	120057	120056
60204	120052	931	0	0	0	0	0	0	14	88	1	0	120020	98767	109740	25	80121	50102	10001	20000	40100	10000	20000	13851483	5733676	3465626	1	120031	120139	120216	112139	3	112515	70100	30200	20000	10000	60200	30000	10000	120136	120056	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	0	20000	2	2	0	0	3210	2	16	1	1	119828	50000	14	0	13	20000	50100	120052	120148	120056	120056	120056
60204	120035	930	1	0	0	0	1	0	0	0	1	1	120240	98671	109832	45	80179	50113	10013	20004	40583	10030	20102	13863997	5737984	3470780	1	120178	120145	120699	113173	14	112693	70509	30298	20254	10031	60968	30093	10127	120186	120258	3	1	50201	100	99	100	40100	10000	10000	0	100	20008	2	2	20004	7	0	4468	20006	2	2	0	0	3253	2	33	1	1	119970	50036	10	10	9	20000	50100	120142	120409	120227	120329	120211

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120048	930	0	0	1	0	0	0	14	0	1	0	0	120032	96476	109736	25	80013	50012	10001	20000	40010	10000	20000	13848323	5733244	3465234	120023	120049	120035	112158	3	112532	70010	30020	20066	10000	60020	30000	10000	120051	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	3	20000	2	2	0	3140	0	5	17	4	4	119822	50000	6	9	9	20000	50010	120048	120048	120053	120048	120050
60024	120047	930	0	0	0	1	0	0	2	0	0	0	0	120036	96476	109736	25	80013	50012	10001	20000	40010	10000	20000	13848668	5733244	3465234	120023	120048	120053	112162	3	112526	70010	30020	20000	10000	60020	30000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	0	2	0	3140	0	4	17	4	4	119822	50002	6	6	5	20000	50010	120048	120048	120052	120052	120052
60024	120035	931	0	0	0	0	0	0	2	0	0	0	0	120034	96483	109736	25	80013	50012	10001	20000	40010	10000	20000	13848323	5733436	3465234	120023	120051	120051	112158	3	112526	70010	30020	20000	10000	60020	30000	10000	120051	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	0	20000	0	2	0	3140	0	5	17	4	4	119826	50002	6	6	10	20000	50010	120053	120048	120036	120052	120048
60024	120050	931	0	0	0	0	0	0	2	0	0	0	0	120032	96477	109740	25	80013	50023	10001	20000	40010	10000	20000	13849761	5733244	3465234	120023	120047	120047	112158	10	112521	70010	30020	20000	10000	60020	30000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	0	20000	2	2	0	3140	0	5	17	4	4	119822	50002	6	6	9	20000	50010	120042	120052	120048	120052	120036
60024	120051	931	0	0	0	0	0	0	134	0	0	0	0	120032	96349	109736	46	80013	50012	10001	20000	40010	10000	20000	13848323	5733244	3465234	120023	120047	120047	112159	3	112526	70010	30020	20000	10000	60020	30000	10000	120047	120137	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	3	20000	2	2	0	3140	0	4	17	4	4	119810	50002	6	10	5	20000	50010	120048	120051	120048	120150	120048
60024	120047	931	0	0	0	0	0	0	2	0	0	0	0	120020	96326	109724	25	80013	50012	10001	20000	40010	10000	20000	13849577	5733244	3465292	120025	120047	120134	112158	3	112526	70010	30020	20000	10000	60076	30000	10000	120047	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	2	2	20000	0	0	3	20000	2	2	0	3140	0	3	17	4	3	119810	50000	6	0	10	20000	50010	120048	120048	120048	120052	120052
60024	120051	931	0	0	0	0	0	0	12	0	0	0	0	120032	96476	109737	25	80013	50012	10001	20000	40010	10000	20000	13854355	5733244	3465234	120094	120051	120035	112159	3	112526	70010	30020	20000	10000	60020	30000	10000	120047	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20078	2	2	0	3140	0	3	17	4	5	119822	50002	10	6	5	20000	50010	120048	120052	120048	120052	120048
60024	120047	931	0	0	1	0	0	0	2	0	0	0	0	120036	96512	109736	25	80013	50012	10001	20000	40010	10000	20000	13848323	5735714	3465234	120023	120048	120047	112158	3	112526	70010	30114	20000	10000	60020	30000	10000	120035	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	2	0	3140	0	4	17	4	4	119823	50002	6	6	0	20000	50010	120048	120048	120048	120048	120048
60024	120140	930	0	0	1	0	0	0	2	0	0	0	0	120036	96476	109736	25	80013	50012	10001	20000	40129	10000	20000	13848323	5733532	3465377	120023	120051	120035	112158	3	112526	70010	30020	20000	10000	60020	30000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	3	20000	2	2	0	3140	0	4	17	4	4	119826	50000	10	6	9	20000	50010	120048	120048	120052	120048	120048
60024	120051	931	0	0	0	0	0	0	125	0	0	0	0	120122	96476	109725	25	80013	50012	10001	20000	40010	10000	20000	13846911	5733244	3465234	120023	120035	120047	112158	3	112526	70010	30020	20000	10000	60020	30000	10000	120125	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	3	20000	0	2	0	3140	0	5	24	4	4	119822	50002	6	6	5	20000	50010	120048	120049	120125	120052	120048

Test 4: throughput

Count: 8

Code:

  ld1 { v0.4s, v1.4s }, [x6], x8
  ld1 { v0.4s, v1.4s }, [x6], x8
  ld1 { v0.4s, v1.4s }, [x6], x8
  ld1 { v0.4s, v1.4s }, [x6], x8
  ld1 { v0.4s, v1.4s }, [x6], x8
  ld1 { v0.4s, v1.4s }, [x6], x8
  ld1 { v0.4s, v1.4s }, [x6], x8
  ld1 { v0.4s, v1.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80041	620	0	0	0	0	0	0	0	0	30	0	0	0	0	80025	2	12	12	54	25	240100	80100	160000	80100	160000	2006800	3675954	0	80015	80040	80040	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	42	160023	0	0	32	160024	6	1	24	27	0	0	5110	2	16	2	2	80037	1	80000	6	6	160000	80100	80041	80041	80041	80042	80041
160204	80040	620	0	0	0	0	1	1	0	0	29	0	0	0	0	80026	2	12	12	96	25	240100	80100	160000	80100	160000	2033463	3669333	0	80015	80040	80040	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	27	160024	0	0	0	160032	6	1	24	0	0	0	5110	3	16	2	3	80037	1	80000	10	6	160000	80100	80042	80041	80041	80041	80041
160204	80040	621	0	0	0	0	1	0	0	0	29	0	0	0	0	80025	2	12	12	145	25	240100	80100	160000	80100	160000	2040110	3669892	0	80015	80040	80040	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	27	160023	0	0	32	160026	6	1	23	27	0	0	5110	2	16	3	3	80037	0	80000	10	10	160000	80100	80041	80041	80041	80041	80041
160204	80040	620	0	0	0	0	0	0	0	0	30	0	0	0	0	80025	2	12	12	148	25	240100	80100	160000	80100	160000	2019482	3672652	0	80015	80041	80043	59954	3	59998	240100	200	160000	200	240000	80040	80042	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	42	160031	0	0	36	160032	6	1	31	37	0	0	5110	2	16	4	3	80037	1	80000	14	10	160000	80100	80041	80041	80044	80044	80043
160204	80043	620	1	0	1	1	1	0	0	0	70	0	0	0	2	80029	3	6	6	122	25	240100	80100	160000	80100	160000	2012923	3666126	0	80017	80042	80042	59955	3	60001	240100	200	160000	200	240000	80042	80043	1	1	80201	100	99	0	100	100	80000	80000	0	100	160013	12	43	160051	0	0	52	160039	6	1	51	43	13	1	5110	3	16	3	2	80039	0	80000	13	13	160000	80100	80046	80043	80044	80045	80043
160204	80042	620	1	1	0	1	0	0	0	0	58	0	0	0	2	80027	2	6	6	140	25	240100	80100	160000	80100	160000	1986393	3666133	0	80018	80040	80040	59956	3	60004	240100	200	160000	200	240000	80042	80042	1	1	80201	100	99	0	100	100	80000	80000	0	100	160012	13	42	160052	0	0	51	160038	6	1	52	43	12	0	5110	3	16	2	2	80039	0	80000	13	14	160000	80100	80045	80045	80044	80043	80043
160204	80042	620	1	1	0	0	0	0	0	0	58	108	0	0	2	80027	3	6	6	43	25	240100	80100	160000	80100	160000	1996353	3666180	0	80017	80042	80043	59956	3	60001	240100	200	160000	200	240000	80042	80042	1	1	80201	100	99	0	100	100	80000	80000	0	100	160014	12	43	160051	0	1	52	160039	6	1	52	0	13	0	5110	2	16	3	3	80040	0	80000	13	13	160000	80100	80044	80043	80045	80043	80044
160204	80043	620	1	1	0	1	0	0	0	0	87	0	0	0	2	80028	2	6	6	29	25	240100	80100	160000	80100	160000	2012974	3670735	0	80017	80043	80042	59956	3	60000	240100	200	160000	200	240000	80043	80046	1	1	80201	100	99	0	100	100	80000	80000	0	100	160012	13	43	160052	0	0	52	160039	6	1	52	43	12	0	5110	2	16	3	2	80039	0	80000	13	13	160000	80100	80043	80044	80044	80045	80043
160204	80045	620	1	1	1	1	0	0	0	0	79	0	0	1	2	80028	2	6	6	99	25	240100	80100	160000	80100	160000	2012923	3662807	0	80017	80043	80047	59955	3	60001	240100	200	160000	200	240000	80042	80042	1	1	80201	100	99	0	100	100	80000	80000	0	100	160014	14	42	160052	1	0	51	160039	6	1	52	42	13	1	5110	2	16	2	3	80040	0	80000	13	13	160000	80100	80043	80042	80044	80045	80045
160204	80043	620	1	1	1	0	0	0	0	0	58	0	0	0	2	80032	3	6	6	31	25	240100	80100	160000	80100	160000	1996892	3656146	0	80017	80042	80042	59955	3	60000	240100	200	160000	200	240000	80042	80043	1	1	80201	100	99	0	100	100	80000	80000	0	100	160014	13	43	160052	0	1	55	160039	6	1	52	43	13	1	5110	2	16	2	2	80039	0	80000	13	13	160000	80100	80044	80043	80043	80043	80044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	18	19	1e	1f	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80157	621	0	0	0	0	0	0	42	0	2	80025	2	0	12	20	25	240010	80010	160000	80010	160000	2024570	3669355	1	0	80015	0	80041	80040	59976	3	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160038	1	0	35	163058	6	1	32	40	0	0	5020	0	0	0	10	16	10	8	80037	0	80000	14	10	160000	80010	80041	80041	80159	80041	80041
160024	80040	620	0	0	0	1	0	0	44	0	2	80025	2	0	12	16	25	240010	80010	160000	80010	160000	2032451	3669355	0	0	80015	0	80040	80041	59975	3	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160036	0	0	35	160036	6	1	36	35	0	0	5020	0	0	0	8	16	9	9	80037	0	80000	14	10	160000	80010	80041	80041	80041	80041	80041
160024	80040	621	0	0	0	0	0	0	42	0	2	80025	0	12	12	16	25	240010	80010	160000	80010	160000	2024570	3656164	0	0	80015	0	80120	80040	59975	3	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	40	0	160036	0	0	32	160036	6	1	31	40	0	0	5020	0	0	0	10	16	8	12	80040	1	80000	14	10	160000	80010	80041	80043	80041	80041	80041
160024	80040	620	0	0	0	0	2	2	42	0	0	80027	2	12	12	19	25	240010	80072	160000	80010	160000	2001884	3672685	0	0	80015	0	80040	80040	59975	3	60020	240010	20	160000	20	240000	80155	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160038	0	0	34	160036	6	1	32	40	0	0	5020	0	4	0	10	16	8	9	80037	0	80000	14	14	160000	80010	80041	80041	80041	80042	80041
160024	80040	620	0	0	0	0	0	0	42	0	0	80025	2	12	12	16	25	240010	80010	160000	80010	160000	2024570	3680982	0	0	80015	0	80040	80040	59976	3	60020	240010	20	160000	20	240000	80041	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160036	0	0	32	160036	6	1	32	0	0	0	5020	0	0	0	10	16	8	12	80037	0	80000	14	14	160000	80010	80041	80041	80041	80041	80041
160024	80040	620	0	0	0	0	0	0	42	0	2	80025	2	12	12	17	25	240010	80010	160000	80010	160000	2031163	3669355	0	0	80015	0	80040	80040	59976	3	60020	240261	20	160000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160038	0	0	39	160036	6	1	0	40	0	0	5020	0	0	0	10	16	10	9	80037	0	80000	14	14	160000	80010	80043	80041	80041	80041	80041
160024	80040	621	0	0	0	0	0	0	42	0	2	80025	2	12	12	16	25	240010	80010	160000	80010	160000	2039153	3672662	0	0	80015	0	80157	80040	59975	3	60020	240010	20	160000	20	240000	80040	80040	2	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160036	0	0	0	160032	0	1	36	40	0	0	5020	0	0	0	9	16	10	11	80037	0	80000	14	14	160000	80010	80041	80041	80041	80041	80041
160024	80040	621	0	0	0	0	0	0	42	0	2	80025	2	12	12	16	25	240010	80010	160000	80010	160000	2024570	3669355	0	0	80015	0	80040	80040	59975	3	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160036	1	0	36	160000	6	1	31	40	0	0	5020	0	0	0	9	15	12	9	80037	0	80000	14	10	160000	80010	80041	80041	80041	80041	80041
160024	80157	620	0	0	0	0	0	0	38	0	0	80025	2	12	12	11	25	240010	80010	160000	80010	160000	2039665	3672662	0	0	80015	0	80040	80040	59975	3	60022	240258	20	160000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160036	0	0	36	160036	6	1	38	40	0	0	5020	5	4	0	9	25	10	9	80037	0	80000	14	10	160000	80010	80041	80042	80041	80041	80041
160024	80040	620	0	0	0	0	0	0	176	0	2	80025	2	12	12	16	25	240010	80010	160000	80010	160000	2011220	3659350	1	0	80016	0	80040	80040	59976	3	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	35	0	160036	0	0	851	160038	6	1	32	35	0	0	5020	0	0	0	8	16	10	10	80037	0	80000	14	10	160000	80010	80042	80041	80041	80041	80041

LD1 (multiple, post-index, 2 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations