Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 2 regs, 8B)

Test 1: uops

Code:

  ld1 { v0.8b, v1.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22243a3f43464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)dfe0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6200528709223201200100200046582834500123807200010001000100010005000500111001604328234287443102000200030002860828666116100110001000010000210011011003010013355974369833207058200413195381721596322813810001536613129144861000100010002878628715287372883828689
6200428694222100100000240004820283010112378120001000100010001000500050007081604628270286173102000200030002861928619116100110001000010000210012011001113013342954270033186164200463236381924536022813510001584412974142771000100010002870928606287752864728653
620042875022100010000020004749283380112366120001000100010001000500050005061603928189285013102000200030002852928609116100110001000010000210001011001112013465938869273187057200453130381823676022815710001563512960142171000100010002874628730287982874328795
620042866022220020000000004730283570102368720001000100010001000500050007081605628224286903102000200030002852228468116100110001000010000210012031000133013319937369613269062200073163382419595622813910001542312694141221000100010002879528709286192870728690
6200428638222000200000200046782842401023627200010001000100010005000500012081606128163286933102000200030002861228595116100110001000010000210030011001112013252968269333203060200033204382211646022816510001534012932143241000100010002865728727286522876128625
6200428632223200200000400047972825300123648200410001000100010005000500012101603328168286453102000200230002854128510116100110001000010000210033011001013013280945969603165162201373198381419535622808110001528713121140691000100010002869728636286392868828717
6200428619223100200000401046812832601023634200010001000100010005000500413001603328185285603102000200030002853728614116100110001000010030210010011001112013239961269573190160199253149382524625622808010001555612856140761000100010002878828593286512863828648
6200428738222200200000400047012829900123647200010001000100010005000500212081602828195285893102000200030002848828592116100110001000010000310010011001212013165963770233233054200213256381620556522806710001536912765143271000100010002858628657286202858528602
6200428743222200200000200047232839501123610200010001000100010005000500012001600328171285803102000200030002850228579116100110001000010000210010011001112013223920769283235058199083166382722616632812010001544412851142671000100010002863828853286312869628842
62004286902231012000001600048392830801123728200010001000100010005000500016101603028248286893102000200030002856928627116100110001000110000210011011003212012992955070553204055200833144382217516222804110001526312894141811000100010002864928725287432869928795

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b, v1.8b }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0056

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4c4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6020512005493110000000140100112003801197172570103501041000210000401001000010000106221245461974574699120029012004112005611204019112582601003020020000100006020030000100001200571200851150201100991004010010000100000100100011110001101100001111032101831111975250002968100001000050100120042120042120057120057120054
602041200439301000110014000001200260119639257010650104100021000040100100001000010619144546236457469912001701200561200561120463112432601003020020000100006020030000100001200411200531150201100991004010010000100000100100011110001101100001011032101831111975950000968100001000050100120057120057120057120057120057
602041200569311000000010000012004101197172570103501141000210000401001000010000106179545444744574699120017312005612005611204613112447601003020020000100006020030000100001200561200531150201100991004010010000100000100100022110000011100001111032101831111975950004968100001000050100120057120042120042120058120042
60204120056931101100002001001200260119717257010650102100021000040100100001000010622574546159457469912002901200561200351120463112447601003020020000100006020030000100401200591200541150201100991004010010000100001100100023110002001100000111032103831111975950004065100001000050100120140120057120042120057120036
602041200419301110000014000001200410119641257010350117100021000040100100001000010623384548667457339012002901200411200411120423112447601003020020000100006020030000100001200411200531150201100991004010010000100001100100021010002004100000111032101831111975950004060100001000050100120051120057120054120042120057
60204120047930100001002000001200200119720257010350114100021000040100100001000010622394546159457469912003201200561200561120443112447601003020020000100006020030000100001200411200531150201100991004010010000100000100100022110043001100001111032101831111975950004968100001000050100120042120042120042120057120151
602041200539311001000028800001200320119717527010650104100011000040100100001000010617954544474457339012003201200421200561120483112447601003020020000100006020030000100001200561200532150201100991004010010000100000100100021110001101100001101132101831211975950002065100001000050100120057120057120057120137120060
60204120041931111010002000001200260119639257010650104100021000040100100001000010617954546159457450312003301200471200561120463112447601003032120000100006020030000100001200561200541150201100991004010010000100000100100010010000011100001110032351831111976150004968100001000050100120051120057120057120057120057
602041200569311100000014001001200410119640257010350102100041000040100100001000010617954544474457339012001701200561200561120433112489601003020020000100006020030000100001200561200541150201100991004010010000100000100100011010002111100000111132101831111975450004668100001000050100120048120057120057120036120057
60204120059964100011004000001200260119683257010650102100011000040100100001000010622394546159457339012003201200561200541120423112435601003020020000100006044230000100001200411200411150201100991004010010000100000100100014110001002764100000111032103831111983850002960100001000050100120499120240120145120146120195

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60025120047930000100100013000012003211970125700135001210001100004001010000100001062200454857645778230120011120051120047112057311247160010300202000010000600203000010000120035120035115002110910400101000010000010100000110000000100001010003529127811911983750000965100001000050010120036120036120048120115120051
600241201399310000000000000001200201197012570013500121000110000400101000010039106222845485764577862012008312005012003511207231124536001030020200001000060020300001000012005012004711500211091040010100001000001010000011000010285510000101000316511781010119834500021068100001000050010120051120051120042120109120057
60024120137931100000000059000012004111970625700135001210001100004015210000100001062228454799245778230120023120035120051112072311245360010300202000010000600203000010000120047120050115002110910400101000010000010100000110000130100001010003140978121211975950004008100001000050010120057120051120051120117120126
60024120050930100001000070000120038119701257002750012100011000040010100001000010622824548296457827401200321200501200471120693112474600103002020000100006002030000100001200501200471150021109104001010000100000101000111100030101000001110031401177111211976750014990100001000050010120042120057120042120118120036
60024120056930001000000020000120032119704257001650010100001000040010100001000010622284548804457842601200111200351200351120933112460600103002020000100006002030000100411200561200471150021109104001010000100000101000111100010011000011110031401078101111976550002060100001000050010120130120042120057120112120054
60024120056931002000010020000120035119710257001650014100011000040010100001000010622824548031457805701200181200531200351120993112453600103002020000100006002030120100001200561200551150021109104001010000100000101000011100000011000201110031409102109119801500029128100001000050010120036120039120058120145120057
60024120056931000000000010000120035119710257001650024100011000040010100001000010622554548576457782301200171200571200471120723112466600103002020000100006002030000100001200531200561150021109104001010000100000101000001100000001000010000031401078101111975950002695100001000050010120051120147120051120316120057
6002412005093100000000001300001200351197102570013500141000210000400101000010000106228245488044578057012003212005612005711210731124686001030020200001000060020300001004012004912004311500211091040010100001000001010000011000011010000011000314010781011119759500021098100001000050010120136120051120053120048120057
6002412005093110000100001001112004111970425700135001210002100004001010000100401062200454880445780570120027120035120056112078311247460232300202000010000600203000010000120053120050115002110910400101000010000010100010110001101100001110003140117891011976550002960100001000050010120057120043120052120099120051
6002412005093010000000002000012004111971025700135001210001100004001010000100001062228454857645780570120027120056120050112078311246060010301682000010000602683000010000120047120050115002110910400101000010000010100011110001004100011111003140978111111976550002698100001000050010120057120057120057120048120042

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b, v1.8b }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22233a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
6020512005393010000130002501001200261196452570103501041000110000401001000010000106179545444744574582120032012005612005611211331124326010030200200001000060200300001000012005612004111502011009910040100100001000001001000321100010101041000001100032101831111975250004968100001000050100120042120057120057120051120135
6020412005693110000011002001012002611963925701035010410002100004010010000100001061914454615945748161200320120059120056112026311243260100302002000010000602003000010000120053120053115020110099100401001000010000010010002101000200141000011110032101831111975950002968100001000050100120042120057120057120057120108
60204120053931101001100020010120043119717257010650104100021000040100100001000010622394546159457469912003201200561200561120463112447601003020020000100006020030000100001200561200531150201100991004010010000100000100100021110002091011000001110032101831111975950004968100001000050100120057120057120057120058120094
60204120056930101100000011000012003511963925701065010410002100004010010000100001062239454615945746991200320120035120056112046311244760100302002000010000602003000010000120047120053115020110099100401001000010000010010002201000100211000011010032101831111976250002998100001000050100120057120057120057120057120107
6020412005393110000110002001012004111971725701065010410002100004010010000100001062239454615945747381200320120056120050112047311244760100302002000010000602003000010000120053120053115020110099100401001000010000010010001211000100041000011100032101831111975250004998100001000050100120057120057120057120057120099
60204120041931100000000014000112003811963925701065010410002100004010010000100001061795454615945760601200320120053120056112046311245060100302002000010000602003000010000120056120053115020110099100401001000010000010010001111000100101000011110032101831111975950002998100001000050100120051120057120045120057120131
6020412004193110000100002000112004111963925701065010410002100004010010000100001062239454615945745041200330120050120053112026311244760100302002000010040602003000010000120041120035115020110099100401001000010000010010002111000100028171000011110032101831111986750004968100001000050100120057120057120146120056120054
60204120053931111101100080000120041119633257010650116100021000040100100001000010622394546159457350712001701200561200411120463112441601003020020000100006020030000100411200561200531150201100991004010010000100001100100022110000095041000011010032101831111991750033968100001000050100120155120150120246120333120267
6020412022993210000200223982640101202241197297770136501381000410006403861007810078106659045492874578279120236012025712033211216347112545605443032520164100406069630120100811202391202253150201100991004010010000100000100100101110001098041000001110032101831111975250004990100001000050100120042120057120057120057120110
6020412005693010110000001900001201381196392570106501041000210000401001000010000106179545444744574699120033012005612005611204631124476010030200200001000060200300001000012005912004111502011009910040100100001000001001000121100010101111000011010032101831111991550004968100001000050100120057120054120057120058120054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0054

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f2223243f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
60025120051930000011001010012003911970825700135001210001100004001010000100001064347454861445779790012003012005412005411207331124696001030020200001000060020300001000012005112005111500211091040010100001000011010000011000010010000110031660410436119907500121309100001000050010120244120052120144120052120052
600241201439310101112313317610012031311972549700415003110007100044029610080100781067640455230445840980012017712013812043111222323112642606753014420160100426050830363100811203301202153150021109104001010000100000101000501100029084251000411003140061125411976350002101012100001000050010120052120052120052120052120055
600241200519310000010010100120039119705257001350012100011000040010100001000010622644548614457797900120030120054120057112073311247260010300202000010000600203000010000120054120051115002110910400101000010000110100000110000703100001100314004783211976050002131312100001000050010120052120052120053120058120056
60024120055930000001001001012003811970825700135001210001100004001010000100001062300454865245779790012003012005112005611207831124696001030020200001000060020300001000012005412005111500211091040010100001000001010000011000000010000110031400378431197605000210109100001000050010120055120055120054120052120053
600241200519310000110010010120036119705257001350012100011000040010100001000010622644548614457797900120027120054120054112076311247260010300202000010000600203000010000120054120051115002110910400101000010000010100000110000003100001100314003783411976050002101012100001000050010120057120055120055120056120052
60024120054930000011001000012003611970625700135001210001100004001010000100001062264454861445780180012003012005412005411207331124746001030020200001000060020300001000012005412005511500211091040010100001000011010000011000000010000110031400478431197635000213109100001000050010120055120052120052120052120055
600241200519310000010010010120039119708257001350012100011000040010100001000010622644548804457797900120030120051120051112076311247260010300202000010000600203000010000120054120051115002110910400101000010000010100000110000000100001100314005784411976350002101012100001000050010120055120055120052120052120053
600241200519310000110013001012003611970825700135001210001100004016210000100001062264454872845779790012002712005712005111207631124746001030020200001000060020300001000012005112005111500211091040010100001000001010000011000000610000110031400378341197635000213109100001000050010120055120055120052120052120055
600241200519310000010010010120039119707257001350012100011000040010100001000010622644548728457797900120030120054120057112076311247260010300202000010000600203000010000120051120051115002110910400101000010000010100000110000000100001100314003785311976650002131012100001000050010120055120055120052120052120055
600241200519310000110010010120036119705257001350012100011000040010100001000010622374548728457797900120030120051120051112076311247260010300202000010000600203000010000120051120051115002110910400101000010000110100000110000000100001100314004783411976350002101012100001000050010120055120055120055120055120052

Test 4: throughput

Count: 8

Code:

  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f23243f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160205800406200000000220008002510652516010080100800008010080000435901037588240800158004080040599243599981601002001600002002400008004080040218020110099100100800008000001008004501480058007638005661130051381251280077180000998000080000801008009680096800968009580096
1602048009462110000122838800800790664899160152801278002580252800694359002376100908001580147800965993618600251602452021603042002402258009580095318020110099100100800008000001008004421480060007578003561917251391341180037180000968000080000801008004180041800418004180041
160204800406200000000190008002516692516010080100800008010080000435900237588240800158004080040599243599981601002001600002002400008004080040118020110099100100800008000001008000001480012101680010611017051101161180037180000968000080000801008004180041800418004180041
16020480040620000000018000800251664251601008010080000801008000043590023758824080015800408004059924359998160100200160000200240000800408004011802011009910010080000800000100800000148001300118001261017051101161180037180000948000080000801008004180041800418004180041
1602048004062000001001800080025168125160100801008000080100800004358982375882408001580040800405992435999816010020016000020024000080040800401180201100991001008000080000010080000008001000138001361017051101161180037180000968000080000801008004180041800418004180041
16020480040620000000019000800251664251601528010080000801008000043590063758824080015800408004059924359998160100200160000200240000800408004011802011009910010080000800000100800000148001300108001061917051101161180037180000968000080000801008004180041800418004180041
16020480040621000000019000800251665251601008010080000801008000043590023758824080015800408004059924359998160100200160000200240000800408004011802011009910010080000800000100800000148001310108001561017051101161180037080000068000080000801008004180041800418004180041
16020480040620000000016000800251664251601008010080000801008000043590023758824080015800408004059924359998160100200160000200240000800408004011802011009910010080000800000100800000148001200128001561017051101161180037180000998000080000801008004180041800418004180041
16020480040620000100016000800251665251601008010080000801008000043590023758824080015800408004059924359998160100200160000200240000800408004011802011009910010080000800000100800000178001310138001060017051101162280037180000668000080000801008004180041800418004180041
1602048004062100000001800080025166025160100801008000080100800004359006375882408001580040800405992435999816010020016000020024000080040800401180201100991001008000080000010080000008001300080000001017051101161280037180000998000080000801008004180041800418004180041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f1e223a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600258004060010001360080025066102516001080010800008001080000435835737588180080015080040800405994636002016001020160000202400008004080040118002110910108000080000010800077278003094036800006130277050200031633800371800001308000080000800108004180041800418004180041
16002480040599100003600800251661025160010800108000080314800004358377375882000800150800408004059946106009916001020160152202400008004080040118002110910108000080000110800088278003097029800236129277150200031633800371800000138000080000800108004180041800418004180041
16002480040599111006008002516612516001080010800008001080000435838137588200080015080040800405994636002016001020160000202400008004080040118002110910108000080000010800077278002901398002260292770502000216338003718000013138000080000800108004180041800418004180041
160024800405991010070180025106102516001080010800008001080000435838937588240080015080040800405994636002016001020160000202400008004080040118002110910108000080000010800066278003001328000061292770502000316348003718000013138000080000800108004180041800418004180041
1600248004059911100360180025060102516001080010800008001080000435842937588200080015080040800405994636002016001020160000202400008004080040118002110910108000080000010800087278003101358002361292770502000316328003708000013138000080000800108004180041800418004180041
1600248004059910000360080025166102516001080010800008001080000435837737588200080015080040800405994636002016001020160000202400008004080040118002110910108000080000010800077278003000328002361302770502000316338003718000013138000080000800108004180041800418004180041
16002480040599100003500800251661025160010800108007580010800004358373375882300800150800408004059946360020160010201600002024000080040800401180021109101080000800000108000662780030971308002361292760502000316448003708000013138000080000800108004180041800418004180041
160024800405991100035018002516622516001080010800008001080000435838137588200080015080040800405994636002016001020160000202400008004080040118002110910108000080000010800088278003101358002261302772502000216438003718000013138000080000800108004180041800418004180041
1600248004060011100360080025166102516001080010800008001080000435838937588250080015080040800405994636002016001020160000202400008004080040118002110910108000080000010800089278003100328002361292771502000316338003718000013138000080000800108004180041800418004180041
1600248004059910011360080025166102516001080010800008001080000435837737588200080015080040800405994636002016001020160000202400008004080040118002110910108000080000010800086278002901328002361302770502000316328003708000013138000080000800108004180041800418004180041