Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1 { v0.8b, v1.8b }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.000
Integer unit issues: 1.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | df | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
62005 | 28709 | 223 | 2 | 0 | 1 | 2 | 0 | 0 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | 4658 | 28345 | 0 | 0 | 1 | 23807 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5001 | 11 | 0 | 0 | 16043 | 28234 | 28744 | 3 | 10 | 2000 | 2000 | 3000 | 28608 | 28666 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1001 | 1 | 0 | 1 | 1003 | 0 | 1 | 0 | 0 | 13355 | 9743 | 6983 | 3207 | 0 | 58 | 20041 | 3195 | 3817 | 21 | 59 | 63 | 2 | 28138 | 1000 | 15366 | 13129 | 14486 | 1000 | 1000 | 1000 | 28786 | 28715 | 28737 | 28838 | 28689 |
62004 | 28694 | 222 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | 4820 | 28301 | 0 | 1 | 1 | 23781 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5000 | 7 | 0 | 8 | 16046 | 28270 | 28617 | 3 | 10 | 2000 | 2000 | 3000 | 28619 | 28619 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1001 | 2 | 0 | 1 | 1001 | 1 | 1 | 3 | 0 | 13342 | 9542 | 7003 | 3186 | 1 | 64 | 20046 | 3236 | 3819 | 24 | 53 | 60 | 2 | 28135 | 1000 | 15844 | 12974 | 14277 | 1000 | 1000 | 1000 | 28709 | 28606 | 28775 | 28647 | 28653 |
62004 | 28750 | 221 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 4749 | 28338 | 0 | 1 | 1 | 23661 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5000 | 5 | 0 | 6 | 16039 | 28189 | 28501 | 3 | 10 | 2000 | 2000 | 3000 | 28529 | 28609 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1000 | 1 | 0 | 1 | 1001 | 1 | 1 | 2 | 0 | 13465 | 9388 | 6927 | 3187 | 0 | 57 | 20045 | 3130 | 3818 | 23 | 67 | 60 | 2 | 28157 | 1000 | 15635 | 12960 | 14217 | 1000 | 1000 | 1000 | 28746 | 28730 | 28798 | 28743 | 28795 |
62004 | 28660 | 222 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4730 | 28357 | 0 | 1 | 0 | 23687 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5000 | 7 | 0 | 8 | 16056 | 28224 | 28690 | 3 | 10 | 2000 | 2000 | 3000 | 28522 | 28468 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1001 | 2 | 0 | 3 | 1000 | 1 | 3 | 3 | 0 | 13319 | 9373 | 6961 | 3269 | 0 | 62 | 20007 | 3163 | 3824 | 19 | 59 | 56 | 2 | 28139 | 1000 | 15423 | 12694 | 14122 | 1000 | 1000 | 1000 | 28795 | 28709 | 28619 | 28707 | 28690 |
62004 | 28638 | 222 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 4678 | 28424 | 0 | 1 | 0 | 23627 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5000 | 12 | 0 | 8 | 16061 | 28163 | 28693 | 3 | 10 | 2000 | 2000 | 3000 | 28612 | 28595 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1003 | 0 | 0 | 1 | 1001 | 1 | 1 | 2 | 0 | 13252 | 9682 | 6933 | 3203 | 0 | 60 | 20003 | 3204 | 3822 | 11 | 64 | 60 | 2 | 28165 | 1000 | 15340 | 12932 | 14324 | 1000 | 1000 | 1000 | 28657 | 28727 | 28652 | 28761 | 28625 |
62004 | 28632 | 223 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 4797 | 28253 | 0 | 0 | 1 | 23648 | 2004 | 1000 | 1000 | 1000 | 1000 | 5000 | 5000 | 12 | 1 | 0 | 16033 | 28168 | 28645 | 3 | 10 | 2000 | 2002 | 3000 | 28541 | 28510 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1003 | 3 | 0 | 1 | 1001 | 0 | 1 | 3 | 0 | 13280 | 9459 | 6960 | 3165 | 1 | 62 | 20137 | 3198 | 3814 | 19 | 53 | 56 | 2 | 28081 | 1000 | 15287 | 13121 | 14069 | 1000 | 1000 | 1000 | 28697 | 28636 | 28639 | 28688 | 28717 |
62004 | 28619 | 223 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 4681 | 28326 | 0 | 1 | 0 | 23634 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5004 | 13 | 0 | 0 | 16033 | 28185 | 28560 | 3 | 10 | 2000 | 2000 | 3000 | 28537 | 28614 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1003 | 0 | 2 | 1001 | 0 | 0 | 1 | 1001 | 1 | 1 | 2 | 0 | 13239 | 9612 | 6957 | 3190 | 1 | 60 | 19925 | 3149 | 3825 | 24 | 62 | 56 | 2 | 28080 | 1000 | 15556 | 12856 | 14076 | 1000 | 1000 | 1000 | 28788 | 28593 | 28651 | 28638 | 28648 |
62004 | 28738 | 222 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 4701 | 28299 | 0 | 0 | 1 | 23647 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5002 | 12 | 0 | 8 | 16028 | 28195 | 28589 | 3 | 10 | 2000 | 2000 | 3000 | 28488 | 28592 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 3 | 1001 | 0 | 0 | 1 | 1001 | 2 | 1 | 2 | 0 | 13165 | 9637 | 7023 | 3233 | 0 | 54 | 20021 | 3256 | 3816 | 20 | 55 | 65 | 2 | 28067 | 1000 | 15369 | 12765 | 14327 | 1000 | 1000 | 1000 | 28586 | 28657 | 28620 | 28585 | 28602 |
62004 | 28743 | 222 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 4723 | 28395 | 0 | 1 | 1 | 23610 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5000 | 12 | 0 | 0 | 16003 | 28171 | 28580 | 3 | 10 | 2000 | 2000 | 3000 | 28502 | 28579 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 2 | 1001 | 0 | 0 | 1 | 1001 | 1 | 1 | 2 | 0 | 13223 | 9207 | 6928 | 3235 | 0 | 58 | 19908 | 3166 | 3827 | 22 | 61 | 66 | 3 | 28120 | 1000 | 15444 | 12851 | 14267 | 1000 | 1000 | 1000 | 28638 | 28853 | 28631 | 28696 | 28842 |
62004 | 28690 | 223 | 1 | 0 | 1 | 2 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 4839 | 28308 | 0 | 1 | 1 | 23728 | 2000 | 1000 | 1000 | 1000 | 1000 | 5000 | 5000 | 16 | 1 | 0 | 16030 | 28248 | 28689 | 3 | 10 | 2000 | 2000 | 3000 | 28569 | 28627 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 0 | 2 | 1001 | 1 | 0 | 1 | 1003 | 2 | 1 | 2 | 0 | 12992 | 9550 | 7055 | 3204 | 0 | 55 | 20083 | 3144 | 3822 | 17 | 51 | 62 | 2 | 28041 | 1000 | 15263 | 12894 | 14181 | 1000 | 1000 | 1000 | 28649 | 28725 | 28743 | 28699 | 28795 |
Chain cycles: 3
Code:
ld1 { v0.8b, v1.8b }, [x6], x8 fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0056
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 3a | 3f | 4c | 4d | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60205 | 120054 | 931 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 1 | 0 | 0 | 1 | 120038 | 0 | 119717 | 25 | 70103 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062212 | 4546197 | 4574699 | 120029 | 0 | 120041 | 120056 | 112040 | 19 | 112582 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120057 | 120085 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 1 | 1 | 10001 | 1 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 3210 | 1 | 83 | 1 | 1 | 119752 | 50002 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120042 | 120042 | 120057 | 120057 | 120054 |
60204 | 120043 | 930 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 120026 | 0 | 119639 | 25 | 70106 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1061914 | 4546236 | 4574699 | 120017 | 0 | 120056 | 120056 | 112046 | 3 | 112432 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120041 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 1 | 1 | 10001 | 1 | 0 | 1 | 10000 | 1 | 0 | 1 | 1 | 0 | 3210 | 1 | 83 | 1 | 1 | 119759 | 50000 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120057 | 120057 | 120057 | 120057 | 120057 |
60204 | 120056 | 931 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 120041 | 0 | 119717 | 25 | 70103 | 50114 | 10002 | 10000 | 40100 | 10000 | 10000 | 1061795 | 4544474 | 4574699 | 120017 | 3 | 120056 | 120056 | 112046 | 13 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120056 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10002 | 2 | 1 | 10000 | 0 | 1 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 3210 | 1 | 83 | 1 | 1 | 119759 | 50004 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120057 | 120042 | 120042 | 120058 | 120042 |
60204 | 120056 | 931 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 1 | 0 | 0 | 120026 | 0 | 119717 | 25 | 70106 | 50102 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062257 | 4546159 | 4574699 | 120029 | 0 | 120056 | 120035 | 112046 | 3 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10040 | 120059 | 120054 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10002 | 3 | 1 | 10002 | 0 | 0 | 1 | 10000 | 0 | 1 | 1 | 1 | 0 | 3210 | 3 | 83 | 1 | 1 | 119759 | 50004 | 0 | 6 | 5 | 10000 | 10000 | 50100 | 120140 | 120057 | 120042 | 120057 | 120036 |
60204 | 120041 | 930 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 120041 | 0 | 119641 | 25 | 70103 | 50117 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062338 | 4548667 | 4573390 | 120029 | 0 | 120041 | 120041 | 112042 | 3 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120041 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10002 | 1 | 0 | 10002 | 0 | 0 | 4 | 10000 | 0 | 1 | 1 | 1 | 0 | 3210 | 1 | 83 | 1 | 1 | 119759 | 50004 | 0 | 6 | 0 | 10000 | 10000 | 50100 | 120051 | 120057 | 120054 | 120042 | 120057 |
60204 | 120047 | 930 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 120020 | 0 | 119720 | 25 | 70103 | 50114 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062239 | 4546159 | 4574699 | 120032 | 0 | 120056 | 120056 | 112044 | 3 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120041 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10002 | 2 | 1 | 10043 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 3210 | 1 | 83 | 1 | 1 | 119759 | 50004 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120042 | 120042 | 120042 | 120057 | 120151 |
60204 | 120053 | 931 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 88 | 0 | 0 | 0 | 0 | 120032 | 0 | 119717 | 52 | 70106 | 50104 | 10001 | 10000 | 40100 | 10000 | 10000 | 1061795 | 4544474 | 4573390 | 120032 | 0 | 120042 | 120056 | 112048 | 3 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120056 | 120053 | 2 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10002 | 1 | 1 | 10001 | 1 | 0 | 1 | 10000 | 1 | 1 | 0 | 1 | 1 | 3210 | 1 | 83 | 1 | 2 | 119759 | 50002 | 0 | 6 | 5 | 10000 | 10000 | 50100 | 120057 | 120057 | 120057 | 120137 | 120060 |
60204 | 120041 | 931 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 120026 | 0 | 119639 | 25 | 70106 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1061795 | 4546159 | 4574503 | 120033 | 0 | 120047 | 120056 | 112046 | 3 | 112447 | 60100 | 30321 | 20000 | 10000 | 60200 | 30000 | 10000 | 120056 | 120054 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 0 | 0 | 10000 | 0 | 1 | 1 | 10000 | 1 | 1 | 1 | 0 | 0 | 3235 | 1 | 83 | 1 | 1 | 119761 | 50004 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120051 | 120057 | 120057 | 120057 | 120057 |
60204 | 120056 | 931 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 1 | 0 | 0 | 120041 | 0 | 119640 | 25 | 70103 | 50102 | 10004 | 10000 | 40100 | 10000 | 10000 | 1061795 | 4544474 | 4573390 | 120017 | 0 | 120056 | 120056 | 112043 | 3 | 112489 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120056 | 120054 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 1 | 0 | 10002 | 1 | 1 | 1 | 10000 | 0 | 1 | 1 | 1 | 1 | 3210 | 1 | 83 | 1 | 1 | 119754 | 50004 | 6 | 6 | 8 | 10000 | 10000 | 50100 | 120048 | 120057 | 120057 | 120036 | 120057 |
60204 | 120059 | 964 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 120026 | 0 | 119683 | 25 | 70106 | 50102 | 10001 | 10000 | 40100 | 10000 | 10000 | 1062239 | 4546159 | 4573390 | 120032 | 0 | 120056 | 120054 | 112042 | 3 | 112435 | 60100 | 30200 | 20000 | 10000 | 60442 | 30000 | 10000 | 120041 | 120041 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 4 | 1 | 10001 | 0 | 0 | 2764 | 10000 | 0 | 1 | 1 | 1 | 0 | 3210 | 3 | 83 | 1 | 1 | 119838 | 50002 | 9 | 6 | 0 | 10000 | 10000 | 50100 | 120499 | 120240 | 120145 | 120146 | 120195 |
Result (median cycles for code, minus 3 chain cycles): 9.0054
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60025 | 120047 | 930 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 13 | 0 | 0 | 0 | 0 | 120032 | 119701 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062200 | 4548576 | 4577823 | 0 | 120011 | 120051 | 120047 | 112057 | 3 | 112471 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120035 | 120035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3529 | 12 | 78 | 11 | 9 | 119837 | 50000 | 9 | 6 | 5 | 10000 | 10000 | 50010 | 120036 | 120036 | 120048 | 120115 | 120051 |
60024 | 120139 | 931 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 120020 | 119701 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10039 | 1062228 | 4548576 | 4577862 | 0 | 120083 | 120050 | 120035 | 112072 | 3 | 112453 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120050 | 120047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 1 | 0 | 2855 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3165 | 11 | 78 | 10 | 10 | 119834 | 50002 | 10 | 6 | 8 | 10000 | 10000 | 50010 | 120051 | 120051 | 120042 | 120109 | 120057 |
60024 | 120137 | 931 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 59 | 0 | 0 | 0 | 0 | 120041 | 119706 | 25 | 70013 | 50012 | 10001 | 10000 | 40152 | 10000 | 10000 | 1062228 | 4547992 | 4577823 | 0 | 120023 | 120035 | 120051 | 112072 | 3 | 112453 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120047 | 120050 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 1 | 3 | 0 | 10000 | 1 | 0 | 1 | 0 | 0 | 0 | 3140 | 9 | 78 | 12 | 12 | 119759 | 50004 | 0 | 0 | 8 | 10000 | 10000 | 50010 | 120057 | 120051 | 120051 | 120117 | 120126 |
60024 | 120050 | 930 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | 0 | 120038 | 119701 | 25 | 70027 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062282 | 4548296 | 4578274 | 0 | 120032 | 120050 | 120047 | 112069 | 3 | 112474 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120050 | 120047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10001 | 1 | 1 | 10003 | 0 | 1 | 0 | 10000 | 0 | 1 | 1 | 1 | 0 | 0 | 3140 | 11 | 77 | 11 | 12 | 119767 | 50014 | 9 | 9 | 0 | 10000 | 10000 | 50010 | 120042 | 120057 | 120042 | 120118 | 120036 |
60024 | 120056 | 930 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 120032 | 119704 | 25 | 70016 | 50010 | 10000 | 10000 | 40010 | 10000 | 10000 | 1062228 | 4548804 | 4578426 | 0 | 120011 | 120035 | 120035 | 112093 | 3 | 112460 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10041 | 120056 | 120047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10001 | 1 | 1 | 10001 | 0 | 0 | 1 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 3140 | 10 | 78 | 10 | 11 | 119765 | 50002 | 0 | 6 | 0 | 10000 | 10000 | 50010 | 120130 | 120042 | 120057 | 120112 | 120054 |
60024 | 120056 | 931 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 120035 | 119710 | 25 | 70016 | 50014 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062282 | 4548031 | 4578057 | 0 | 120018 | 120053 | 120035 | 112099 | 3 | 112453 | 60010 | 30020 | 20000 | 10000 | 60020 | 30120 | 10000 | 120056 | 120055 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 1 | 10000 | 0 | 0 | 1 | 10002 | 0 | 1 | 1 | 1 | 0 | 0 | 3140 | 9 | 102 | 10 | 9 | 119801 | 50002 | 9 | 12 | 8 | 10000 | 10000 | 50010 | 120036 | 120039 | 120058 | 120145 | 120057 |
60024 | 120056 | 931 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 120035 | 119710 | 25 | 70016 | 50024 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062255 | 4548576 | 4577823 | 0 | 120017 | 120057 | 120047 | 112072 | 3 | 112466 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120053 | 120056 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 0 | 0 | 3140 | 10 | 78 | 10 | 11 | 119759 | 50002 | 6 | 9 | 5 | 10000 | 10000 | 50010 | 120051 | 120147 | 120051 | 120316 | 120057 |
60024 | 120050 | 931 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 0 | 0 | 120035 | 119710 | 25 | 70013 | 50014 | 10002 | 10000 | 40010 | 10000 | 10000 | 1062282 | 4548804 | 4578057 | 0 | 120032 | 120056 | 120057 | 112107 | 3 | 112468 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10040 | 120049 | 120043 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 1 | 1 | 0 | 10000 | 0 | 1 | 1 | 0 | 0 | 0 | 3140 | 10 | 78 | 10 | 11 | 119759 | 50002 | 10 | 9 | 8 | 10000 | 10000 | 50010 | 120136 | 120051 | 120053 | 120048 | 120057 |
60024 | 120050 | 931 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 120041 | 119704 | 25 | 70013 | 50012 | 10002 | 10000 | 40010 | 10000 | 10040 | 1062200 | 4548804 | 4578057 | 0 | 120027 | 120035 | 120056 | 112078 | 3 | 112474 | 60232 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120053 | 120050 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10001 | 0 | 1 | 10001 | 1 | 0 | 1 | 10000 | 1 | 1 | 1 | 0 | 0 | 0 | 3140 | 11 | 78 | 9 | 10 | 119765 | 50002 | 9 | 6 | 0 | 10000 | 10000 | 50010 | 120057 | 120043 | 120052 | 120099 | 120051 |
60024 | 120050 | 930 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 120041 | 119710 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062228 | 4548576 | 4578057 | 0 | 120027 | 120056 | 120050 | 112078 | 3 | 112460 | 60010 | 30168 | 20000 | 10000 | 60268 | 30000 | 10000 | 120047 | 120050 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10001 | 1 | 1 | 10001 | 0 | 0 | 4 | 10001 | 1 | 1 | 1 | 1 | 0 | 0 | 3140 | 9 | 78 | 11 | 11 | 119765 | 50002 | 6 | 9 | 8 | 10000 | 10000 | 50010 | 120057 | 120057 | 120057 | 120048 | 120042 |
Chain cycles: 3
Code:
ld1 { v0.8b, v1.8b }, [x6], x8 fmov x1, d1 eor x8, x8, x1 eor x8, x8, x1 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 9.0057
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60205 | 120053 | 930 | 1 | 0 | 0 | 0 | 0 | 1 | 3 | 0 | 0 | 0 | 25 | 0 | 1 | 0 | 0 | 120026 | 119645 | 25 | 70103 | 50104 | 10001 | 10000 | 40100 | 10000 | 10000 | 1061795 | 4544474 | 4574582 | 120032 | 0 | 120056 | 120056 | 112113 | 3 | 112432 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120056 | 120041 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10003 | 2 | 1 | 10001 | 0 | 101 | 0 | 4 | 10000 | 0 | 1 | 1 | 0 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119752 | 50004 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120042 | 120057 | 120057 | 120051 | 120135 |
60204 | 120056 | 931 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 1 | 0 | 120026 | 119639 | 25 | 70103 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1061914 | 4546159 | 4574816 | 120032 | 0 | 120059 | 120056 | 112026 | 3 | 112432 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120053 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10002 | 1 | 0 | 10002 | 0 | 0 | 1 | 4 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119759 | 50002 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120042 | 120057 | 120057 | 120057 | 120108 |
60204 | 120053 | 931 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 1 | 0 | 120043 | 119717 | 25 | 70106 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062239 | 4546159 | 4574699 | 120032 | 0 | 120056 | 120056 | 112046 | 3 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120056 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10002 | 1 | 1 | 10002 | 0 | 91 | 0 | 1 | 10000 | 0 | 1 | 1 | 1 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119759 | 50004 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120057 | 120057 | 120057 | 120058 | 120094 |
60204 | 120056 | 930 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 120035 | 119639 | 25 | 70106 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062239 | 4546159 | 4574699 | 120032 | 0 | 120035 | 120056 | 112046 | 3 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120047 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10002 | 2 | 0 | 10001 | 0 | 0 | 2 | 1 | 10000 | 1 | 1 | 0 | 1 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119762 | 50002 | 9 | 9 | 8 | 10000 | 10000 | 50100 | 120057 | 120057 | 120057 | 120057 | 120107 |
60204 | 120053 | 931 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 1 | 0 | 120041 | 119717 | 25 | 70106 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062239 | 4546159 | 4574738 | 120032 | 0 | 120056 | 120050 | 112047 | 3 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120053 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 2 | 1 | 10001 | 0 | 0 | 0 | 4 | 10000 | 1 | 1 | 1 | 0 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119752 | 50004 | 9 | 9 | 8 | 10000 | 10000 | 50100 | 120057 | 120057 | 120057 | 120057 | 120099 |
60204 | 120041 | 931 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 1 | 120038 | 119639 | 25 | 70106 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1061795 | 4546159 | 4576060 | 120032 | 0 | 120053 | 120056 | 112046 | 3 | 112450 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120056 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 1 | 1 | 10001 | 0 | 0 | 1 | 0 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119759 | 50002 | 9 | 9 | 8 | 10000 | 10000 | 50100 | 120051 | 120057 | 120045 | 120057 | 120131 |
60204 | 120041 | 931 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 120041 | 119639 | 25 | 70106 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062239 | 4546159 | 4574504 | 120033 | 0 | 120050 | 120053 | 112026 | 3 | 112447 | 60100 | 30200 | 20000 | 10040 | 60200 | 30000 | 10000 | 120041 | 120035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10002 | 1 | 1 | 10001 | 0 | 0 | 0 | 2817 | 10000 | 1 | 1 | 1 | 1 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119867 | 50004 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120057 | 120057 | 120146 | 120056 | 120054 |
60204 | 120053 | 931 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 120041 | 119633 | 25 | 70106 | 50116 | 10002 | 10000 | 40100 | 10000 | 10000 | 1062239 | 4546159 | 4573507 | 120017 | 0 | 120056 | 120041 | 112046 | 3 | 112441 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10041 | 120056 | 120053 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 1 | 100 | 10002 | 2 | 1 | 10000 | 0 | 95 | 0 | 4 | 10000 | 1 | 1 | 0 | 1 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119917 | 50033 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120155 | 120150 | 120246 | 120333 | 120267 |
60204 | 120229 | 932 | 1 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 2 | 2 | 398 | 264 | 0 | 1 | 0 | 120224 | 119729 | 77 | 70136 | 50138 | 10004 | 10006 | 40386 | 10078 | 10078 | 1066590 | 4549287 | 4578279 | 120236 | 0 | 120257 | 120332 | 112163 | 47 | 112545 | 60544 | 30325 | 20164 | 10040 | 60696 | 30120 | 10081 | 120239 | 120225 | 3 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10010 | 1 | 1 | 10001 | 0 | 98 | 0 | 4 | 10000 | 0 | 1 | 1 | 1 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119752 | 50004 | 9 | 9 | 0 | 10000 | 10000 | 50100 | 120042 | 120057 | 120057 | 120057 | 120110 |
60204 | 120056 | 930 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 120138 | 119639 | 25 | 70106 | 50104 | 10002 | 10000 | 40100 | 10000 | 10000 | 1061795 | 4544474 | 4574699 | 120033 | 0 | 120056 | 120056 | 112046 | 3 | 112447 | 60100 | 30200 | 20000 | 10000 | 60200 | 30000 | 10000 | 120059 | 120041 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10001 | 2 | 1 | 10001 | 0 | 101 | 1 | 1 | 10000 | 1 | 1 | 0 | 1 | 0 | 0 | 3210 | 1 | 83 | 1 | 1 | 119915 | 50004 | 9 | 6 | 8 | 10000 | 10000 | 50100 | 120057 | 120054 | 120057 | 120058 | 120054 |
Result (median cycles for code, minus 3 chain cycles): 9.0054
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 61 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | cd | cf | d0 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60025 | 120051 | 930 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 120039 | 119708 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1064347 | 4548614 | 4577979 | 0 | 0 | 120030 | 120054 | 120054 | 112073 | 3 | 112469 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 1 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3166 | 0 | 4 | 104 | 3 | 6 | 119907 | 50012 | 13 | 0 | 9 | 10000 | 10000 | 50010 | 120244 | 120052 | 120144 | 120052 | 120052 |
60024 | 120143 | 931 | 0 | 1 | 0 | 1 | 1 | 1 | 2 | 3 | 133 | 176 | 1 | 0 | 0 | 120313 | 119725 | 49 | 70041 | 50031 | 10007 | 10004 | 40296 | 10080 | 10078 | 1067640 | 4552304 | 4584098 | 0 | 0 | 120177 | 120138 | 120431 | 112223 | 23 | 112642 | 60675 | 30144 | 20160 | 10042 | 60508 | 30363 | 10081 | 120330 | 120215 | 3 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10005 | 0 | 1 | 10002 | 9 | 0 | 8425 | 10004 | 1 | 1 | 0 | 0 | 3140 | 0 | 6 | 112 | 5 | 4 | 119763 | 50002 | 10 | 10 | 12 | 10000 | 10000 | 50010 | 120052 | 120052 | 120052 | 120052 | 120055 |
60024 | 120051 | 931 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 120039 | 119705 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062264 | 4548614 | 4577979 | 0 | 0 | 120030 | 120054 | 120057 | 112073 | 3 | 112472 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 7 | 0 | 3 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 4 | 78 | 3 | 2 | 119760 | 50002 | 13 | 13 | 12 | 10000 | 10000 | 50010 | 120052 | 120052 | 120053 | 120058 | 120056 |
60024 | 120055 | 930 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 120038 | 119708 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062300 | 4548652 | 4577979 | 0 | 0 | 120030 | 120051 | 120056 | 112078 | 3 | 112469 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 3 | 78 | 4 | 3 | 119760 | 50002 | 10 | 10 | 9 | 10000 | 10000 | 50010 | 120055 | 120055 | 120054 | 120052 | 120053 |
60024 | 120051 | 931 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 120036 | 119705 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062264 | 4548614 | 4577979 | 0 | 0 | 120027 | 120054 | 120054 | 112076 | 3 | 112472 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 3 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 3 | 78 | 3 | 4 | 119760 | 50002 | 10 | 10 | 12 | 10000 | 10000 | 50010 | 120057 | 120055 | 120055 | 120056 | 120052 |
60024 | 120054 | 930 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 120036 | 119706 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062264 | 4548614 | 4578018 | 0 | 0 | 120030 | 120054 | 120054 | 112073 | 3 | 112474 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120054 | 120055 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 4 | 78 | 4 | 3 | 119763 | 50002 | 13 | 10 | 9 | 10000 | 10000 | 50010 | 120055 | 120052 | 120052 | 120052 | 120055 |
60024 | 120051 | 931 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 120039 | 119708 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062264 | 4548804 | 4577979 | 0 | 0 | 120030 | 120051 | 120051 | 112076 | 3 | 112472 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120054 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 5 | 78 | 4 | 4 | 119763 | 50002 | 10 | 10 | 12 | 10000 | 10000 | 50010 | 120055 | 120055 | 120052 | 120052 | 120053 |
60024 | 120051 | 931 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 13 | 0 | 0 | 1 | 0 | 120036 | 119708 | 25 | 70013 | 50012 | 10001 | 10000 | 40162 | 10000 | 10000 | 1062264 | 4548728 | 4577979 | 0 | 0 | 120027 | 120057 | 120051 | 112076 | 3 | 112474 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 6 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 3 | 78 | 3 | 4 | 119763 | 50002 | 13 | 10 | 9 | 10000 | 10000 | 50010 | 120055 | 120055 | 120052 | 120052 | 120055 |
60024 | 120051 | 931 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 120039 | 119707 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062264 | 4548728 | 4577979 | 0 | 0 | 120030 | 120054 | 120057 | 112076 | 3 | 112472 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 3 | 78 | 5 | 3 | 119766 | 50002 | 13 | 10 | 12 | 10000 | 10000 | 50010 | 120055 | 120055 | 120052 | 120052 | 120055 |
60024 | 120051 | 931 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 120036 | 119705 | 25 | 70013 | 50012 | 10001 | 10000 | 40010 | 10000 | 10000 | 1062237 | 4548728 | 4577979 | 0 | 0 | 120030 | 120051 | 120051 | 112076 | 3 | 112472 | 60010 | 30020 | 20000 | 10000 | 60020 | 30000 | 10000 | 120051 | 120051 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 4 | 78 | 3 | 4 | 119763 | 50002 | 10 | 10 | 12 | 10000 | 10000 | 50010 | 120055 | 120055 | 120055 | 120055 | 120052 |
Count: 8
Code:
ld1 { v0.8b, v1.8b }, [x6], x8 ld1 { v0.8b, v1.8b }, [x6], x8 ld1 { v0.8b, v1.8b }, [x6], x8 ld1 { v0.8b, v1.8b }, [x6], x8 ld1 { v0.8b, v1.8b }, [x6], x8 ld1 { v0.8b, v1.8b }, [x6], x8 ld1 { v0.8b, v1.8b }, [x6], x8 ld1 { v0.8b, v1.8b }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 23 | 24 | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160205 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 80025 | 1 | 0 | 6 | 5 | 25 | 160100 | 80100 | 80000 | 80100 | 80000 | 4359010 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80045 | 0 | 14 | 80058 | 0 | 0 | 763 | 80056 | 6 | 1 | 13 | 0 | 0 | 5138 | 1 | 25 | 1 | 2 | 80077 | 1 | 80000 | 9 | 9 | 80000 | 80000 | 80100 | 80096 | 80096 | 80096 | 80095 | 80096 |
160204 | 80094 | 621 | 1 | 0 | 0 | 0 | 0 | 1 | 2 | 283 | 88 | 0 | 0 | 80079 | 0 | 6 | 6 | 48 | 99 | 160152 | 80127 | 80025 | 80252 | 80069 | 4359002 | 3761009 | 0 | 80015 | 80147 | 80096 | 59936 | 18 | 60025 | 160245 | 202 | 160304 | 200 | 240225 | 80095 | 80095 | 3 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80044 | 2 | 14 | 80060 | 0 | 0 | 757 | 80035 | 6 | 1 | 9 | 17 | 2 | 5139 | 1 | 34 | 1 | 1 | 80037 | 1 | 80000 | 9 | 6 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 80025 | 1 | 6 | 6 | 9 | 25 | 160100 | 80100 | 80000 | 80100 | 80000 | 4359002 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 14 | 80012 | 1 | 0 | 16 | 80010 | 6 | 1 | 10 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 1 | 80000 | 9 | 6 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 80025 | 1 | 6 | 6 | 4 | 25 | 160100 | 80100 | 80000 | 80100 | 80000 | 4359002 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 14 | 80013 | 0 | 0 | 11 | 80012 | 6 | 1 | 0 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 1 | 80000 | 9 | 4 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 18 | 0 | 0 | 0 | 80025 | 1 | 6 | 8 | 1 | 25 | 160100 | 80100 | 80000 | 80100 | 80000 | 4358982 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 80010 | 0 | 0 | 13 | 80013 | 6 | 1 | 0 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 1 | 80000 | 9 | 6 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 80025 | 1 | 6 | 6 | 4 | 25 | 160152 | 80100 | 80000 | 80100 | 80000 | 4359006 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 14 | 80013 | 0 | 0 | 10 | 80010 | 6 | 1 | 9 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 1 | 80000 | 9 | 6 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 80025 | 1 | 6 | 6 | 5 | 25 | 160100 | 80100 | 80000 | 80100 | 80000 | 4359002 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 14 | 80013 | 1 | 0 | 10 | 80015 | 6 | 1 | 0 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 0 | 80000 | 0 | 6 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 80025 | 1 | 6 | 6 | 4 | 25 | 160100 | 80100 | 80000 | 80100 | 80000 | 4359002 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 14 | 80012 | 0 | 0 | 12 | 80015 | 6 | 1 | 0 | 17 | 0 | 5110 | 1 | 16 | 1 | 1 | 80037 | 1 | 80000 | 9 | 9 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 620 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 80025 | 1 | 6 | 6 | 5 | 25 | 160100 | 80100 | 80000 | 80100 | 80000 | 4359002 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 17 | 80013 | 1 | 0 | 13 | 80010 | 6 | 0 | 0 | 17 | 0 | 5110 | 1 | 16 | 2 | 2 | 80037 | 1 | 80000 | 6 | 6 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
160204 | 80040 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 80025 | 1 | 6 | 6 | 0 | 25 | 160100 | 80100 | 80000 | 80100 | 80000 | 4359006 | 3758824 | 0 | 80015 | 80040 | 80040 | 59924 | 3 | 59998 | 160100 | 200 | 160000 | 200 | 240000 | 80040 | 80040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 80013 | 0 | 0 | 0 | 80000 | 0 | 0 | 10 | 17 | 0 | 5110 | 1 | 16 | 1 | 2 | 80037 | 1 | 80000 | 9 | 9 | 80000 | 80000 | 80100 | 80041 | 80041 | 80041 | 80041 | 80041 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 61 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160025 | 80040 | 600 | 1 | 0 | 0 | 0 | 1 | 36 | 0 | 0 | 80025 | 0 | 6 | 6 | 10 | 25 | 160010 | 80010 | 80000 | 80010 | 80000 | 4358357 | 3758818 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80007 | 7 | 27 | 80030 | 94 | 0 | 36 | 80000 | 6 | 1 | 30 | 27 | 7 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 1 | 80000 | 13 | 0 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 599 | 1 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 80025 | 1 | 6 | 6 | 10 | 25 | 160010 | 80010 | 80000 | 80314 | 80000 | 4358377 | 3758820 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 10 | 60099 | 160010 | 20 | 160152 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 80008 | 8 | 27 | 80030 | 97 | 0 | 29 | 80023 | 6 | 1 | 29 | 27 | 7 | 1 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 1 | 80000 | 0 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 599 | 1 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 80025 | 1 | 6 | 6 | 1 | 25 | 160010 | 80010 | 80000 | 80010 | 80000 | 4358381 | 3758820 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80007 | 7 | 27 | 80029 | 0 | 1 | 39 | 80022 | 6 | 0 | 29 | 27 | 7 | 0 | 5020 | 0 | 0 | 2 | 16 | 3 | 3 | 80037 | 1 | 80000 | 13 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 599 | 1 | 0 | 1 | 0 | 0 | 7 | 0 | 1 | 80025 | 1 | 0 | 6 | 10 | 25 | 160010 | 80010 | 80000 | 80010 | 80000 | 4358389 | 3758824 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80006 | 6 | 27 | 80030 | 0 | 1 | 32 | 80000 | 6 | 1 | 29 | 27 | 7 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 4 | 80037 | 1 | 80000 | 13 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 599 | 1 | 1 | 1 | 0 | 0 | 36 | 0 | 1 | 80025 | 0 | 6 | 0 | 10 | 25 | 160010 | 80010 | 80000 | 80010 | 80000 | 4358429 | 3758820 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80008 | 7 | 27 | 80031 | 0 | 1 | 35 | 80023 | 6 | 1 | 29 | 27 | 7 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 2 | 80037 | 0 | 80000 | 13 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 599 | 1 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 80025 | 1 | 6 | 6 | 10 | 25 | 160010 | 80010 | 80000 | 80010 | 80000 | 4358377 | 3758820 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80007 | 7 | 27 | 80030 | 0 | 0 | 32 | 80023 | 6 | 1 | 30 | 27 | 7 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 1 | 80000 | 13 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 599 | 1 | 0 | 0 | 0 | 0 | 35 | 0 | 0 | 80025 | 1 | 6 | 6 | 10 | 25 | 160010 | 80010 | 80075 | 80010 | 80000 | 4358373 | 3758823 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80006 | 6 | 27 | 80030 | 97 | 1 | 30 | 80023 | 6 | 1 | 29 | 27 | 6 | 0 | 5020 | 0 | 0 | 3 | 16 | 4 | 4 | 80037 | 0 | 80000 | 13 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 599 | 1 | 1 | 0 | 0 | 0 | 35 | 0 | 1 | 80025 | 1 | 6 | 6 | 2 | 25 | 160010 | 80010 | 80000 | 80010 | 80000 | 4358381 | 3758820 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80008 | 8 | 27 | 80031 | 0 | 1 | 35 | 80022 | 6 | 1 | 30 | 27 | 7 | 2 | 5020 | 0 | 0 | 2 | 16 | 4 | 3 | 80037 | 1 | 80000 | 13 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 600 | 1 | 1 | 1 | 0 | 0 | 36 | 0 | 0 | 80025 | 1 | 6 | 6 | 10 | 25 | 160010 | 80010 | 80000 | 80010 | 80000 | 4358389 | 3758825 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80008 | 9 | 27 | 80031 | 0 | 0 | 32 | 80023 | 6 | 1 | 29 | 27 | 7 | 1 | 5020 | 0 | 0 | 3 | 16 | 3 | 3 | 80037 | 1 | 80000 | 13 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |
160024 | 80040 | 599 | 1 | 0 | 0 | 1 | 1 | 36 | 0 | 0 | 80025 | 1 | 6 | 6 | 10 | 25 | 160010 | 80010 | 80000 | 80010 | 80000 | 4358377 | 3758820 | 0 | 0 | 80015 | 0 | 80040 | 80040 | 59946 | 3 | 60020 | 160010 | 20 | 160000 | 20 | 240000 | 80040 | 80040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80008 | 6 | 27 | 80029 | 0 | 1 | 32 | 80023 | 6 | 1 | 30 | 27 | 7 | 0 | 5020 | 0 | 0 | 3 | 16 | 3 | 2 | 80037 | 0 | 80000 | 13 | 13 | 80000 | 80000 | 80010 | 80041 | 80041 | 80041 | 80041 | 80041 |