Firestorm: LD1 (multiple, post-index, 2 regs, 8H) measurements

Code:

  ld1 { v0.8h, v1.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	22	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
62005	28513	213	1	0	0	0	1	2	1	8	0	5052	27974	0	0	0	23213	3000	1000	2000	1000	2000	5000	10000	22	16011	27913	28260	3	10	3000	2000	3000	28274	28348	1	1	61001	1000	1000	2003	2	6	2002	0	0	4	2006	2	4	0	2	1	13500	9891	7129	3293	0	41	19526	3242	3810	16	47	43	27958	1000	14509	12409	13947	2000	1000	28441	28414	28282	28427	28261
62004	28342	212	0	0	1	1	1	2	1	10	0	5069	28213	0	2	2	23281	3000	1000	2000	1000	2000	5000	10000	20	16041	28007	28399	3	10	3000	2000	3000	28212	28175	1	1	61001	1000	1000	2000	3	6	2002	0	1	4	2006	4	4	6	2	1	13713	9922	7082	3401	2	37	19418	3218	3813	11	51	43	27980	1000	14800	12144	13046	2000	1000	28440	28309	28427	28382	28377
62004	28170	212	0	1	2	1	1	2	1	8	0	4923	28223	0	2	0	23355	3000	1000	2000	1000	2000	5000	10000	13	16029	28035	28426	3	10	3000	2000	3000	28198	28289	1	1	61001	1000	1000	2000	0	6	2002	0	0	2	2002	4	4	6	0	1	13491	10145	7156	3356	0	38	19760	3209	3809	14	44	41	27962	1000	14855	12260	13454	2000	1000	28326	28480	28361	28495	28330
62004	28291	212	0	1	1	0	0	2	0	29	0	5074	28229	0	0	2	23238	3000	1000	2000	1000	2000	5000	10000	18	16036	28148	28462	3	10	3000	2000	3000	28262	28182	1	1	61001	1000	1000	2000	0	6	2004	0	1	2	2002	4	2	6	0	0	13953	10202	7132	3365	1	42	19720	3340	3816	12	47	40	27896	1000	14765	12359	13509	2000	1000	28306	28420	28467	28397	28280
62004	28316	213	0	1	2	0	0	1	1	8	0	5058	28023	2	2	2	23300	3000	1000	2000	1000	2000	5000	10000	18	16041	27989	28482	3	10	3000	2000	3000	28308	28177	1	1	61001	1000	1000	2000	0	4	2002	0	0	2	2002	2	2	4	0	0	13842	10034	7170	3378	0	41	19822	3290	3805	10	42	45	27971	1000	14617	12467	13383	2000	1000	28383	28333	28295	28305	28287
62004	28406	213	0	0	3	0	0	2	0	8	0	4964	28133	2	2	2	23281	3000	1000	2000	1000	2000	5000	10000	18	16045	28055	28322	3	10	3000	2000	3000	28355	28319	1	1	61001	1000	1000	2003	2	4	2004	0	0	4	2000	4	4	0	2	1	13722	9736	7135	3307	0	41	19830	3276	3813	13	43	39	27971	1000	14817	12304	13458	2000	1000	28123	28276	28305	28181	28379
62004	28385	212	0	0	2	0	0	1	0	8	0	5013	28050	0	2	0	23202	3000	1000	2000	1000	2000	5000	10000	13	16042	28091	28313	3	10	3000	2000	3000	28346	28406	1	1	61001	1000	1000	2003	3	6	2004	0	0	4	2002	2	2	0	2	1	13640	10010	7147	3309	1	44	19512	3306	3812	13	42	44	28173	1000	14689	12450	13186	2000	1000	28381	28451	28382	28386	28398
62004	28391	213	0	0	0	1	1	3	0	8	0	4818	28005	0	2	0	23331	3000	1000	2000	1000	2000	5000	10002	13	16052	28051	28363	3	10	3000	2000	3000	28169	28276	1	1	61001	1000	1000	2002	0	6	2002	0	1	2	2002	2	2	4	0	0	13653	10015	7161	3317	0	36	19558	3421	3816	8	39	46	27979	1000	14922	12480	13490	2000	1000	28496	28443	28276	28401	28167
62004	28407	211	0	0	1	1	0	3	0	8	0	5062	28259	0	2	2	23237	3000	1000	2000	1000	2000	5000	10000	13	16052	28092	28411	3	10	3000	2000	3000	28096	28251	1	1	61001	1000	1000	2000	3	6	2002	0	1	2	2002	2	4	8	2	1	13494	10032	7183	3313	0	49	19762	3274	3810	11	45	50	27856	1000	14585	12342	13254	2000	1000	28439	28378	28278	28357	28522
62004	28395	214	0	0	1	0	0	4	0	8	0	5121	28256	0	2	2	23397	3000	1000	2000	1000	2000	5000	10000	8	16031	28045	28343	3	10	3000	2000	3000	28270	28272	1	1	61001	1000	1000	2002	3	6	2004	0	0	4	2002	4	4	6	2	0	13475	9860	7141	3360	1	38	19714	3280	3815	11	39	44	27992	1000	14552	12258	13297	2000	1000	28245	28111	28376	28319	28209

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h, v1.8h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0057

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120058	899	0	0	1	0	1	1	0	0	23	0	1	0	0	0	120043	98763	109737	25	80103	50102	10001	20000	40100	10000	20000	13850459	5733436	3465510	120027	120051	120055	112139	3	112601	70100	30200	20000	10000	60200	30000	10000	120051	120035	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	0	0	2	0	0	3210	1	16	1	1	119820	50002	9	6	5	20000	50100	120049	120048	120048	120048	120048
60204	120047	931	0	0	0	0	0	0	0	0	2	0	0	1	0	1	120036	98905	109741	25	80103	50102	10001	20000	40100	10000	20000	13850459	5732666	3465510	120027	120047	120047	112135	3	112505	70100	30200	20000	10000	60200	30000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	2	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119824	50002	0	6	9	20000	50100	120153	120052	120052	120052	120052
60204	120051	964	0	0	0	0	1	1	0	0	2	0	0	0	0	0	120036	98905	109740	25	80103	50102	10001	20000	40100	10000	20000	13850459	5736174	3465510	120027	120053	120051	112139	3	112550	70100	30292	20000	10000	60200	30000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119903	50002	10	0	5	20000	50100	120052	120052	120052	120052	120052
60204	120145	931	0	0	1	0	0	0	0	0	2	0	0	1	0	1	120036	98763	109740	25	80103	50102	10001	20004	40100	10000	20000	13850691	5733436	3465625	120029	120051	120035	112125	3	112571	70100	30200	20000	10000	60200	30000	10000	120052	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119808	50002	12	6	0	20000	50100	120048	120052	120052	120052	120036
60204	120051	931	0	0	0	0	0	0	0	0	134	0	0	0	0	0	120032	98763	109739	25	80103	50102	10001	20000	40100	10000	20000	13849995	5733244	3465510	120011	120035	120035	112135	3	112507	70100	30200	20000	10000	60200	30000	10031	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119824	50002	10	6	5	20000	50100	120052	120052	120052	120052	120052
60204	120051	930	0	0	0	0	0	1	0	0	2	0	0	1	0	0	120032	98763	109736	25	80103	50102	10001	20000	40100	10030	20000	13849995	5733244	3465510	120023	120047	120047	112135	3	112536	70304	30200	20000	10000	60200	30000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119824	50002	10	6	0	20000	50100	120052	120048	120052	120049	120146
60204	120051	930	0	0	0	0	1	0	0	0	14	88	0	1	0	1	120125	98764	109782	25	80103	50102	10001	20000	40100	10000	20000	13850459	5733436	3465510	120011	120054	120051	112139	3	112505	70100	30200	20000	10000	60200	30000	10030	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119820	50002	10	0	5	20000	50100	120052	120052	120052	120052	120048
60204	120047	931	0	1	0	0	0	0	0	0	2	0	0	0	0	1	120036	98905	109740	25	80103	50102	10001	20000	40100	10000	20000	13848583	5732666	3466892	120011	120051	120051	112139	3	112586	70100	30298	20000	10000	60200	30000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	0	20000	0	0	2	0	0	3210	1	17	1	1	119820	50000	6	10	9	20000	50100	120049	120048	120048	120039	120052
60204	120051	930	0	0	0	0	0	0	0	0	2	0	0	1	0	1	120036	98763	109740	25	80103	50115	10001	20000	40100	10000	20000	13850459	5733436	3465510	120027	120035	120035	112139	3	112554	70100	30200	20000	10000	60200	30000	10000	120048	120138	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	0	0	3	20000	2	0	2	0	0	3210	1	16	1	1	119824	50000	10	11	9	20000	50100	120142	120052	120049	120052	120036
60204	120051	930	0	0	1	0	0	0	1	0	2	0	0	1	0	1	120036	98759	109740	25	80100	50102	10001	20000	40100	10000	20050	13850459	5733436	3465539	120105	120051	120051	112123	3	112574	70100	30200	20000	10000	60200	30000	10000	120047	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	3	0	0	20000	2	0	2	0	0	3210	1	16	1	1	119824	50002	10	6	9	20000	50100	120052	120052	120052	120052	120148

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	d9	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120048	931	0	0	0	0	0	0	0	0	2	0	0	0	0	1	120109	96480	109740	25	80031	50012	10001	20000	40010	10030	20000	13848900	5733244	3465234	0	120028	120052	120051	112158	3	112532	70010	30111	20000	10000	60020	30000	10000	120057	120053	1	1	50021	10	9	10	40010	10000	10000	1	10	20002	2	2	20003	0	1	1	5	20000	2	2	2	2	0	3140	0	3	24	0	0	2	2	119832	50002	6	6	9	20000	50010	120042	120059	120149	120060	120054
60024	120128	965	1	0	0	0	0	1	0	0	5	0	0	0	0	0	120122	96542	109818	48	80030	50012	10006	20004	40129	10030	20050	13855153	5736384	3467119	0	120181	120139	120140	112162	16	112534	70209	30116	20062	10032	60206	30093	10032	120137	120051	2	1	50021	10	9	10	40010	10000	10000	0	10	20006	1	2	20004	0	0	2	8925	20006	2	0	0	0	0	3182	0	2	41	0	0	2	5	120010	50024	14	10	0	20000	50010	120222	120335	120237	120280	120418
60024	120323	932	0	0	1	0	1	0	0	0	0	0	0	0	0	0	120041	96484	109744	25	80013	50012	10000	20002	40010	10000	20000	13849475	5733436	3465350	1	120031	120102	120097	112162	3	112534	70010	30020	20000	10000	60020	30000	10000	120055	120055	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	3140	0	3	17	0	0	3	3	119830	50002	14	0	1	20000	50010	120056	120056	120103	120082	120036
60024	120035	931	0	0	0	0	0	0	0	0	2	0	0	0	0	1	120040	96484	109744	25	80013	50012	10001	20000	40010	10000	20000	13849251	5733628	3465350	0	120031	120056	120035	112166	3	112534	70010	30020	20000	10000	60218	30000	10000	120100	120054	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	1	0	0	20000	0	0	2	0	2	3140	0	3	17	0	0	2	0	119810	50002	10	10	16	20000	50010	120056	120056	120056	120056	120056
60024	120055	931	0	0	0	0	1	1	0	0	2	0	0	0	0	1	120020	96512	109744	25	80013	50010	10001	20000	40010	10000	20000	13848787	5733628	3465350	0	120011	120055	120055	112166	3	112534	70221	30020	20000	10000	60020	30000	10000	120055	120055	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	198	20000	2	0	2	0	0	3140	0	2	17	0	0	3	3	119826	50002	10	0	13	20000	50010	120057	120056	120056	120056	120056
60024	120055	931	0	0	0	0	0	0	0	0	2	0	0	0	0	1	120040	96484	109744	25	80013	50012	10001	20000	40010	10000	20000	13846911	5733628	3467734	1	120031	120055	120061	112166	3	112534	70010	30020	20000	10000	60020	30000	10000	120055	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	3	20000	2	0	2	0	0	3140	0	3	17	0	0	2	3	119830	50000	14	10	13	20000	50010	120059	120056	120036	120052	120057
60024	120055	931	0	0	0	0	0	0	0	0	2	0	0	0	1	1	120020	96484	109744	25	80013	50012	10001	20000	40010	10000	20000	13849700	5733772	3465350	0	120011	120055	120035	112166	3	112514	70010	30020	20000	10000	60020	30000	10000	120055	120055	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	1	0	0	20000	2	0	2	0	0	3140	0	3	17	0	0	2	2	119831	50002	14	14	9	20000	50010	120056	120056	120056	120056	120052
60024	120055	930	0	0	0	0	0	0	0	0	26	0	0	0	0	1	120040	96484	109744	25	80013	50012	10001	20000	40010	10000	20000	13849367	5733628	3465379	0	120031	120055	120051	112166	3	112534	70010	30020	20000	10000	60020	30000	10000	120055	120055	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	0	20000	2	0	2	0	0	3140	0	3	17	0	0	3	3	119831	50002	14	10	13	20000	50010	120056	120056	120036	120057	120057
60024	120055	931	0	0	0	0	0	0	0	0	2	0	0	0	0	1	120040	96484	109746	25	80013	50012	10001	20000	40010	10000	20000	13849251	5733628	3464880	0	120027	120035	120055	112166	3	112534	70010	30020	20000	10000	60020	30000	10000	120055	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20002	0	2	20000	0	0	0	0	20000	2	0	2	0	0	3140	0	3	17	0	0	2	2	119810	50000	0	0	13	20000	50010	120056	120036	120056	120056	120056
60024	120051	931	0	0	0	0	0	0	0	0	2	0	0	0	0	0	120040	96480	109724	25	80013	50012	10000	20000	40010	10000	20000	13849251	5733628	3464880	0	120034	120055	120055	112166	3	112534	70010	30020	20000	10000	60020	30000	10000	120055	120055	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	0	2	20000	0	1	0	0	20000	0	0	2	0	2	3140	0	3	17	0	0	2	2	119909	50000	14	14	13	20000	50010	120036	120056	120056	120056	120056

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h, v1.8h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	ce	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60205	120057	930	0	0	0	0	1	0	0	203	0	0	0	0	120041	98763	109724	25	80100	50102	10001	20000	40100	10000	20000	13850923	5732666	3465626	0	120011	120056	120035	112143	3	112509	70100	30200	20000	10000	60200	30000	10000	120059	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	0	20000	2	2	2	2	0	0	0	3210	1	16	1	1	119814	50004	0	0	13	20000	50100	120046	120042	120045	120062	120042
60204	120061	930	1	0	1	0	0	0	0	553	0	1	0	0	120026	98769	109746	25	80106	50104	10002	20000	40100	10000	20000	13851155	5732956	3465420	0	120033	120041	120057	112145	3	112515	70100	30200	20000	10000	60200	30000	10000	120057	120053	1	1	50201	100	99	100	40100	10000	10000	0	100	20003	3	2	20003	1	0	5	20000	2	2	2	2	0	0	0	3210	1	16	1	1	119830	50004	13	6	0	20000	50100	120058	120055	120054	120058	120054
60204	120057	931	0	0	0	0	0	0	0	315	0	0	0	1	120036	98905	109742	25	80103	50102	10001	20000	40100	10000	20000	13850459	5733436	3465510	0	120030	120051	120051	112139	3	112511	70100	30200	20000	10000	60200	30000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	20000	2	0	2	0	0	0	0	3210	1	16	1	1	119824	50000	8	6	9	20000	50100	120036	120052	120036	120053	120052
60204	120035	930	0	0	0	0	0	0	0	92	0	0	0	0	123256	98905	109724	25	80103	50102	10001	20000	40100	10000	20000	13850571	5733436	3465597	0	120027	120051	120052	112161	3	112509	70100	30200	20064	10000	60200	30000	10000	120051	120087	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	3	20000	2	0	2	0	0	0	0	3210	1	16	1	1	119820	50002	0	10	5	20000	50100	120052	120052	120052	120049	120052
60204	120051	931	0	0	0	0	0	0	0	38	0	0	0	1	120020	98763	109760	25	80100	50100	10000	20000	40100	10030	20000	13849995	5733436	3465156	0	120027	120051	120051	112139	3	112509	70100	30200	20000	10000	60200	30000	10000	120051	120051	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	1	2	0	20000	2	0	0	0	0	0	0	3210	1	16	1	1	119824	50002	0	0	9	20000	50100	120052	120052	120036	120052	120053
60204	120047	930	0	0	0	0	0	0	0	56	0	0	1	0	120036	98602	109736	25	80100	50102	10000	20000	40100	10000	20000	13849995	5733436	3465510	0	120027	120053	120137	112123	3	112509	70100	30200	20000	10030	60200	30000	10000	120035	120035	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	2	20000	0	0	3	20000	2	0	2	0	0	0	0	3210	1	16	1	1	119825	50002	0	10	9	20000	50100	120052	120052	120052	120052	120057
60204	120140	930	0	0	0	0	0	0	0	68	0	0	0	0	120036	98763	109740	25	80103	50100	10003	20000	40100	10000	20000	13849995	5733436	3465510	0	120023	120035	120035	112123	3	112509	70100	30200	20000	10000	60200	30000	10000	120052	120051	2	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	0	20000	0	0	0	20000	2	0	2	0	0	0	0	3210	3	316	1	1	119886	50002	10	0	9	20000	50100	120052	120052	120053	120054	120052
60204	120051	930	0	0	0	0	0	0	0	68	0	0	0	1	120036	98904	109740	25	80103	50102	10001	20000	40100	10000	20000	13850459	5733436	3465539	0	120027	120135	120047	112139	3	112509	70100	30200	20064	10000	60200	30000	10000	120035	120047	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	0	20000	2	0	2	0	0	0	0	3210	1	16	2	1	119824	50002	11	10	0	20000	50100	120036	120052	120036	120052	120054
60204	120051	930	0	0	0	0	0	0	0	42	0	0	0	1	120036	98763	109724	25	80118	50102	10001	20000	40100	10000	20000	13850459	5733436	3465156	0	120027	120051	120052	112139	3	112510	70100	30200	20000	10000	60200	30000	10000	120051	120140	1	1	50201	100	99	100	40100	10000	10000	0	100	20000	0	2	20000	1	0	0	20000	2	0	0	0	0	0	0	3210	1	16	1	1	119824	50002	10	10	9	20000	50100	120054	120052	120052	120036	120052
60204	120051	931	0	0	0	0	1	0	0	56	0	0	0	0	120036	98763	109724	25	80100	50102	10001	20000	40223	10000	20000	13850459	5733484	3465539	0	120027	120051	120051	112124	3	112571	70100	30200	20000	10000	60200	30000	10000	120051	120047	1	1	50201	100	99	100	40100	10000	10000	1	100	20000	0	0	20000	0	0	0	20000	2	0	2	0	0	0	0	3210	1	16	1	1	119808	50002	0	0	9	20000	50100	120052	120052	120054	120052	120052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60025	120047	930	0	0	1	0	3	0	0	2	161	88	0	0	0	120088	96419	109829	25	80049	50012	10007	20000	40253	10000	20102	13848323	5739000	3466843	120242	0	120139	120331	112268	15	112655	70409	30301	20126	10062	60578	30189	10063	120123	120318	3	1	50021	10	9	10	40010	10000	10000	0	10	20004	0	2	20006	0	0	4625	20002	2	0	0	0	3204	3	39	1	3	2	119903	50033	10	6	0	20000	50010	120242	120229	120237	120231	120124
60024	120224	932	2	0	1	1	1	1	0	0	14	0	0	0	0	120036	96477	109740	25	80013	50012	10001	20000	40010	10000	20000	13848787	5733436	3465350	120027	0	120051	120053	112163	3	112530	70010	30020	20000	10000	60020	30000	10000	120051	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	2	0	0	3140	3	17	1	2	3	119826	50000	10	6	9	20000	50010	120052	120052	120052	120052	120052
60024	120051	931	0	0	0	0	0	0	0	0	2	0	0	0	1	120036	96480	109740	25	80013	50012	10001	20000	40010	10000	20000	13849123	5733436	3465234	120011	0	120051	120051	112146	3	112530	70010	30020	20000	10000	60020	30000	10000	120051	120047	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	3	20000	0	2	0	0	3140	2	17	1	2	3	119810	50000	10	14	9	20000	50010	120052	120036	120036	120052	120036
60024	120035	931	0	0	0	0	0	0	0	0	2	0	0	0	1	120036	96484	109740	25	80013	50012	10001	20000	40010	10000	20000	13848787	5733436	3465234	120027	0	120051	120051	112162	3	112530	70010	30020	20000	10000	60020	30000	10000	120054	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20002	2	2	0	0	3140	2	17	0	4	4	119810	50002	10	13	5	20000	50010	120036	120052	120051	120052	120055
60024	120051	931	0	0	0	0	0	0	0	0	0	0	0	0	1	120020	96480	109857	25	80013	50012	10001	20000	40010	10000	20000	13848787	5733436	3464880	120027	0	120051	120051	112146	3	112531	70010	30020	20000	10000	60020	30000	10000	120051	120047	1	1	50021	10	9	10	40010	10000	10000	1	10	20000	0	2	20000	0	0	3	20000	0	0	0	0	3140	2	17	0	3	2	119810	50002	11	6	9	20000	50010	120048	120052	120052	120036	120036
60024	120051	931	0	0	0	0	0	0	0	0	2	0	0	0	1	120036	96480	109740	25	80013	50010	10001	20000	40010	10000	20000	13848787	5733436	3464880	120027	0	120051	120227	112332	3	112530	70010	30020	20000	10000	60020	30000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	0	20000	0	0	0	20000	2	2	0	0	3140	3	17	1	3	3	119826	50002	10	10	9	20000	50010	120052	120052	120036	120052	120052
60024	120051	930	0	0	0	0	0	0	0	0	14	0	0	1	0	120021	96512	109740	25	80013	50012	10001	20000	40010	10000	20000	13848323	5733436	3465234	120027	0	120051	120035	112162	3	112530	70010	30020	20000	10000	60020	30000	10000	120051	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	0	2	0	0	3140	2	17	0	2	3	119826	50002	0	6	0	20000	50010	120036	120052	120036	120036	120052
60024	120047	931	0	0	0	0	0	0	0	0	14	0	0	0	1	120032	96480	109724	25	80013	50010	10001	20000	40010	10000	20000	13848323	5732666	3464880	120027	0	120047	120051	112146	3	112530	70010	30020	20000	10033	60020	30000	10000	120035	120035	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	0	0	0	20000	2	2	0	0	3140	3	17	0	3	4	119826	50000	10	6	9	20000	50010	120053	120036	120052	120052	120052
60024	120035	930	0	0	0	0	1	0	0	0	2	0	0	0	1	120036	96512	109724	25	80013	50012	10001	20000	40010	10000	20000	13848323	5733244	3465318	120027	0	120047	120035	112162	3	112530	70010	30020	20000	10000	60020	30000	10000	120051	120051	1	1	50021	10	9	10	40010	10000	10000	0	10	20000	0	2	20000	1	0	0	20000	2	2	0	0	3140	2	17	0	3	3	119826	50002	10	6	9	20000	50010	120048	120052	120052	120036	120052
60024	120051	931	0	0	0	0	0	0	0	0	2	0	0	0	0	120036	96476	109740	25	80013	50012	10001	20000	40010	10000	20000	13848323	5733436	3465350	120027	0	120051	120051	112162	3	112532	70010	30020	20000	10000	60020	30000	10000	120051	120059	1	1	50021	10	9	10	40010	10000	10000	0	10	20008	0	2	20014	0	2	4508	20002	2	0	0	0	3161	3	187	0	4	3	121617	50024	10	6	9	20000	50010	120231	120218	120313	120235	120229

Test 4: throughput

Count: 8

Code:

  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3c	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160205	80040	642	0	0	0	0	0	0	0	0	0	0	41	0	0	0	1	0	80025	2	12	12	11	25	240100	80100	160000	80100	0	160000	2026711	3679352	0	0	80027	80040	80040	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	0	0	32	160032	6	1	24	35	0	0	5110	0	2	16	3	2	80037	0	80000	10	6	160000	80100	80041	80042	80041	80041	80042
160204	80040	642	0	0	0	0	0	0	0	0	0	0	37	0	0	0	0	0	80025	0	0	12	8	25	240100	80100	160000	80100	0	160000	2026711	3672670	0	0	80016	80040	80040	59953	3	59998	240100	200	160000	200	240000	80040	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160000	0	0	0	0	160031	6	1	24	29	0	0	5110	0	3	16	3	3	80037	0	80000	10	10	160000	80100	80041	80041	80041	80041	80041
160204	80040	642	0	0	0	0	0	0	0	0	0	0	40	0	0	0	0	0	80025	2	12	12	11	25	240100	80100	160000	80100	0	160000	2026711	3672670	0	0	80015	80040	80040	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160032	0	1	0	24	160000	6	1	23	0	0	0	5110	0	3	16	2	2	80037	1	80063	10	0	160000	80100	80041	80041	80041	80041	80041
160204	80040	643	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	80025	2	12	12	11	25	240100	80100	160000	80100	0	160000	2036598	3652002	0	0	80022	80040	80040	59954	12	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160032	0	1	0	3	160000	6	0	23	35	0	0	5110	0	3	16	4	4	80037	1	80000	10	10	160000	80100	80041	80042	80041	80041	80041
160204	80040	643	0	0	0	0	0	0	0	0	0	0	51	0	0	0	0	0	80025	2	12	12	19	25	240100	80100	160000	80100	0	160000	2006713	3646096	0	0	80015	80040	80041	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160031	0	2	0	0	160031	6	1	29	35	0	0	5110	0	3	16	3	3	80037	1	80000	6	6	160000	80100	80041	80041	80042	80041	80041
160204	80040	643	0	0	0	0	0	0	1	0	0	0	49	0	0	0	1	0	80025	0	12	12	11	25	240100	80100	160000	80100	0	160000	2030764	3680385	0	0	80015	80040	80040	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160032	0	0	0	0	160023	6	1	32	35	0	0	5110	0	3	16	3	3	80037	1	80000	10	6	160000	80100	80041	80041	80041	80041	80041
160204	80040	643	0	0	0	0	0	0	0	0	0	0	38	0	0	1	1	0	80025	2	12	12	11	25	240100	80100	160000	80100	0	160000	2040250	3672670	0	0	80015	80040	80279	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160032	0	0	0	32	160032	6	1	31	35	0	0	5126	0	3	16	2	3	80037	1	80000	0	0	160000	80100	80041	80041	80041	80041	80041
160204	80155	643	0	0	0	0	0	0	0	0	0	0	37	0	0	0	0	0	80025	2	12	12	15	25	240100	80100	160000	80100	0	160000	2040097	3672670	0	0	80015	80040	80040	59953	3	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160033	0	0	0	31	160032	6	1	32	35	0	0	5110	0	3	16	3	3	80037	0	80000	10	6	160000	80100	80041	80041	80041	80041	80041
160204	80040	643	0	0	0	0	0	0	0	1	0	0	44	0	0	0	1	0	80025	1	12	12	0	25	240100	80100	160000	80100	0	160166	1983561	3675988	0	0	80015	80040	80158	59953	11	59998	240100	200	160000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160148	0	0	0	33	160032	6	1	23	35	0	0	5110	0	3	25	3	3	80037	1	80000	0	6	160000	80100	80041	80041	80041	80158	80041
160204	80040	643	0	0	1	0	0	0	0	0	0	0	53	0	0	0	1	0	80025	2	12	12	15	50	240100	80163	160000	80100	0	160000	2006800	3679325	0	0	80414	80040	80040	59953	3	59999	240100	200	160000	200	240252	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160000	0	0	0	34	160032	6	1	23	27	0	0	5110	0	3	16	3	3	80037	1	80000	0	6	160000	80100	80042	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
160025	80042	620	0	0	0	0	0	0	0	0	67	598	0	1	80025	2	16	27	23	51	240010	80010	160000	80010	160000	2032689	3666035	1	80370	80414	80411	60296	3	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	50	160046	62	0	47	160031	6	1	46	0	0	5020	0	37	16	13	35	80037	0	80000	10	6	160000	80010	80041	80041	80041	80041	80042
160024	80040	610	0	0	0	0	1	0	0	0	37	0	0	1	80025	12	17	26	11	25	240010	80010	160000	80010	160000	2020546	3659642	0	80015	80040	80040	59975	3	60020	240010	20	160000	20	240000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	1	10	160000	0	27	160046	0	0	32	160012	6	1	23	40	0	5020	0	35	16	36	35	80037	0	80000	10	6	160000	80010	80041	80041	80041	80042	80041
160024	80040	599	0	0	0	0	0	0	0	0	52	0	0	1	80025	12	12	27	16	25	240010	80010	160000	80010	160000	1992622	3672629	0	80015	80041	80040	59975	3	60020	240010	20	160000	20	240000	80041	80120	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	53	160031	0	0	49	160036	6	1	32	40	0	5020	0	37	16	26	38	80037	0	80000	10	10	160000	80010	80043	80043	80041	80041	80043
160024	80040	621	0	0	0	0	0	0	0	0	56	0	0	1	80027	13	7	17	20	25	240010	80010	160000	80010	160000	2031425	3662759	0	80017	80042	80040	59978	3	60023	240010	20	160000	20	240000	80042	80042	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	53	160050	0	0	31	160050	6	1	50	43	0	5020	0	37	16	15	37	80042	0	80000	10	10	160000	80010	80041	80041	80043	80041	80043
160024	80042	620	0	0	0	0	0	0	0	0	149	0	0	1	80025	13	7	18	20	25	240010	80010	160000	80010	160000	2012385	3662815	0	80017	80042	80042	59976	3	60020	240010	20	160000	20	240000	80042	80042	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	53	160050	1	0	53	160050	6	0	49	43	0	5020	19	33	16	37	35	80037	1	80000	10	0	160000	80010	80041	80041	80042	80041	80041
160024	80040	620	0	0	0	0	1	1	0	0	37	0	0	1	80026	12	16	0	16	25	240010	80010	160000	80010	160000	2016803	3662736	0	80015	80040	80040	59975	3	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	50	160012	0	0	50	160046	6	0	46	40	0	5020	0	36	16	36	18	80037	1	80000	10	6	160000	80010	80041	80041	80042	80041	80041
160024	80040	621	0	0	0	0	0	0	0	0	38	0	0	1	80025	12	12	26	16	25	240010	80010	160000	80010	160000	2032486	3672670	0	80015	80041	80040	59976	3	60021	240010	20	160000	20	240000	80040	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	50	160046	0	0	17	160024	0	1	26	40	0	5020	0	13	16	35	19	80038	0	80000	10	6	160000	80010	80041	80041	80041	80042	80041
160024	80040	621	0	0	0	0	0	0	0	0	38	0	0	1	80025	12	12	27	16	25	240010	80010	160000	80010	160000	1993070	3672629	0	80016	80040	80041	59975	3	60021	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	0	160047	0	0	47	160047	6	0	12	40	0	5020	0	48	169	35	17	80039	0	80000	6	10	160000	80010	80041	80041	80041	80041	80041
160024	80040	621	0	0	0	0	1	1	0	0	169	0	0	1	80025	2	12	26	20	25	240010	80010	160000	80010	160000	2017779	3679323	0	80015	80041	80040	59975	38	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	50	160046	1	0	46	160046	6	0	47	40	0	5020	0	35	16	33	21	80037	0	80000	6	6	160000	80010	80041	80041	80041	80041	80041
160024	80040	621	0	0	0	0	0	0	0	0	38	0	0	1	80026	12	12	26	11	25	240010	80010	160000	80094	160000	2012569	3667451	0	80016	80041	80160	59976	3	60020	240010	20	160000	20	240000	80040	80040	1	1	80021	10	9	0	10	10	80000	80000	0	10	160000	0	35	160032	0	0	31	160046	6	1	46	40	0	5020	0	32	16	32	19	80041	1	80000	0	6	160000	80010	80041	80041	80041	80041	80041

LD1 (multiple, post-index, 2 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations