Firestorm: LD1 (multiple, post-index, 3 regs, 16B) measurements

Code:

  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5e	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29465	237	4	1	3	1	0	0	0	1	1	0	0	28	0	1	0	4601	29031	1	0	3	24015	4000	1000	3000	1000	3000	5000	15000	0	16	1	0	16166	28803	29483	3	10	4000	3000	4000	29319	29310	1	1	61001	1000	1000	1	3004	4	0	3008	0	0	8	3007	5	1	4	9	3	2	0	13256	9441	6932	3153	0	54	20711	3362	3807	11	56	58	28684	1000	16542	13583	15148	3000	1000	29389	29478	29363	29376	29331
63004	29465	237	1	1	0	1	0	1	0	1	0	0	0	16	0	0	0	4787	28993	0	0	0	24198	4000	1000	3000	1000	3000	5000	15000	0	10	0	0	16141	28828	29372	3	10	4000	3000	4000	29208	29296	1	1	61001	1000	1000	0	3004	4	9	3012	0	1	11	3007	0	0	3	12	3	1	0	13253	9574	6874	3136	1	54	20743	3289	3809	12	48	57	28618	1000	16182	13648	14888	3000	1000	29426	29345	29442	29418	29359
63004	29391	236	1	1	1	0	0	1	0	1	1	0	0	16	0	0	0	4683	28963	0	3	1	24017	4000	1000	3000	1000	3000	5000	15000	0	9	0	0	16166	28748	29570	3	10	4000	3000	4000	29219	29264	1	1	61001	1000	1000	0	3003	3	0	3003	0	1	7	3000	0	0	3	12	3	2	0	13148	9398	6935	3143	1	55	20751	3163	3803	18	59	54	28556	1000	16221	13312	14986	3000	1000	29298	29403	29391	29336	29359
63004	29376	236	0	1	1	1	0	0	1	1	0	0	0	16	0	0	0	4642	29004	1	3	0	24201	4000	1000	3000	1000	3000	5000	15003	0	7	0	0	16182	28880	29405	3	10	4000	3000	4000	29271	29158	1	1	61001	1000	1000	0	3004	4	0	3012	0	1	15	3004	5	1	11	12	3	1	0	12993	9595	6949	3176	2	47	20809	3196	3810	19	49	56	28607	1000	16234	13396	15026	3000	1000	29458	29549	29446	29440	29497
63004	29500	236	2	1	1	1	0	0	1	1	1	0	0	28	0	0	0	4629	28978	1	3	1	24208	4000	1000	3000	1000	3000	5000	15004	0	4	0	0	16152	28876	29456	3	10	4000	3000	4000	29183	29321	1	1	61001	1000	1000	0	3003	5	9	3003	0	0	10	3000	0	1	11	12	3	1	0	13214	9305	6901	3088	0	53	20704	3311	3812	22	52	51	28624	1000	16361	13657	14938	3000	1000	29330	29447	29371	29478	29491
63004	29497	236	2	1	0	0	0	1	1	1	1	0	0	13	0	0	0	4502	28940	0	0	3	24199	4000	1000	3000	1000	3000	5000	15004	0	5	0	0	16140	28870	29369	3	10	4000	3000	4000	29016	29382	2	1	61001	1000	1000	0	3003	3	0	3010	1	0	5	3004	0	0	7	9	3	1	0	13171	9501	6943	3150	0	59	20891	3264	3811	18	51	53	28613	1000	16208	13331	15014	3000	1000	29429	29445	29444	29488	29320
63004	29490	237	0	1	1	1	0	0	1	1	1	0	0	16	0	0	0	4683	28938	1	0	1	24232	4000	1000	3000	1000	3000	5000	15000	0	6	0	0	16166	28878	29384	3	10	4000	3000	4000	29183	29364	1	1	61001	1000	1000	0	3005	4	12	3003	0	0	4	3000	5	1	3	0	3	2	0	13129	9371	6957	3135	0	59	20738	3298	3810	13	56	55	28619	1000	16155	13372	15081	3000	1000	29556	29592	29429	29325	29384
63004	29444	236	0	1	1	1	0	1	1	1	1	0	0	26	0	0	0	4747	28976	0	0	0	24242	4000	1000	3000	1000	3000	5000	15000	0	5	0	0	16147	28712	29472	3	10	4000	3000	4000	29334	29312	1	1	61001	1000	1000	0	3003	4	9	3012	0	1	7	3001	5	1	4	9	3	1	0	13097	9262	6947	3140	0	57	20703	3232	3808	17	49	62	28668	1000	16234	13466	14833	3000	1000	29460	29424	29489	29454	29538
63004	29426	237	0	1	0	0	0	1	1	0	1	0	0	25	0	0	0	4679	29030	0	0	0	24265	4000	1000	3000	1000	3000	5000	15003	0	6	0	0	16155	28808	29407	3	10	4000	3000	4000	29394	29340	1	1	61001	1000	1000	0	3004	4	9	3011	0	0	4	3007	5	1	3	6	3	0	0	13235	9249	6930	3145	0	56	20827	3274	3811	18	53	52	28700	1000	16209	13403	14839	3000	1000	29443	29483	29375	29439	29388
63004	29507	236	1	1	1	0	0	0	0	1	0	0	0	10	0	0	0	4643	28991	0	1	0	24188	4000	1000	3000	1000	3000	5000	15000	0	6	1	0	16167	28850	29431	3	10	4000	3000	4000	29260	29256	1	1	61001	1000	1000	0	3003	3	12	3005	0	0	8	3007	5	1	3	12	3	1	0	13286	9407	6979	3129	0	63	20678	3222	3815	13	56	58	28639	1000	16101	13505	15194	3000	1000	29442	29552	29414	29503	29433

Count: 8

Code:

  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80079	620	0	1	0	1	1	0	0	46	0	0	0	2	80049	2	6	0	19	25	320100	80100	240000	80100	240000	661398	3490773	1	0	80042	80064	80072	49991	3	50025	320100	200	240000	200	320000	80069	80067	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240041	0	0	41	240041	0	1	41	43	0	5110	1	16	1	1	80061	80000	14	10	240000	80100	80065	80065	80065	80065	80066
240204	80064	620	0	1	0	1	1	0	0	46	0	0	0	2	80049	2	0	17	20	25	320100	80100	240000	80100	240000	678470	3522214	0	0	80039	80201	80064	49989	3	50022	320100	200	240000	200	320256	80045	80062	2	1	80201	100	99	0	100	100	80000	80000	0	100	240000	2	43	34	240000	0	0	0	240040	5	1	40	0	0	5110	1	25	1	1	80061	80000	14	14	240000	80100	80057	80202	80456	80046	80888
240204	80048	621	0	1	0	0	0	0	0	178	0	0	0	2	80049	2	6	6	20	52	320100	80100	240130	80100	240000	1013698	3501497	0	0	80040	80064	80064	50090	3	50022	320362	200	240000	200	320000	80064	80217	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	45	0	240132	0	0	41	240040	5	1	40	0	0	5110	1	16	1	1	80205	80000	14	15	240000	80100	80068	80065	80224	80067	80065
240204	80064	621	0	1	0	0	0	0	0	177	0	0	0	2	80049	2	6	6	19	25	320100	80100	240000	80100	240178	678470	3522214	0	1	80039	80064	80045	49987	3	50031	320100	200	240000	200	320000	80221	80045	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	2	45	30	240041	0	0	850	240041	0	1	40	45	0	5124	1	24	1	1	80063	80000	0	0	240000	80100	80221	80046	80046	80046	80201
240204	80203	621	0	0	0	1	0	0	0	46	0	0	0	2	80209	2	6	6	0	25	320291	80100	240000	80161	240000	678348	3507375	0	0	80171	80220	80064	49987	3	50022	320100	200	240000	200	320000	80045	80065	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240041	0	0	41	240042	6	1	42	44	0	5110	1	16	1	1	80061	80000	14	16	240000	80100	80065	80066	80065	80065	80065
240204	80064	620	0	1	0	1	0	0	0	46	0	0	0	2	80049	2	0	6	20	25	320100	80100	240000	80100	240000	667323	3522214	0	0	80039	80065	80065	49987	3	50023	320100	200	240000	200	320000	80064	80061	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240000	0	10	3	240041	0	1	40	44	0	5110	1	16	1	1	80062	80000	15	14	240000	80100	80065	80065	80065	80046	80222
240204	80204	620	0	1	1	1	0	0	1	179	0	0	0	2	80045	2	3	6	19	54	320100	80100	240000	80179	240000	622428	3524326	0	0	80039	80228	80064	49987	11	50401	320352	200	240000	200	320000	80157	80060	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240041	0	2	44	240040	5	0	40	45	0	5110	1	16	1	1	80071	80000	0	10	240000	80100	80069	80065	80071	80072	80070
240204	80069	643	0	0	0	0	0	0	0	67	0	0	0	0	80038	2	17	17	28	25	320100	80100	240130	80100	240000	632150	3479226	0	0	80039	80045	80062	49987	3	50022	320100	200	245566	200	320000	80049	80061	1	1	80201	100	99	1	100	100	80000	80000	0	100	240000	0	36	0	240040	0	2	839	240040	5	1	33	0	0	5110	1	16	1	1	80056	80000	9	6	240000	80100	80227	80065	80061	80049	80049
240204	80049	643	0	0	0	0	0	0	1	57	0	0	0	2	80051	0	17	17	15	25	320291	80100	240000	80100	240000	610121	3492333	0	0	80039	80064	80063	49987	3	50025	320100	200	240000	200	320000	80052	80218	1	1	80201	100	99	0	100	100	80000	80000	0	100	240130	0	36	0	240040	0	1	3	240040	5	1	33	43	0	5110	1	16	1	1	80062	80000	10	6	240000	80100	80049	80050	80068	80222	80065
240204	80065	644	0	0	0	0	0	7	30	57	0	0	0	2	80049	0	0	0	18	25	320294	80100	240000	80170	240199	662644	3538167	1	0	80035	80061	80068	49974	3	50022	320100	200	240000	200	320000	80221	80059	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	36	0	240130	0	1	40	240041	5	1	40	43	0	5124	1	16	1	1	80045	80000	0	10	240000	80100	80050	80069	80227	80050	80049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80070	620	1	0	0	0	0	0	0	0	0	16	0	0	0	0	3	80049	2	18	17	16	25	320010	80010	240000	80010	240000	676539	3519175	80040	80066	80065	50011	3	50045	320010	20	240000	20	320000	80066	80056	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	36	0	240054	0	0	0	33	240040	5	1	33	43	0	0	0	5020	5	16	0	5	5	80063	80000	9	6	240000	80010	80066	80067	80062	80061	80061
240024	80061	621	0	0	0	0	0	0	0	0	0	45	0	0	0	0	2	80051	3	19	17	18	25	320010	80010	240000	80010	240000	671069	3501161	80030	80055	80060	50010	3	50026	320010	20	240000	20	320000	80079	80066	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	0	0	240040	0	0	0	40	240041	0	1	54	42	0	0	0	5020	5	16	0	4	5	80057	80000	10	9	240000	80010	80061	80063	80067	80062	80046
240024	80060	620	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	80030	0	17	17	16	25	320010	80010	240000	80010	240000	638462	3522027	80035	80065	80045	49993	3	50035	320010	20	240000	20	320000	80059	80055	1	1	80021	10	9	10	10	80000	80000	0	10	240014	16	43	0	240054	0	1	0	57	240039	5	0	40	43	0	0	0	5020	4	17	0	5	4	80067	80000	6	6	240000	80010	80061	80063	80061	80067	80062
240024	80060	620	1	0	0	0	0	0	0	0	0	45	0	0	0	0	2	80049	2	17	0	16	25	320010	80010	240000	80010	240000	778485	3507089	80040	80069	80061	50006	3	50041	320010	20	240000	20	320000	80061	80059	1	1	80021	10	9	10	10	80000	80000	0	10	240000	14	36	0	240040	0	0	0	33	240040	5	1	32	43	14	0	0	5020	4	16	0	4	4	80052	80000	10	0	240000	80010	80067	80061	80062	80056	80066
240024	80066	621	1	0	0	0	0	0	0	0	0	73	0	1	0	0	2	80046	3	18	17	18	25	320010	80010	240000	80010	240000	676539	3486748	80035	80065	80065	50006	3	50045	320010	20	240000	20	320000	80065	80049	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	35	0	240054	0	0	0	43	240041	5	1	14	44	0	1	0	5020	5	15	0	7	6	80058	80000	9	10	240000	80010	80065	80067	80062	80067	80056
240024	80045	621	0	0	0	0	0	0	0	0	0	46	0	0	0	0	2	80032	3	17	17	16	25	320010	80010	240000	80010	240000	860834	3520776	80035	80060	80065	50006	3	50040	320010	20	240000	20	320000	80055	80065	1	1	80021	10	9	10	10	80000	80000	0	10	240014	14	43	0	240054	0	0	0	33	240040	5	1	54	44	0	0	0	5020	4	16	0	4	4	80057	80000	6	0	240000	80010	80068	80061	80066	80061	80062
240024	80061	620	1	0	1	0	0	0	0	0	0	45	0	0	0	0	0	80040	2	0	17	0	25	320010	80010	240000	80010	240000	653701	3487120	80044	80045	80064	50011	3	50040	320010	20	240000	20	320000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	240014	0	43	0	240000	0	1	0	56	240040	5	0	33	36	14	1	0	5020	5	16	0	4	4	80066	80000	10	10	240000	80010	80068	80061	80071	80070	80062
240025	80050	621	1	0	0	0	0	0	0	0	0	38	0	0	0	1	2	80046	2	18	18	15	25	320010	80010	240000	80010	240000	671880	3507089	80040	80070	80060	50000	3	50046	320010	20	240000	20	320000	80060	80049	1	1	80021	10	9	10	10	80000	80000	0	10	240000	14	35	0	240054	0	0	0	34	240000	5	1	33	43	14	0	0	5020	9	16	0	5	4	80058	80000	10	0	240000	80010	80066	80062	80061	80061	80066
240024	80065	620	0	0	0	0	0	0	0	0	0	62	0	0	0	1	3	80049	2	18	17	16	53	320010	80010	240000	80010	240000	647117	3489254	80030	80060	80047	49990	3	50046	320010	20	240000	20	320000	80069	80059	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240054	0	1	0	39	240040	6	1	32	43	0	0	0	5020	3	16	0	5	4	80052	80000	9	6	240000	80010	80063	80067	80062	80061	80061
240024	80061	621	0	0	0	0	1	0	0	0	0	57	0	0	0	0	2	80054	2	14	17	15	25	320010	80010	240000	80010	240000	979245	3487120	80036	80060	80061	50006	3	50044	320010	20	240000	20	320000	80061	80065	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	43	0	240040	2	0	0	40	240040	5	1	54	44	0	0	1	5020	5	16	0	5	5	80057	80000	9	9	240000	80010	80070	80067	80067	80065	80061

LD1 (multiple, post-index, 3 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations