Firestorm: LD1 (multiple, post-index, 3 regs, 1D) measurements

Code:

  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29357	236	0	3	0	0	1	0	1	1	0	0	7	0	1	0	0	4651	28699	0	2	1	24066	3000	1000	2000	1000	2000	5000	10001	16	0	0	16113	28554	29288	3	10	3000	3000	3000	29040	29095	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	3	2002	4	2	6	0	0	0	13122	9524	6883	3066	1	70	20617	3295	3801	45	62	59	28481	1000	16179	13438	14841	2000	1000	1000	29287	29226	29276	29416	29281
63004	29276	236	0	0	0	0	0	0	0	1	0	0	7	0	0	0	0	4617	28669	0	2	1	24096	3000	1000	2000	1000	2000	5000	10002	15	0	0	16141	28491	29223	3	10	3000	3000	3000	29080	29066	1	1	61001	1000	1000	0	2000	0	5	2002	0	0	0	2002	4	2	6	0	0	0	13057	9097	6889	3180	0	66	20703	3311	3815	45	58	60	28383	1000	15915	13517	14772	2000	1000	1000	29281	29317	29279	29229	29382
63004	29239	235	0	1	0	0	0	0	0	1	0	0	4	0	0	0	0	4638	28657	0	2	1	24263	3000	1000	2000	1000	2000	5000	10002	10	0	0	16127	28576	29311	3	10	3000	3000	3000	29139	28973	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2	2002	4	2	6	0	0	0	12965	9245	6930	3189	2	75	20530	3278	3805	47	60	59	28393	1000	16119	13275	14980	2000	1000	1000	29295	29355	29280	29188	29296
63004	29245	235	0	0	0	0	0	0	0	1	0	0	10	0	0	0	0	4536	28726	0	2	1	24085	3000	1000	2000	1000	2000	5000	10000	18	0	0	16115	28606	29275	3	29	3000	3000	3000	29035	29143	1	1	61001	1000	1000	0	2000	0	6	2002	0	0	2	2002	2	2	6	0	0	0	13268	9145	6830	3195	0	68	20683	3278	3805	49	56	56	28480	1000	15889	13473	14895	2000	1000	1000	29197	29302	29186	29192	29254
63004	29166	235	0	0	0	0	1	0	1	1	0	0	138	0	0	0	0	4733	28642	0	2	2	24104	3000	1000	2000	1000	2000	5000	10002	9	0	0	16105	28564	29320	3	10	3000	3000	3000	29082	28989	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	0	2002	4	2	4	0	0	0	13126	9341	6871	3135	0	72	20665	3267	3806	44	61	64	28456	1000	16140	13593	14906	2000	1000	1000	29370	29267	29333	29351	29241
63004	29057	234	0	0	0	0	0	0	0	0	0	0	10	0	0	0	0	4622	28629	0	2	2	24004	3000	1000	2000	1000	2000	5000	10000	11	0	0	16132	28684	29327	3	10	3000	3000	3000	29161	28933	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2	2002	4	2	6	0	0	0	13163	9467	6850	3167	0	73	20576	3294	3808	45	56	65	28545	1000	15961	13344	14867	2000	1000	1000	29217	29226	29226	29290	29360
63004	29243	235	0	1	0	0	0	0	0	0	0	0	7	0	0	0	0	4737	28690	0	2	1	24101	3000	1000	2000	1000	2000	5000	10001	10	0	0	16120	28610	29267	3	10	3000	3000	3000	29055	29026	1	1	61001	1000	1000	0	2000	0	4	2002	1	0	3	2006	4	2	6	0	0	0	13055	9389	6924	3126	0	70	20587	3225	3804	39	59	55	28566	1000	16054	13392	14936	2000	1000	1000	29148	29173	29299	29281	29254
63004	29335	234	0	0	0	0	0	0	0	0	0	0	7	0	0	0	0	4573	28671	0	0	1	24156	3000	1000	2000	1000	2000	5000	10002	13	0	0	16091	28617	29363	3	10	3000	3000	3000	29036	29108	1	1	61001	1000	1000	0	2000	0	4	2002	0	0	2	2002	4	2	0	0	0	0	12997	9220	6893	3082	0	70	20644	3233	3805	42	55	65	28375	1000	15911	13488	14753	2000	1000	1000	29315	29200	29325	29358	29271
63004	29153	234	0	0	0	0	1	0	0	0	0	0	7	0	0	0	0	4666	28675	0	2	2	24150	3000	1000	2000	1000	2000	5000	10002	5	0	0	16132	28626	29196	3	10	3000	3000	3000	29004	28997	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	2	2002	4	2	6	0	0	0	13086	9176	6904	3175	0	67	20531	3292	3810	46	54	56	28502	1000	15986	13719	14996	2000	1000	1000	29265	29337	29345	29246	29239
63004	29275	235	0	0	0	0	0	0	0	0	0	0	7	0	0	0	0	4695	28610	0	1	2	24146	3000	1000	2000	1000	2000	5000	10004	15	0	0	16104	28575	29256	3	10	3000	3000	3000	29024	29067	1	1	61001	1000	1000	0	2000	0	4	2000	1	0	3	2002	4	2	6	0	0	0	13123	9334	6871	3169	0	67	20664	3290	3804	51	62	59	28499	1000	16045	13654	14834	2000	1000	1000	29226	29094	29229	29147	29319

Count: 8

Code:

  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80040	643	0	0	0	0	0	0	0	0	125	0	0	0	0	80025	2	12	12	12	25	240100	80100	160000	80100	160000	2052958	3675995	0	80015	80040	80040	49954	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	27	160024	0	0	24	160000	6	1	23	35	0	0	0	0	5110	1	16	1	1	80037	1	80000	10	0	0	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	643	0	0	0	0	0	0	0	0	936	0	0	0	1	80026	2	12	12	0	25	240100	80100	160000	80100	160000	2070175	3675995	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	27	160031	0	0	32	160000	6	1	24	27	0	0	0	0	5110	1	25	1	1	80037	0	80000	10	10	0	160000	80000	80100	80041	80041	80041	80042	80041
240204	80040	643	0	0	0	0	0	0	0	0	500	0	1	0	0	80025	2	12	12	15	25	240100	80100	160000	80100	160000	2064876	3672672	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160032	0	0	32	160032	6	0	24	0	0	0	0	0	5110	1	16	2	2	80037	0	80000	0	0	0	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	643	0	0	0	0	0	0	0	0	641	0	0	0	1	80025	2	12	12	0	25	240100	80100	160000	80100	160000	2065067	3669344	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160032	0	0	35	160033	6	1	24	35	0	0	0	0	5110	1	16	1	1	80038	1	80000	6	7	0	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	643	0	0	0	0	0	0	0	0	571	0	0	0	0	80025	2	12	12	11	25	240100	80100	160000	80100	160000	2061496	3646101	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160023	0	0	26	160033	6	1	23	35	0	0	0	0	5110	1	16	1	1	80037	1	80000	6	6	0	160000	80000	80100	80042	80041	80041	80041	80041
240204	80040	642	0	0	0	0	1	0	0	0	1019	0	0	0	1	80025	2	12	12	15	25	240100	80100	160000	80100	160000	2060782	3669470	0	80015	80040	80041	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160032	0	0	35	160000	6	1	35	35	0	0	0	1	5110	1	16	1	1	80038	1	80000	6	6	0	160000	80000	80100	80041	80041	80042	80041	80041
240204	80040	643	0	0	0	0	0	0	0	0	1008	0	0	0	0	80025	2	12	12	13	25	240100	80100	160000	80100	160000	2050044	3672664	0	80015	80162	80040	49954	18	49998	240100	200	240249	200	240000	80161	80040	1	1	80201	100	99	100	100	80000	80000	1	100	160000	0	39	160032	0	0	32	160147	6	1	24	35	0	0	0	0	5110	1	16	1	1	80114	0	80000	10	6	0	160000	80000	80100	80042	80041	80041	80164	80041
240204	80040	642	0	0	0	0	0	0	0	1	1005	0	0	0	1	80025	2	12	12	11	25	240100	80100	160000	80100	160164	2025384	3665518	0	80015	80040	80040	50008	3	49998	240100	200	240000	202	240000	80040	80163	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	27	160000	0	0	0	160000	6	1	32	0	0	2	0	0	5110	1	16	1	1	80037	0	80065	0	6	0	160000	80000	80100	80041	80041	80041	80163	80041
240204	80040	643	0	0	2	0	0	1	0	1	1026	0	1	0	0	80025	2	12	12	55	25	240100	80174	160000	80100	160000	2044958	3646101	0	80015	80040	80162	49954	3	50081	240100	200	240248	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160232	7	0	160147	0	0	821	160113	6	1	24	35	0	7	0	0	5171	1	61	2	3	80636	0	80207	12	10	0	160000	80000	80100	80402	80286	80407	80289	80407
240204	80282	647	0	0	0	0	0	0	6	5	1333	528	0	0	0	80390	2	12	0	220	181	241041	80492	160613	80524	160966	2072933	3702166	0	80015	80139	80040	49953	18	49998	240100	200	240249	200	240000	80163	82580	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	0	160000	0	0	24	160031	6	1	0	35	0	0	21	0	5445	1	16	6	2	80037	0	81542	10	7	880	160000	80000	80100	81390	82602	80261	80041	87111

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80040	642	1	0	0	0	0	1	0	0	0	59	0	0	0	2	80025	2	16	16	19	25	240010	80010	160000	80010	160000	2050106	3672662	0	0	80018	80040	80040	49976	3	50020	240010	20	240000	20	240000	80040	80044	1	1	80021	10	9	10	10	80000	80000	1	10	160013	12	42	160050	0	0	0	50	160038	0	6	1	52	42	13	0	5020	0	0	2	16	0	2	2	80037	0	80000	6	6	160000	80000	80010	80041	80045	80044	80041	80041
240024	80040	643	1	0	0	0	0	1	1	0	0	75	0	0	0	2	80028	16	15	29	24	25	240010	80010	160000	80010	160000	2042373	3669453	0	0	80018	80040	80040	49976	3	50021	240010	20	240000	20	240000	80043	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160012	14	41	160067	0	0	0	69	160054	0	6	1	66	42	12	0	5020	0	0	2	16	0	2	2	80037	0	80000	6	9	160000	80000	80010	80044	80041	80044	80044	80044
240024	80043	643	1	0	0	0	0	0	0	0	0	67	0	0	0	2	80025	16	13	16	19	25	240010	80010	160000	80010	160000	2058429	3672561	0	0	80018	80040	80044	49979	3	50021	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160013	13	57	160067	1	0	0	50	160039	0	6	0	66	41	13	0	5020	0	0	2	16	0	2	2	80041	0	80000	6	9	160000	80000	80010	80042	80044	80042	80041	80041
240024	80043	643	1	0	0	0	0	0	0	0	0	64	0	1	0	2	80025	17	0	16	17	25	240010	80010	160000	80010	160000	2057301	3672660	0	0	80018	80040	80040	49976	3	50020	240010	20	240000	20	240000	80043	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160013	13	42	160051	1	0	0	51	160038	0	6	1	50	43	13	1	5020	0	0	3	16	0	3	3	80040	0	80000	6	9	160000	80000	80010	80044	80045	80041	80044	80778
240024	80040	642	1	0	0	0	1	0	0	0	0	62	88	1	0	2	80028	2	15	16	17	25	240010	80010	160000	80010	160000	2047183	3665789	0	0	80019	80040	80040	49976	3	50024	240010	20	240000	20	240000	80043	80043	1	1	80021	10	9	10	10	80000	80000	0	10	160013	13	42	160050	0	0	0	52	160038	0	6	1	65	43	12	1	5051	0	0	3	16	0	2	3	80040	0	80000	6	9	160000	80000	80010	80041	80045	80045	80045	80041
240024	80040	642	1	0	0	0	0	0	0	0	0	58	0	0	0	2	80028	3	16	29	16	25	240010	80010	160000	80010	160000	2048565	3659646	0	0	80018	80044	80040	49979	3	50106	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160013	12	57	160053	0	1	1	65	160040	0	6	1	38	43	13	0	5020	0	0	3	16	0	3	2	80037	0	80000	6	6	160000	80000	80010	80041	80041	80041	80044	80044
240024	80043	643	1	0	0	0	1	0	0	0	0	73	0	0	0	2	80028	2	15	29	63	25	240010	80010	160000	80010	160000	2057950	3672653	0	0	80018	80040	80040	49976	3	50020	240010	20	240000	20	240000	80040	80043	1	1	80021	10	9	10	10	80000	80000	0	10	160014	14	57	160052	0	0	1	867	160054	0	6	1	66	42	13	1	5020	0	0	3	16	0	2	2	80037	0	80062	9	6	160000	80000	80010	80044	80041	80044	80041	80045
240024	80043	643	1	0	0	0	0	0	0	0	0	57	0	0	0	2	80029	16	15	16	20	25	240010	80010	160000	80010	160000	2037039	3659387	0	0	80018	80041	80040	50014	3	50020	240010	20	240000	20	240000	80043	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160014	14	42	160050	0	0	1	52	160039	0	6	1	50	41	13	1	5020	0	0	2	15	0	2	2	80040	0	80000	6	9	160000	80000	80010	80045	80041	80041	80041	80041
240024	80040	643	1	0	0	0	0	0	0	0	0	85	0	0	0	2	80152	17	15	29	15	25	240010	80010	160000	80010	160000	2037519	3666151	0	0	80018	80040	80041	49979	3	50020	240010	20	240247	20	240000	80043	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160014	12	41	160067	0	1	0	50	160053	0	6	1	50	43	13	0	5020	0	0	2	16	0	3	3	80041	0	80000	6	9	160000	80000	80010	80041	80044	80044	80044	80041
240024	80043	643	1	0	0	0	0	0	0	0	0	72	0	0	0	2	80029	3	16	29	17	25	240010	80010	160000	80010	160000	2047183	3672666	0	0	80018	80040	80040	49975	3	50020	240010	20	240000	20	240000	80043	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160012	13	57	160066	3	1	1	66	160039	0	6	1	50	43	13	6	5020	0	0	2	16	0	2	2	80037	0	80000	6	6	160000	80000	80010	80042	80045	80041	80041	80045

LD1 (multiple, post-index, 3 regs, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations