Firestorm: LD1 (multiple, post-index, 3 regs, 2D) measurements

Code:

  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29627	238	26	0	17	0	0	0	0	0	99	0	0	0	0	4587	28957	0	3	3	24017	4000	1000	3000	1000	3000	5000	15004	9	0	0	16149	28759	29576	3	10	4000	3000	4000	29367	29297	1	1	61001	1000	1000	0	3000	0	9	3000	0	0	4	3000	5	1	0	9	0	0	13213	9298	6896	3112	9	58	20742	3355	3822	20	50	49	28659	0	1000	16084	13486	14784	3000	1000	29431	29253	29359	29434	29445
63004	29410	236	21	0	12	0	0	0	0	0	411	0	1	0	0	4621	28917	0	0	3	24170	4000	1000	3000	1000	3000	5000	15001	7	0	0	16156	28733	29482	3	10	4000	3000	4000	29285	29251	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	4	3006	5	1	4	0	0	0	13179	9264	6894	3218	5	52	20673	3181	3820	24	49	52	28636	0	1000	16076	13557	14779	3000	1000	29351	29430	29402	29443	29372
63004	29452	237	17	0	20	0	0	0	0	0	513	0	0	0	0	4657	28939	0	2	0	24215	4000	1000	3000	1000	3000	5000	15000	0	0	0	16142	28901	29499	3	10	4000	3000	4000	29256	29258	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	0	3004	5	0	4	9	0	0	13155	9357	6916	3191	7	54	20738	3337	3817	17	54	53	28674	0	1000	16005	13565	15148	3000	1000	29474	29350	29390	29408	29462
63004	29454	237	19	0	17	0	0	0	0	0	543	0	0	0	0	4687	29052	0	0	0	24268	4000	1000	3000	1000	3000	5000	15000	0	0	0	16151	28721	29451	3	10	4000	3000	4000	29268	29311	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	0	3004	5	1	4	9	0	0	13266	9189	6972	3160	6	55	20777	3296	3820	14	48	57	28582	0	1000	16434	13521	15052	3000	1000	29436	29601	29457	29386	29361
63004	29454	237	14	0	20	0	0	0	0	0	609	0	1	0	0	4544	28960	0	3	0	24190	4000	1000	3000	1000	3000	5000	15004	2	0	0	16160	28737	29272	3	10	4000	3000	4000	29266	29311	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	4	3006	5	0	4	0	0	0	13309	9251	6912	3138	6	47	20698	3317	3823	24	55	54	28613	0	1000	16232	13572	15068	3000	1000	29466	29375	29453	29494	29367
63004	29590	237	19	0	14	0	0	0	0	0	531	0	1	0	0	4704	29024	0	0	0	24253	4000	1000	3000	1000	3000	5000	15004	1	0	0	16159	28855	29445	3	10	4000	3000	4000	29283	29293	1	1	61001	1000	1000	0	3000	0	0	3004	0	0	0	3000	5	1	0	9	0	0	13175	9498	6920	3167	6	54	20806	3314	3821	20	51	53	28753	0	1000	16354	13338	14920	3000	1000	29409	29315	29485	29460	29351
63004	29474	237	17	0	21	0	1	1	0	0	615	0	0	0	0	4712	29037	0	3	1	24258	4000	1000	3000	1000	3000	5000	15000	0	0	0	16146	28858	29416	3	10	4000	3000	4000	29206	29442	1	1	61001	1000	1000	0	3000	0	9	3004	0	0	0	3005	0	1	4	9	0	0	13107	9471	6952	3166	7	56	20772	3365	3829	15	53	49	28546	0	1000	15972	13209	14846	3000	1000	29331	29322	29469	29398	29382
63004	29460	236	18	0	15	0	0	0	0	0	492	0	0	0	0	4736	29009	0	0	1	24222	4000	1000	3000	1000	3000	5000	15000	5	0	0	16137	28842	29508	3	10	4000	3000	4000	29274	29306	1	1	61001	1000	1000	0	3000	0	0	3000	1	0	4	3001	0	0	4	9	0	0	13186	9407	6931	3202	6	55	20768	3265	3823	17	54	46	28587	0	1000	15954	13347	15214	3000	1000	29327	29389	29456	29566	29317
63004	29452	236	17	0	21	0	0	0	0	0	550	0	0	0	0	4689	29029	0	0	1	24222	4000	1000	3000	1000	3000	5000	15004	3	0	0	16147	28780	29490	3	10	4000	3000	4000	29281	29189	1	1	61001	1000	1000	0	3000	0	9	3000	0	0	0	3004	5	1	0	0	0	0	13416	9522	6961	3145	6	51	20751	3200	3826	17	52	46	28530	0	1000	16312	13370	15232	3000	1000	29291	29482	29438	29299	29464
63004	29441	237	17	0	26	0	0	0	0	0	585	0	1	0	0	4664	29047	0	0	0	24068	4000	1000	3000	1000	3000	5000	15003	5	0	9	16153	28762	29555	3	10	4000	3000	4000	29350	29295	1	1	61001	1000	1000	0	3000	2	9	3004	0	0	4	3004	5	1	4	9	0	0	13154	9463	6936	3130	10	52	20700	3269	3824	16	47	50	28619	0	1000	16133	13348	14931	3000	1000	29497	29412	29372	29384	29405

Count: 8

Code:

  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80083	620	0	0	0	1	0	0	0	0	0	0	46	0	0	0	2	80049	2	6	6	22	25	320100	80100	240000	80100	240000	678470	3522214	0	0	80040	80070	80060	49983	3	50022	320100	200	240189	200	320000	80060	80377	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240040	0	0	0	851	240041	5	1	40	44	0	0	0	5110	1	16	1	1	80062	80000	14	10	240000	80100	80065	80069	80065	80065	80065
240204	80064	620	0	0	0	0	0	0	0	0	0	0	45	0	0	0	1	80049	2	17	6	0	25	320100	80100	240000	80184	240000	678470	3522214	0	0	80039	80067	80064	49987	3	50021	320100	202	240000	200	320000	80069	80069	1	1	80201	100	99	0	100	100	80000	80000	0	100	240014	15	44	0	240056	1	8	0	56	240000	6	1	54	44	14	0	0	5110	1	16	1	1	80066	80000	13	13	240000	80100	80070	80071	80070	80070	80070
240204	80074	620	1	0	0	0	0	0	0	0	0	0	16	0	0	0	2	80055	2	7	7	20	25	320100	80100	240000	80100	240000	668787	3498422	0	0	80044	80073	80069	49996	3	50027	320100	200	240000	200	320000	80073	80069	1	1	80201	100	99	0	100	100	80000	80000	0	100	240014	14	44	0	240054	0	0	0	60	240000	5	1	55	44	14	0	0	5110	1	16	1	1	80061	80000	14	14	240000	80100	80061	80061	80061	80061	80065
240204	80219	620	0	0	0	0	0	0	0	0	0	1	45	0	0	0	2	80049	2	6	6	22	25	320100	80100	240000	80100	240000	678470	3501497	1	0	80039	80060	80064	49987	3	50028	320100	200	240000	200	320000	80060	80069	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240041	0	1	0	964	240041	6	1	40	43	0	0	0	5110	1	16	1	3	80057	80000	0	10	240000	80100	80065	80221	80061	80067	80065
240204	80061	620	0	0	0	0	0	0	0	0	0	0	45	0	0	0	2	80050	2	6	17	20	25	320100	80100	240000	80100	240000	678470	3501578	0	0	80040	80221	80064	49987	3	50022	320100	200	240000	200	320000	80068	80069	2	1	80201	100	99	0	100	100	80000	80000	1	100	240000	0	43	0	240041	0	0	0	3	240040	0	1	40	44	0	0	0	5110	1	16	1	1	80067	80000	0	10	240000	80100	80062	80066	80065	80068	80065
240204	80064	620	0	0	0	0	0	0	0	0	0	0	46	0	0	0	2	80049	2	6	17	166	83	320291	80167	240130	80164	240178	711132	3519450	0	0	80175	80375	80377	50199	23	50147	320585	200	240577	200	320513	80376	80388	2	1	80201	100	99	0	100	100	80000	80000	0	100	240130	0	43	32	240300	0	0	7	825	240171	6	1	39	44	0	0	0	5124	0	25	1	2	80202	80066	10	10	240000	80100	80356	80224	80374	80202	80227
240204	80383	622	0	0	0	0	1	0	0	0	1	1	178	0	0	0	1	80162	0	17	6	166	53	320314	80246	240130	80298	240178	967572	3518067	0	0	80039	80220	80218	50186	25	50145	320342	200	240193	200	320257	80219	80200	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	44	0	240041	0	0	0	40	240041	6	1	40	44	0	0	0	5110	1	16	1	1	80057	80000	0	10	240000	80100	80065	80061	80065	80069	80061
240204	80064	620	0	0	0	0	0	0	0	0	0	0	46	0	0	0	1	80050	2	6	6	22	25	320100	80100	240000	80100	240000	678348	3495411	0	0	80039	80069	80060	49983	3	50018	320100	200	240000	200	320000	80060	80257	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240040	0	0	0	41	240040	5	1	40	44	0	0	0	5110	1	16	1	1	80065	80000	0	10	240000	80100	80065	80068	80065	80074	80065
240204	80064	621	0	0	0	0	0	0	0	0	0	0	45	0	0	0	2	80057	2	6	6	16	25	320100	80100	240000	80100	240000	678351	3507921	0	0	80039	80165	80064	49983	3	50022	320100	200	240000	200	320000	80064	80075	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240040	0	0	0	47	240039	5	1	40	44	0	0	0	5110	1	16	1	1	80063	80000	14	10	240000	80100	80066	80061	80069	80065	80065
240204	80064	620	0	0	0	0	0	0	0	0	0	0	45	0	0	0	2	80049	2	6	17	21	25	320100	80100	240000	80100	240000	622428	3522455	1	0	80039	80049	80060	49987	3	50018	320100	200	240000	200	320000	80060	80216	1	1	80201	100	99	0	100	100	80000	80000	0	100	240000	0	43	0	240040	0	0	0	40	240041	6	1	40	44	0	0	0	5110	1	16	1	1	80067	80000	10	10	240000	80100	80069	80066	80065	80066	80061

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80069	621	1	0	0	0	0	0	0	62	0	0	0	0	80054	2	7	7	19	25	320010	80010	240000	80010	240000	590542	3489717	0	80044	80076	80080	50015	3	50049	320010	20	240000	20	320000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240015	14	44	0	240055	1	0	1	60	240041	5	1	55	44	14	1	0	5020	31	16	31	13	80066	80000	14	13	240000	80010	80048	80070	80070	80055	80070
240024	80074	620	1	0	0	0	0	0	0	63	0	0	0	3	80062	3	7	7	19	25	320010	80010	240000	80010	240000	590542	3517413	0	80046	80082	80077	50015	3	50049	320010	20	240000	20	320000	80069	80073	1	1	80021	10	9	0	10	10	80000	80000	0	10	240015	15	44	0	240054	1	0	0	57	240041	5	1	56	44	14	1	0	5020	30	16	29	13	80160	80000	13	13	240000	80010	80070	80074	80048	80070	80070
240024	80047	620	1	0	0	0	0	0	0	63	0	0	0	2	80054	0	7	7	22	25	320010	80010	240000	80010	240000	652982	3489836	0	80048	80084	80069	50018	3	50031	320010	20	240000	20	320000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240014	14	0	0	240055	0	1	0	60	240000	0	1	14	44	14	0	0	5020	31	16	13	30	80066	80000	13	0	240000	80010	80070	80070	80048	80074	80070
240024	80047	621	1	0	0	0	0	0	0	62	0	0	0	2	80032	2	0	7	20	25	320010	80010	240000	80010	240000	679285	3489717	0	80045	80087	80075	50014	3	50049	320010	20	240000	20	320000	80069	80069	1	1	80021	10	9	1	10	10	80000	80000	0	10	240014	14	44	0	240055	0	0	0	16	240000	5	0	14	44	14	0	0	5020	28	16	28	30	80071	80000	13	13	240000	80010	80070	80070	80070	80074	80070
240024	80073	621	1	1	0	1	0	0	0	63	0	0	0	2	80395	2	7	7	19	25	320010	80010	240000	80010	240000	600366	3489717	0	80044	80061	80069	50018	3	50052	320010	20	240000	20	320000	80073	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240014	15	44	0	240053	0	1	1	56	240042	6	1	54	44	14	0	0	5020	26	16	28	13	80066	80000	0	13	240000	80010	80070	80070	80070	80074	80070
240024	80069	620	1	0	0	0	0	0	0	62	0	0	0	2	80054	2	7	7	20	25	320010	80010	240000	80010	240000	652982	3489717	0	80044	80065	80072	50014	3	50049	320010	20	240000	20	320000	80073	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240015	14	44	0	240055	0	0	1	56	240041	6	1	54	44	14	1	0	5020	13	16	29	30	80066	80002	13	13	240000	80010	80074	80070	80070	80074	80070
240024	80073	620	1	0	1	0	0	0	0	62	0	0	0	2	80036	2	7	7	21	25	320010	80010	240000	80010	240000	748725	3489446	0	80044	80086	80074	50015	3	50049	320010	20	240000	20	320000	80069	80048	1	1	80021	10	9	0	10	10	80000	80000	0	10	240016	14	43	0	240055	1	0	0	57	240041	5	1	55	44	14	0	0	5020	33	16	33	14	80066	80000	13	13	240000	80010	80070	80070	80070	80070	80074
240024	80048	620	1	0	0	0	0	0	0	63	0	0	0	1	80054	3	7	7	19	25	320010	80010	240000	80010	240000	649213	3517413	0	80022	80066	80169	50015	3	50051	320010	20	240000	20	320000	80071	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240014	14	44	0	240055	0	0	0	57	240000	6	1	54	44	14	0	0	5020	12	16	30	16	80066	80000	13	0	240000	80010	80070	80070	80070	80053	80084
240024	80069	620	1	0	0	0	0	0	0	63	0	0	0	3	80056	2	7	7	0	25	320010	80010	240000	80010	240000	785022	3500010	0	80045	80086	80069	50015	3	50049	320010	20	240000	20	320000	80069	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240014	14	44	0	240055	0	0	0	57	240040	6	1	54	45	14	0	0	5020	30	16	32	14	80066	80000	13	13	240000	80010	80070	80070	80070	80074	80048
240024	80069	620	1	0	0	0	0	0	0	81	0	0	0	3	80054	2	7	7	19	25	320010	80010	240000	80010	240000	661612	3489643	0	80048	80069	80069	50019	3	50049	320010	20	240000	20	320000	80073	80069	1	1	80021	10	9	0	10	10	80000	80000	0	10	240014	14	44	0	240056	0	0	0	60	240041	0	1	14	45	14	1	0	5020	14	16	29	16	80070	80000	13	13	240000	80010	80070	80048	80074	80070	80070

LD1 (multiple, post-index, 3 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations