Firestorm: LD1 (multiple, post-index, 3 regs, 4H) measurements

Code:

  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29691	237	3	1	0	0	1	1	0	16	0	1	0	0	4689	29063	0	0	24449	3000	1000	2000	1000	2000	5000	10000	4	1	16180	28869	29495	3	10	3000	3000	3000	29323	29306	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	2	0	2000	4	0	0	4	0	0	13287	9438	6974	3192	0	40	20798	3397	3813	11	57	59	0	28698	1000	16301	13604	14846	2000	1000	1000	29490	29528	29493	29541	29536
63004	29489	237	1	2	0	0	1	1	0	5	0	0	0	0	4740	29005	2	0	24408	3000	1000	2000	1000	2000	5000	10001	9	0	16149	28824	29504	3	10	3000	3000	3000	29359	29272	1	1	61001	1000	1000	1	2000	0	4	2000	0	0	0	3	2002	4	0	2	4	0	0	13177	9282	6949	3183	0	47	20708	3336	3809	10	69	61	0	28673	1000	16082	13478	15035	2000	1000	1000	29427	29496	29523	29551	29539
63004	29550	236	0	1	1	0	0	0	0	17	88	1	0	0	4742	29148	0	0	24455	3003	1000	2000	1001	2000	5000	10000	5	0	16162	28844	29405	3	10	3000	3000	3000	29263	29370	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	0	2000	4	0	0	4	0	0	13286	9475	6954	3154	0	54	20830	3285	3816	11	54	57	0	28701	1000	16368	13626	15095	2000	1000	1000	29538	29427	29475	29512	29503
63004	29424	237	1	0	0	0	0	0	0	8	0	1	0	0	4708	29058	1	0	24398	3000	1000	2000	1000	2000	5000	10000	5	0	16166	28899	29576	3	10	3000	3000	3000	29215	29278	1	1	61001	1000	1000	1	2000	0	4	2000	0	0	0	0	2000	4	0	0	6	2	0	13289	9669	6965	3140	0	46	20912	3378	3812	7	63	60	0	28812	1000	16155	13769	14963	2000	1000	1000	29478	29557	29527	29525	29461
63004	29539	236	0	0	1	0	0	0	0	4	0	1	0	0	4672	29090	0	0	24413	3000	1000	2000	1000	2000	5000	10000	1	1	16189	28715	29400	3	10	3000	3000	3000	29288	29369	1	1	61001	1000	1000	0	2000	2	6	2000	0	0	0	5	2005	4	0	3	4	0	0	13203	9412	6928	3217	0	58	20683	3302	3815	9	50	56	0	28630	1000	16175	13601	14880	2000	1000	1000	29474	29297	29304	29422	29355
63004	29369	236	1	0	1	0	0	0	0	4	88	0	0	0	4667	28993	2	0	24186	3000	1000	2000	1000	2000	5000	10000	0	0	16152	28763	29290	8	10	3000	3000	3000	29261	29304	2	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	0	2000	4	0	2	4	0	0	13330	9356	6942	3142	1	49	20696	3279	3811	10	63	60	0	28580	1000	15921	13382	14872	2000	1000	1000	29323	29215	29340	29357	29422
63004	29407	236	1	0	0	0	0	1	0	5	0	0	0	0	4759	28882	0	2	24197	3000	1000	2000	1000	2000	5000	10000	0	0	16172	28722	29406	3	10	3000	3000	3000	29222	29296	1	1	61001	1000	1000	0	2000	2	4	2000	0	0	0	2	2000	4	0	0	6	0	0	13335	9481	7009	3209	0	51	20751	3241	3807	9	46	59	0	28552	1000	16156	13265	14892	2000	1000	1000	29539	29420	29322	29479	29307
63004	29334	235	1	2	0	0	0	0	0	5	0	0	0	0	4574	28986	2	0	24226	3000	1000	2000	1000	2000	5000	10000	0	0	16182	28787	29363	3	10	3003	3000	3000	29198	29181	1	1	61001	1000	1000	0	2000	2	4	2000	0	0	0	0	2000	4	0	0	4	0	0	13325	9229	7025	3168	0	45	20770	3314	3815	14	62	56	0	28694	1000	16327	13561	14729	2000	1000	1000	29317	29366	29282	29426	29385
63004	29405	236	0	0	0	0	0	0	0	5	0	0	0	0	4757	28996	2	0	24321	3003	1000	2000	1000	2000	5000	10000	0	0	16176	28816	29487	3	10	3000	3000	3000	29164	29263	1	1	61001	1000	1000	1	2000	0	4	2000	0	0	0	0	2000	4	0	0	4	0	0	13416	9244	6972	3169	0	44	20729	3267	3815	14	52	53	0	28691	1000	16170	13459	15018	2000	1000	1000	29419	29282	29549	29424	29356
63004	29448	236	0	0	1	0	0	0	0	1	0	0	0	0	4649	28951	0	0	24302	3000	1000	2000	1000	2000	5000	10000	0	0	16173	28890	29437	3	10	3000	3000	3000	29353	29260	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	400	2000	4	0	0	4	0	0	13288	9350	6961	3179	0	47	20692	3303	3813	12	63	58	0	28673	1000	16180	13520	15199	2000	1000	1000	29488	29401	29320	29377	29402

Count: 8

Code:

  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80041	620	1	0	1	1	0	0	0	1	58	0	0	0	2	80027	0	6	6	20	25	240100	80100	160000	80100	160000	2050084	3671619	0	80016	80041	80041	49954	3	49999	240100	200	240000	200	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160012	12	43	160052	0	1	1	51	160039	6	1	52	42	13	0	5110	1	16	1	1	80038	0	80000	13	14	160000	80000	80100	80042	80165	80042	80042	80163
240204	80041	620	1	0	0	0	0	0	1	0	57	88	0	0	2	80149	2	6	0	65	25	240290	80176	161934	81434	162745	2077541	3726583	0	80318	80164	80286	50011	32	50166	240838	200	240489	200	240493	80409	80163	2	1	80201	100	99	100	100	80000	80000	0	100	160131	13	43	160170	0	0	0	1640	160266	6	1	12	43	13	0	5126	1	25	2	2	80139	0	80062	13	13	160000	80000	80100	80286	80164	80161	80410	80286
240204	80166	623	1	0	0	2	0	0	2	2	190	176	0	0	2	80028	3	6	6	22	25	240100	80100	160000	80100	160000	2047031	3672742	0	80016	80041	80041	49967	3	49999	240100	200	240000	200	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160013	13	42	160051	0	1	0	51	160039	6	1	52	44	12	0	5110	1	16	1	1	80039	0	80000	13	0	160000	80000	80100	80042	80042	80044	80042	80044
240204	80041	621	1	0	0	1	0	0	0	0	67	0	0	0	2	80026	2	3	6	18	25	240100	80100	160000	80100	160000	2052000	3652782	0	80016	80041	80041	49954	3	49999	240100	200	240000	200	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160012	14	43	160052	0	0	0	52	160039	6	1	52	43	13	0	5110	1	16	1	1	80038	0	80000	13	13	160000	80000	80100	80042	80042	80042	80042	80044
240204	80041	620	1	1	1	1	0	0	0	4	69	0	0	0	2	80171	2	3	6	20	25	240100	80173	160000	80100	160000	2047835	3666044	0	80016	80041	80041	49957	3	49999	240100	200	240000	200	240000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160012	15	42	160052	0	0	1	51	160039	6	1	52	42	13	0	5110	1	16	1	1	80037	0	80000	14	14	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	620	0	0	0	0	0	0	0	0	42	0	0	0	2	80025	2	12	10	17	25	240100	80100	160000	80100	160000	2044764	3672671	0	80016	80040	80170	49954	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160036	0	0	0	36	160036	6	1	31	35	0	0	5110	1	16	1	1	80037	0	80000	14	14	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	621	0	0	0	0	0	0	0	0	42	0	0	0	2	80025	2	12	12	16	25	240100	80100	160000	80100	160000	2059730	3672671	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160036	0	0	0	32	160036	6	1	31	40	0	0	5110	1	16	1	1	80037	0	80000	16	10	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	621	0	0	0	0	0	0	0	0	51	0	0	0	2	80025	2	12	12	16	25	240100	80100	160000	80100	160000	2054659	3675178	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160036	0	0	0	36	160036	6	1	31	40	0	0	5110	1	16	1	1	80037	0	80000	0	14	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	621	0	0	0	0	0	0	0	0	42	0	0	0	2	80025	2	12	12	16	25	240100	80100	160000	80100	160000	2043540	3675999	0	80015	80040	80065	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160036	0	0	0	36	160000	6	1	36	42	0	0	5110	1	16	1	1	80037	0	80000	10	10	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	620	0	0	0	0	0	0	0	0	75	0	0	0	2	80025	2	0	0	23	25	240100	80100	160000	80100	160000	2058431	3672664	0	80015	80040	80042	49953	3	49998	240100	200	240000	200	240000	80040	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160000	0	35	160036	0	1	0	0	160036	6	1	32	40	0	0	5110	1	16	2	1	80037	0	80000	10	14	160000	80000	80100	80041	80041	80041	80041	80041

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst simd alu (9a)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c3	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80040	620	0	0	0	0	0	1	1	0	0	184	0	0	0	1	80025	13	17	26	16	25	240010	80010	160000	80010	160000	2048821	3676008	0	0	80015	80040	80040	49976	3	50024	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160046	0	1	2	46	160047	6	1	46	40	0	0	0	5020	5	15	0	0	9	9	80037	80000	6	6	160000	80000	80010	80041	80041	80041	80041	80041
240025	80040	620	0	0	0	0	0	1	1	0	0	52	0	0	0	1	80025	13	17	27	16	25	240010	80073	160000	80010	160000	2053159	3666007	0	0	80015	80040	80040	49975	3	50021	240010	20	240000	20	240000	80040	80164	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160046	0	0	0	50	160046	6	1	46	40	0	0	0	5020	9	15	0	0	9	9	80037	80000	6	6	160000	80000	80010	80042	80041	80041	80041	80162
240024	80040	621	0	0	0	0	0	0	0	0	0	55	0	0	0	1	80025	12	17	27	16	25	240010	80010	160000	80010	160000	2054789	3676008	0	0	80015	80040	80040	49975	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160046	0	1	0	49	160046	6	1	46	0	0	0	0	5020	10	15	0	0	9	11	80037	80000	6	6	160000	80000	80010	80041	80041	80042	80041	80041
240024	80040	620	0	0	0	0	0	0	0	0	0	64	0	0	0	0	80025	12	0	26	16	25	240010	80010	160000	80010	160000	2055129	3673220	0	0	80016	80040	80040	49975	3	50020	240010	20	240000	20	240000	80161	80040	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160046	0	0	0	46	160274	6	1	46	40	0	0	0	5020	9	16	0	0	9	9	80037	80000	6	6	160000	80000	80010	80041	80162	80041	80041	80041
240024	80040	620	0	0	0	0	0	0	0	0	0	52	88	0	0	1	80150	12	17	27	16	25	240010	80010	160000	80010	160000	2063161	3661969	0	0	80015	80040	80165	49975	3	50021	240254	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160046	0	1	0	47	160046	6	1	17	40	0	0	0	5020	5	15	0	0	9	9	80037	80000	6	6	160000	80000	80010	80041	80041	80041	80041	80164
240024	80040	620	0	0	0	0	0	0	0	0	0	52	0	0	0	1	80025	12	17	27	20	25	240010	80010	160000	80010	160000	2058310	3672631	0	0	80015	80040	80040	50030	3	50021	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160046	0	0	0	47	160046	6	1	46	40	0	0	0	5036	9	25	0	0	4	10	80149	80064	6	6	160000	80000	80010	80041	80041	80041	80041	80042
240024	80040	620	0	0	0	0	0	0	0	0	0	52	88	0	0	1	80147	12	16	26	148	57	240562	80075	160246	80093	160321	2060363	3685768	0	0	80214	80163	80282	50030	18	50183	240253	20	240255	20	240489	80161	80065	2	1	80021	10	9	10	10	80000	0	80000	0	10	160236	7	50	0	160159	0	0	0	852	160159	6	1	46	40	0	0	0	5036	10	25	0	0	11	12	80235	80062	6	6	160000	80000	80010	80282	80164	80287	80287	80165
240024	80285	622	0	0	0	0	0	0	0	0	0	53	0	0	0	1	80026	12	16	27	20	25	240010	80010	160000	80010	160000	2055129	3669370	0	0	80015	80040	80040	49976	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160047	0	0	0	46	160047	6	1	47	40	0	0	0	5020	9	16	0	0	6	8	80037	80000	6	0	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	620	0	0	0	0	0	1	0	0	0	52	0	0	0	1	80025	12	17	26	19	25	240010	80010	160000	80010	160000	2063161	3675927	0	0	80015	80040	80040	49975	3	49971	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160050	0	0	0	46	160046	6	1	46	40	0	0	0	5020	10	16	0	0	6	9	80038	80000	6	6	160000	80000	80010	80042	80041	80041	80041	80041
240024	80040	620	0	0	0	0	0	0	0	0	0	52	0	0	0	1	80025	12	17	27	17	25	240010	80010	160000	80010	160000	2053159	3666046	0	0	80314	80040	80040	49977	3	50021	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	0	80000	0	10	160000	0	50	0	160047	0	0	0	49	160046	6	1	47	40	0	0	0	5020	9	16	0	0	10	10	80037	80000	6	6	160000	80000	80010	80041	80041	80041	80041	80041

LD1 (multiple, post-index, 3 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations