Firestorm: LD1 (multiple, post-index, 3 regs, 4S) measurements

Code:

  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5e	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d8	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29410	237	2	0	4	0	1	1	1	0	0	0	0	13	0	1	0	0	4688	28890	1	2	1	24192	4004	1000	3000	1000	3000	5000	15000	0	15	0	0	16154	0	28859	29358	9	10	4000	3000	4000	29241	29308	1	1	61001	1000	1000	0	3003	6	9	3004	0	0	2	11	3004	5	1	10	9	3	0	0	13183	9463	6947	3158	0	53	20791	0	3272	3800	16	55	57	28586	1000	16048	13376	15073	3000	1000	29486	29338	29340	29405	29382
63004	29323	234	0	0	1	1	0	2	1	1	1	0	0	29	0	0	0	0	4621	28952	1	3	3	24135	4000	1000	3000	1000	3000	5000	15000	0	10	0	0	16177	0	28778	29338	9	10	4000	3000	4000	29153	29254	1	1	61001	1000	1000	0	3004	0	9	3013	0	0	0	15	3004	5	1	11	12	3	1	0	13058	9413	6973	3175	0	57	20724	0	3315	3808	19	51	50	28503	1000	16495	13368	14949	3000	1000	29319	29485	29402	29525	29330
63004	29435	237	0	1	1	0	1	3	1	0	0	0	0	13	0	0	0	0	4706	28955	0	3	3	24229	4000	1000	3000	1000	3000	5000	15000	0	7	0	8	16148	0	28746	29430	3	10	4000	3000	4000	29246	29441	1	1	61001	1000	1000	0	3005	5	6	3004	0	0	0	5	3004	5	1	1	6	0	2	0	13170	9471	6942	3185	0	47	20788	0	3282	3811	36	58	50	28600	1000	16229	13550	15068	3000	1000	29565	29518	29551	29377	29576
63004	29365	236	0	1	1	0	0	2	1	0	0	0	1	142	0	0	0	0	4571	29477	0	0	1	24119	4000	1000	3003	1000	3003	5000	15146	0	9	1	8	16240	0	28864	29352	8	10	4000	3003	4000	29267	29323	2	1	61001	1000	1000	0	3009	3	6	3013	0	0	3	8	3001	5	1	4	6	3	0	0	13324	9588	6969	3131	0	52	20831	0	3332	3812	14	42	53	28795	1000	16354	13445	15098	3000	1000	29344	29457	29514	29425	29421
63004	29449	238	0	1	2	0	0	3	0	0	0	1	0	13	88	0	0	0	4674	28895	0	0	0	24154	4000	1000	3000	1000	3000	5005	15000	0	0	0	0	16170	0	28650	29418	3	49	4000	3000	4004	29317	29323	1	1	61001	1000	1000	0	3003	5	9	3007	1	0	3	5	3004	5	1	4	6	3	3	760	13111	9211	6973	3162	0	44	20663	0	3206	3817	22	54	51	28680	1000	16391	13548	15000	3000	1000	29443	29472	29459	29469	29353
63004	29274	237	0	0	0	0	1	5	0	1	1	1	0	144	0	0	0	0	4701	28957	0	0	0	24213	4000	1000	3000	1000	3000	5000	15000	0	0	0	0	16146	0	28770	29381	3	10	4000	3000	4004	29201	29182	2	1	61001	1000	1000	0	3009	0	6	3007	0	0	1	403	3001	5	1	7	6	3	6	0	13123	9237	6947	3122	0	49	20573	0	3267	3809	15	53	54	28462	1000	16384	13759	15293	3000	1000	29394	29597	29356	29315	29424
63004	29362	236	0	1	2	1	1	2	1	0	1	0	0	10	0	0	0	0	4551	28899	0	0	0	24323	4000	1000	3000	1000	3000	5000	15002	0	0	0	0	16172	0	28680	29322	3	10	4000	3000	4000	29231	29222	1	1	61001	1000	1000	0	3004	4	9	3007	0	0	2	8	3004	5	1	4	8	3	0	0	13064	9334	6980	3091	0	44	20669	0	3220	3817	13	52	47	28457	1000	16282	13443	14879	3000	1000	29431	29377	29304	29455	29316
63004	29334	237	0	1	3	1	1	4	0	0	1	0	0	17	0	0	0	0	4697	28944	0	0	0	24288	4000	1000	3000	1000	3000	5000	15000	0	0	0	0	16177	0	28701	29339	3	10	4000	3000	4000	29202	29159	1	1	61001	1000	1000	0	3004	4	9	3007	0	0	0	10	3003	5	1	1	6	0	0	0	13172	9436	6953	3155	0	53	20737	0	3277	3812	17	54	51	28584	1000	16383	13471	15049	3000	1000	29467	29439	29412	29351	29406
63004	29578	235	0	0	2	0	0	3	1	0	0	0	0	10	0	0	0	0	4692	29001	0	0	0	24238	4000	1000	3000	1000	3000	5000	15000	0	4	0	0	16144	0	28687	29396	3	10	4000	3000	4000	29285	29260	1	1	61001	1000	1000	0	3000	0	6	3001	2	0	0	1	3004	5	1	1	6	0	0	145	13068	9253	6999	3152	1	57	20834	0	3230	3813	13	51	48	28709	1000	15409	13318	14909	3000	1000	29855	29112	29281	29119	29007
63004	29162	237	0	1	5	0	0	2	0	1	1	0	0	42	0	0	0	1	4591	29058	0	0	0	24184	4000	1000	3000	1000	3000	5000	15004	0	2	0	0	16154	0	28682	29418	3	10	4000	3000	4000	29206	29436	1	1	61001	1000	1000	0	3000	0	9	3001	0	0	0	10	3001	5	1	1	6	0	0	0	13364	9294	6935	3164	0	50	20879	0	3289	3816	14	50	51	28594	1000	16420	13320	15041	3000	1000	29512	29278	29579	29356	29249

Count: 8

Code:

  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80067	643	1	0	0	0	0	0	0	45	0	1	2	80052	2	6	17	101	54	320102	80102	240000	80105	0	240015	622615	3491083	0	80049	80071	80069	49992	6	50028	320118	200	240024	200	320288	80045	80064	1	1	80201	100	99	0	100	0	100	80000	80000	1	100	240000	0	44	0	240040	0	0	0	45	240039	5	1	40	44	0	1	1	1	5116	0	1	25	1	0	80062	80003	14	10	240000	80100	80069	80066	80402	80066	80071
240204	80069	642	0	0	0	0	0	1	0	247	0	0	2	80048	2	6	6	19	25	320100	80232	240130	80100	0	240000	623390	3491311	0	80048	80406	80243	49991	3	50022	320591	200	240000	200	320000	80068	80065	1	1	80201	100	99	0	100	0	100	80000	80000	0	100	240000	0	44	0	240040	0	4	0	43	240041	6	1	40	44	0	0	0	0	5110	0	2	16	1	1	80069	80073	11	18	240000	80100	80076	80061	80235	80238	80069
240204	80065	643	0	0	1	0	0	0	0	45	0	0	2	80055	2	6	1	142	25	320100	80100	240000	80161	0	240178	662126	3502572	0	80046	80071	80069	49988	24	50023	320100	200	240000	200	320000	80068	80061	1	1	80201	100	99	1	100	0	100	80000	80000	0	100	240000	0	43	0	240040	0	3	0	50	240171	5	1	40	44	0	0	0	0	5125	0	1	16	1	1	80365	80000	14	14	240000	80100	80070	80396	80071	80063	80241
240204	80071	643	0	0	0	0	0	0	1	49	0	0	2	80051	2	6	2	22	25	320307	80100	240000	80100	0	240000	646394	3507064	0	80045	80065	80238	50106	12	50031	320100	200	240000	200	320000	80065	80065	1	1	80201	100	99	0	100	0	100	80000	80000	0	100	240132	0	43	0	240042	0	1	0	41	240041	5	1	40	44	0	0	0	0	5124	0	1	25	1	1	80069	80000	14	10	240000	80100	80066	80066	80068	80063	80252
240204	80065	643	0	1	0	0	0	0	1	61	0	0	2	80052	2	6	6	135	25	320868	80100	240000	80100	0	240000	675611	3515139	0	80040	80069	80066	49996	3	50317	320363	200	240000	200	320000	80065	80060	1	1	80201	100	99	0	100	0	100	80000	80000	0	100	240000	0	44	0	240042	0	1	0	43	240040	6	1	40	44	0	0	0	0	5110	0	1	16	1	1	80065	80000	13	14	240000	80100	80065	80065	80071	80067	80070
240204	80068	643	0	0	0	0	0	0	0	58	0	0	2	80053	2	6	6	20	25	320100	80100	240000	80100	0	240000	623052	3515559	0	80051	80238	80074	49994	3	50022	320100	200	240000	200	320000	80068	80221	1	1	80201	100	99	0	100	0	100	80000	80000	0	100	240000	0	43	0	240041	0	1	0	15	240041	5	1	40	44	0	0	0	0	5110	0	1	16	1	1	80066	80000	15	10	240000	80100	80069	80239	80066	80065	80068
240204	80065	643	0	0	0	0	0	0	0	58	0	0	2	80059	2	6	6	151	25	320100	80100	240000	80100	0	240000	648712	3522358	0	80040	80069	80065	49987	3	50024	320100	200	240000	200	320257	80069	80069	1	1	80201	100	99	0	100	0	100	80000	80000	0	100	240000	0	43	0	240041	0	5	0	41	240040	5	1	41	44	0	0	0	0	5110	0	1	16	1	1	80062	80000	14	10	240000	80100	80067	80066	80066	80063	80075
240204	80234	643	0	0	0	0	0	0	0	51	0	0	1	80053	2	6	6	91	25	320100	80100	240000	80100	0	240000	595591	3502449	0	80043	80404	80068	49988	3	50032	320100	200	240000	200	320256	80065	80066	1	1	80201	100	99	1	100	0	100	80000	80000	0	100	240000	0	43	0	240040	0	2	0	43	240041	6	1	40	44	0	0	0	0	5110	0	1	16	1	1	80066	80000	14	14	240000	80100	80069	80067	80066	80063	80072
240204	80066	644	0	0	0	0	0	0	0	52	0	0	1	80045	2	6	6	20	25	320291	80161	240000	80100	0	240000	670772	3519319	0	80078	80070	80072	49989	3	50023	320100	200	240000	200	320256	80233	80218	1	1	80201	100	99	0	100	0	100	80000	80000	0	100	240000	0	43	0	240041	0	3	0	49	240041	5	1	40	44	0	0	0	0	5110	0	1	16	1	1	80062	80062	14	10	240000	80100	80069	80066	80066	80418	80069
240204	80239	642	0	0	1	0	0	0	0	49	0	0	2	80053	2	17	6	30	25	320100	80100	240000	80100	0	240000	596785	3528195	0	80189	80222	80068	49987	3	50031	320100	200	240000	200	320000	80073	80071	1	1	80202	100	99	0	100	0	100	80000	80000	0	100	240000	0	43	0	240041	0	1	0	41	240041	5	1	40	44	0	0	0	0	5110	0	1	16	1	1	80063	80000	14	10	240000	80100	80067	80074	80242	80412	80072

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80059	643	0	0	0	0	45	0	1	0	0	2	80046	2	17	17	17	25	320010	80010	240000	80010	240000	676539	3549807	0	0	80040	80069	80064	50006	3	50035	320010	20	240000	20	320000	80060	80055	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	36	0	240042	0	0	40	240040	5	1	33	43	0	5020	2	16	0	1	2	80057	0	80000	10	6	240000	80010	80087	80062	80046	80046	80061
240024	80066	643	0	0	0	0	58	0	1	0	0	2	80050	2	11	17	18	25	320010	80010	240000	80010	240000	675547	3487120	0	0	80035	80065	80060	50006	3	50035	320010	20	240000	20	320000	80062	80055	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	36	0	240000	0	0	40	240033	5	1	33	44	0	5022	2	16	0	2	1	80061	0	80000	11	6	240000	80010	80061	80066	80063	80061	80062
240024	80060	643	0	0	0	0	45	0	1	0	0	3	80040	2	17	17	19	25	320010	80010	240000	80010	240000	610849	3507089	0	0	80038	80060	80060	50006	3	50035	320010	20	240000	20	320000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	35	0	240040	0	0	40	240040	5	1	33	44	0	5020	2	16	0	1	1	80061	0	80000	10	6	240000	80010	80061	80062	80065	80061	80062
240024	80061	643	0	0	0	0	57	0	1	0	0	3	80045	0	17	14	16	25	320010	80010	240000	80010	240000	636737	3500743	0	0	80040	80062	80060	50006	3	50035	320010	20	240000	20	320000	80060	80055	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	36	0	240040	1	0	36	240040	5	1	37	43	0	5020	1	16	0	1	2	80057	0	80000	10	11	240000	80010	80061	80062	80065	80061	80062
240024	80060	643	0	0	0	0	57	0	1	0	0	3	80045	2	17	17	1	25	320010	80010	240000	80010	240000	675547	3487120	0	0	80035	80060	80060	50007	3	50328	320010	20	240000	20	320000	80060	80055	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	36	0	240040	0	0	40	240040	5	1	33	43	0	5020	1	16	0	2	1	80062	0	80000	6	10	240000	80010	80061	80061	80067	80061	80061
240024	80061	643	0	0	0	0	45	0	1	0	0	3	80046	2	17	17	15	25	320010	80010	240000	80010	240000	664879	3487120	0	0	80035	80060	80055	50010	3	50040	320010	20	240000	20	320000	80060	80060	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	39	0	240039	0	0	33	240039	5	1	33	36	0	5022	1	16	0	1	1	80061	0	80000	10	6	240000	80010	80063	80060	80061	80061	80061
240024	80060	643	0	0	0	0	45	0	0	0	1	3	80049	2	17	17	16	25	320010	80010	240000	80010	240000	644738	3519409	0	0	80030	80060	80061	50006	3	50347	320010	20	240000	20	320000	80061	80058	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	36	0	240040	0	0	40	240041	5	1	40	43	0	5022	2	16	0	2	1	80057	0	80000	10	6	240000	80010	80062	80066	80062	80061	80066
240024	80063	643	0	0	0	0	46	0	0	0	0	2	80046	3	14	17	16	25	320010	80010	240000	80010	240000	644738	3497640	0	0	80035	80061	80064	50006	3	50035	320010	20	240000	20	320000	80061	80055	1	1	80021	10	9	10	10	80000	80000	1	10	240000	0	36	0	240040	0	0	33	240041	5	0	34	43	0	5020	1	16	0	2	1	80057	0	80000	10	10	240000	80010	80065	80062	80056	80062	80062
240024	80062	643	0	0	0	0	46	0	0	0	1	3	80046	2	17	17	13	25	320010	80010	240000	80010	240000	644738	3507089	0	0	80035	80060	80064	50006	3	50040	320010	20	240000	20	320000	80045	80054	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	36	0	240039	0	0	33	240039	5	1	33	44	0	5020	1	16	0	2	1	80058	0	80000	10	10	240000	80010	80062	80061	80063	80063	80062
240024	80054	643	0	0	0	0	38	0	0	0	1	1	80049	2	17	17	16	25	320010	80010	240000	80010	240000	676539	3507089	0	0	80035	80060	80065	50005	3	50068	320010	20	240220	20	320000	80049	80055	1	1	80021	10	9	10	10	80000	80000	0	10	240000	0	36	0	240040	0	0	39	240040	5	1	0	43	0	5020	1	16	0	1	1	80052	0	80000	12	6	240000	80010	80062	80061	80061	80056	80062

LD1 (multiple, post-index, 3 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations