Firestorm: LD1 (multiple, post-index, 3 regs, 8B) measurements

Code:

  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29289	227	0	18	0	9	0	0	1	0	0	0	0	1	0	4620	28828	1	2	2	24188	3000	1000	2000	1000	2000	5000	10000	4	16118	28625	29349	3	10	3000	3000	3000	29249	29130	1	1	61001	1000	1000	1	2000	0	6	2006	0	0	1	2	2002	6	0	4	0	2	1	0	13235	9288	6983	3097	7	37	20670	3147	3813	4	34	42	28533	1000	16085	13635	14718	2000	1000	1000	29354	29286	29287	29242	29292
63004	29324	227	1	15	1	11	1	1	1	0	0	2	0	0	0	4642	28766	0	0	0	24158	3000	1000	2000	1000	2000	5000	10002	8	16216	28662	29130	3	10	3000	3000	3000	29076	29086	1	1	61001	1000	1000	1	2000	0	6	2003	0	0	0	7	2002	4	0	4	6	0	0	0	12940	9167	6895	3087	8	37	20600	3158	3815	8	40	38	28421	1000	16037	13531	15008	2000	1000	1000	29228	29247	29279	29270	29242
63004	29227	226	1	15	0	14	0	0	0	0	0	143	0	1	0	4643	28888	0	0	0	24135	3000	1000	2000	1000	2000	5000	10000	9	16243	28542	29194	3	10	3000	3000	3000	28988	29133	1	1	61001	1000	1000	0	2000	0	6	2002	0	0	0	2	2002	6	0	2	6	0	0	0	12919	9316	6970	3137	6	36	20612	3209	3808	10	38	37	28405	1000	16171	13440	15175	2000	1000	1000	29209	29224	29159	29233	29260
63004	29314	227	1	13	0	10	0	0	0	0	4	136	0	0	0	4570	28758	0	0	2	24148	3000	1000	2000	1000	2000	5000	10000	9	16135	28601	29177	7	27	3000	3000	3000	29164	29022	1	1	61001	1000	1000	0	2000	0	6	2002	0	0	0	402	2002	0	0	3	6	0	0	0	12919	9414	6933	3066	7	34	20643	3266	3808	6	39	34	28511	1000	16488	13819	15016	2000	1000	1000	29144	29148	29220	29255	29246
63004	29358	227	0	14	0	15	0	1	1	0	0	2	88	0	0	4695	28823	0	0	0	24037	3000	1000	2000	1001	2000	5000	10000	5	16256	28542	29283	3	10	3000	3000	3000	29149	28966	1	1	61001	1000	1000	0	2000	0	6	2003	0	0	0	5	2003	4	0	2	6	0	0	0	13006	9642	6907	3195	5	36	20588	3164	3818	10	35	35	28456	1000	16107	13485	14914	2000	1000	1000	29289	29276	29248	29213	29222
63004	29228	227	0	14	0	13	0	0	0	0	0	5	0	1	0	4628	28749	0	0	0	24196	3000	1000	2000	1000	2000	5000	10000	0	16258	28624	29178	3	10	3000	3000	3000	29222	29219	1	1	61001	1000	1000	0	2003	0	4	2000	0	0	0	0	2000	0	0	0	6	0	0	0	13288	9585	6853	3114	6	36	20649	3266	3810	9	33	37	28344	1000	16272	13606	14934	2000	1000	1000	29106	29172	29322	29275	29184
63004	29292	227	0	17	1	18	0	0	0	1	0	2	0	0	0	4603	28824	0	0	0	24086	3000	1000	2000	1000	2000	5000	10000	1	16272	28593	29250	3	10	3000	3000	3000	29132	29087	1	1	61001	1000	1000	0	2003	2	0	2000	0	0	1	0	2000	0	0	0	4	2	0	0	12992	9471	6943	3086	8	41	20614	3183	3821	8	37	37	28447	1000	16012	13669	14631	2000	1000	1000	29357	29215	29116	29303	29305
63004	29338	226	0	19	0	16	0	0	0	0	0	5	0	0	0	4656	28865	0	0	1	24107	3000	1000	2000	1000	2000	5000	10000	9	16181	28665	29244	3	10	3000	3000	3000	29120	29095	1	1	61001	1000	1000	0	2000	4	6	2000	0	0	0	3	2000	0	0	0	4	2	0	0	13145	9505	6882	3124	6	35	20622	3236	3814	8	36	38	28499	1000	16420	13671	14698	2000	1000	1000	29267	29254	29263	29207	29386
63004	29277	228	0	19	0	10	0	0	0	0	0	2	0	0	1	4779	28753	0	0	0	24205	3000	1000	2000	1000	2000	5000	10000	4	16170	28619	29299	3	10	3000	3000	3000	29043	29193	1	1	61001	1000	1000	0	2000	0	4	2000	0	0	0	0	2000	4	0	2	4	0	1	0	13048	9257	6936	3090	6	31	20551	3271	3817	7	32	35	28385	1000	16301	13507	15204	2000	1000	1000	30070	29971	29648	29517	29335
63004	29249	227	0	10	0	12	1	0	0	0	0	8	0	0	0	4520	28816	0	0	0	24172	3000	1000	2000	1000	2000	5000	10000	5	16168	28593	29393	3	10	3000	3000	3000	29169	29223	1	1	61001	1000	1000	0	2000	2	0	2000	0	0	0	0	2000	4	0	2	4	0	0	0	13035	9278	6915	3210	4	31	20674	3178	3818	9	33	34	28471	1000	16024	13372	14672	2000	1000	1000	29199	29197	29390	29269	29158

Count: 8

Code:

  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	81966	634	1	1	1	0	0	0	1	2	170	88	0	0	1	81862	2	12	12	54	56	240294	80166	160245	80199	160166	2063074	3674918	0	0	0	80211	80162	80280	50013	21	50155	240374	200	240280	202	240280	80160	80286	2	1	80201	100	99	100	100	80000	80000	100	160118	0	27	0	160032	0	85	0	12170	161637	6	1	23	35	0	0	0	0	5125	0	1	34	2	2	80138	0	80134	10	10	160000	80000	80100	80041	80164	80189	80164	80165
240204	80283	621	0	0	0	1	0	0	1	3	293	88	0	0	1	80025	2	0	12	4	46	240100	80100	160000	80100	160000	2024230	3675995	1	0	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	27	0	160032	0	14	0	23	160032	6	1	0	35	0	0	0	0	5110	0	1	16	1	1	80037	1	80000	10	6	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	621	0	0	0	0	0	0	0	0	37	0	0	0	1	80025	2	0	12	12	25	240100	80100	160000	80100	160000	2046787	3646101	1	0	0	80114	80040	80040	49953	3	49999	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	27	0	160000	0	78	0	23	160000	6	1	0	0	0	0	0	0	5110	0	1	16	1	1	80037	0	80000	10	10	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	621	0	0	0	0	0	0	0	0	42	0	0	0	1	80025	2	12	12	15	25	240100	80100	160000	80100	160000	2064971	3679352	1	0	0	80015	80041	80040	49954	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	27	0	160000	0	94	0	56	160024	6	1	0	35	0	0	0	0	5110	0	1	16	1	1	80037	0	80000	11	6	160000	80000	80100	80041	80041	80041	80041	80045
240204	80040	621	0	0	0	0	0	1	0	0	125	0	0	0	1	80025	2	12	12	11	25	240125	80100	160000	80100	160000	2043614	3677230	1	0	0	80015	80040	80040	49954	3	49999	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	33	0	160000	0	83	0	27	160000	6	1	32	35	0	0	0	0	5110	0	1	16	1	1	80037	1	80000	10	6	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	621	0	0	0	0	0	0	0	0	41	0	0	0	0	80025	2	12	12	11	25	240100	80100	160000	80100	160000	2053465	3675995	1	0	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	27	0	160031	0	87	0	27	160024	6	1	0	35	0	0	0	0	5110	0	1	16	1	1	80037	0	80000	10	10	160000	80000	80100	80042	80041	80041	80041	80041
240204	80040	636	0	0	0	0	0	0	0	0	50	0	0	0	0	80025	2	12	12	0	25	240100	80100	160000	80100	160000	2043332	3672664	1	0	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	27	0	160024	0	48	0	32	160024	6	1	23	35	0	0	0	0	5110	0	1	16	1	1	80037	0	80000	10	6	160000	80000	80100	80041	80041	80041	80041	80041
240204	80040	620	0	0	0	0	0	0	0	0	127	0	0	0	1	80025	2	12	12	11	25	240100	80100	160000	80100	160000	2054994	3671328	1	0	0	80015	80040	80040	49953	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	35	0	160032	0	56	0	23	160032	6	1	24	35	0	0	0	0	5110	0	1	16	1	1	80037	1	80000	10	0	160000	80000	80100	80042	80041	80041	80041	80042
240204	80040	620	0	0	0	0	0	0	0	0	62	0	0	0	0	80025	2	12	0	24	25	240100	80100	160000	80100	160000	2053506	3679351	1	0	0	80015	80040	80040	49954	3	49998	240100	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	0	0	160032	0	0	0	37	160000	6	1	24	35	0	0	0	0	5110	0	1	16	1	1	80037	1	80000	10	10	160000	80000	80100	80041	80041	80041	80041	80042
240204	80040	620	0	0	0	0	0	0	0	0	37	0	0	1	1	80025	2	12	12	11	25	240100	80100	160000	80100	160000	2044958	3646101	0	0	0	80015	80040	80040	49953	3	49998	240361	200	240000	200	240000	80040	80040	1	1	80201	100	99	100	100	80000	80000	100	160000	0	35	8	160000	0	0	0	38	160024	6	1	32	35	0	0	0	0	5110	0	1	16	2	1	80037	0	80000	10	10	160000	80000	80100	80041	80041	80041	80041	80170

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80040	620	0	0	0	1	0	0	0	42	0	0	0	0	0	80027	2	0	0	0	25	240010	80010	160000	80010	160000	2045843	3679352	80016	80041	80040	49975	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	160036	0	0	31	160036	6	1	32	40	0	0	0	5020	1	16	0	1	1	80037	0	80000	14	0	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	620	0	0	0	0	0	0	0	59	0	1	0	0	2	80025	0	12	12	4	25	240010	80010	160000	80010	160000	2069658	3679352	80015	80040	80040	49976	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	160000	0	0	31	160036	0	0	0	40	0	0	0	5020	1	16	0	1	1	80037	0	80000	0	10	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	621	0	0	0	0	0	0	0	42	0	1	0	0	0	80025	2	12	12	16	25	240010	80010	160000	80010	160000	2045231	3670522	80019	80040	80040	49975	3	50021	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	160036	0	0	36	160000	6	1	33	40	0	0	0	5020	1	16	0	1	1	80037	0	80000	0	10	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	620	0	0	0	0	0	0	0	38	0	0	0	0	2	80025	2	12	0	20	25	240010	80010	160000	80010	160000	2059231	3672665	80015	80040	80040	49976	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	160036	0	0	36	160036	0	1	0	35	0	0	0	5020	1	16	0	1	1	80037	0	80000	14	14	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	620	0	0	0	0	0	0	0	42	0	0	0	0	2	80025	2	12	12	16	25	240010	80010	160000	80010	160000	2050167	3669341	80015	80040	80040	49976	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	0	160036	1	0	39	160036	0	1	36	35	0	0	0	5020	1	15	0	1	1	80037	0	80000	14	10	160000	80000	80010	80042	80041	80041	80041	80041
240024	80041	620	0	0	0	0	0	0	0	42	0	1	0	0	0	80025	2	12	12	16	25	240010	80010	160000	80010	160000	2053373	3672685	80414	80040	80040	49975	3	50020	240010	20	240000	20	240000	80041	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	160036	4	0	36	160036	6	1	32	40	0	0	0	5020	1	15	0	1	1	80037	0	80000	0	14	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	620	0	0	0	0	0	0	0	54	0	0	0	0	2	80025	2	12	12	11	25	240010	80010	160000	80010	160000	2059231	3679352	80015	80040	80040	49975	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	160031	0	0	36	160039	6	1	0	40	0	0	0	5020	1	16	0	1	1	80037	0	80000	14	0	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	620	0	0	0	1	0	0	0	12	0	0	0	0	2	80025	2	12	0	16	25	240010	80010	160000	80010	160000	2069658	3673070	80017	80040	80040	49976	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	1	10	160000	0	0	160000	0	0	32	160000	6	1	32	40	0	0	0	5020	1	16	0	1	1	80037	0	80000	0	10	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	620	0	0	0	0	0	0	0	54	0	0	0	0	0	80025	2	0	12	0	25	240010	80010	160000	80010	160000	2045231	3669309	80024	80040	80040	49975	3	50020	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	40	160036	0	0	39	160036	6	1	36	40	0	0	0	5020	1	15	0	1	1	80037	0	80000	14	15	160000	80000	80010	80041	80041	80041	80041	80041
240024	80040	620	0	0	0	0	0	0	0	42	0	0	0	0	2	80025	2	12	12	0	25	240010	80010	160000	80010	160000	2057028	3675516	80015	80040	80040	49976	3	50021	240010	20	240000	20	240000	80040	80040	1	1	80021	10	9	10	10	80000	80000	0	10	160000	0	35	160000	0	0	36	160036	6	0	32	0	0	0	0	5020	1	16	0	1	1	80037	0	80000	14	14	160000	80000	80010	80041	80041	80041	80041	80041

LD1 (multiple, post-index, 3 regs, 8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations