Firestorm: LD1 (multiple, post-index, 3 regs, 8H) measurements

Code:

  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.000

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29088	233	2	1	2	1	1	1	1	0	0	0	0	17	0	1	0	0	4747	28392	0	0	0	23694	4000	1000	3000	1000	3000	5000	15003	9	16151	28279	28790	3	10	4000	3000	4000	28810	28803	1	1	61001	1000	1000	3004	4	9	3009	0	0	2	8	3004	5	1	7	9	3	1	0	13050	9454	6962	3166	0	68	20204	3218	3811	14	66	67	28304	1000	15781	13012	14391	3000	1000	28909	28918	28974	28924	28853
63004	28926	233	0	0	4	0	0	4	0	0	0	0	0	11	0	1	0	0	4646	28583	0	2	3	23650	4000	1000	3000	1000	3000	5000	15000	9	16149	28350	28938	3	10	4000	3000	4000	28746	28747	1	1	61001	1000	1000	3000	0	6	3004	0	0	0	4	3004	5	1	3	6	0	0	0	13072	9369	6964	3111	1	62	20293	3143	3814	24	71	72	28345	1000	15666	13117	14650	3000	1000	28878	28909	28962	28854	28849
63004	28898	232	0	1	2	1	1	2	1	0	0	0	0	13	0	1	0	0	4617	28593	0	2	3	23738	4000	1000	3000	1000	3000	5000	15000	3	16148	28428	28978	3	10	4000	3000	4000	28945	28792	1	1	61001	1000	1000	3000	0	6	3001	0	0	0	3	3004	3	1	4	6	0	0	0	13251	9263	6955	3141	2	71	20242	3221	3807	29	73	74	28225	1000	15529	12930	14567	3000	1000	28955	28885	28971	28915	28870
63004	28842	233	0	0	2	0	0	2	0	0	0	0	0	9	0	1	0	0	4805	28503	0	2	3	23720	4000	1000	3000	1000	3000	5000	15000	8	16127	28386	28942	3	10	4000	3000	4000	28824	28751	1	1	61001	1000	1000	3000	0	6	3004	0	0	0	4	3004	5	1	3	9	0	0	0	13121	9114	6963	3114	3	74	20135	3218	3814	16	61	66	28366	1000	15728	12698	14430	3000	1000	28922	28911	28835	28777	28890
63004	28903	233	0	0	2	0	0	3	0	0	0	0	0	9	0	1	0	0	4816	28573	0	0	0	23644	4000	1000	3000	1000	3000	5000	15000	3	16135	28336	28869	3	10	4000	3000	4000	28755	28775	1	1	61001	1000	1000	3000	0	8	3004	0	0	0	4	3004	5	0	3	9	0	0	0	13380	9199	6948	3125	1	64	20301	3146	3817	19	66	65	28265	1000	15780	12986	14546	3000	1000	29011	28872	28995	28892	28946
63004	28858	232	0	0	1	0	0	3	0	0	0	0	0	15	0	0	0	0	4778	28637	0	3	3	23599	4000	1000	3000	1000	3000	5000	15000	3	16148	28488	29002	3	10	4000	3000	4000	28805	28845	1	1	61001	1000	1000	3000	0	6	3004	0	0	0	4	3004	5	1	3	9	0	0	0	13230	9599	6955	3094	2	70	20155	3254	3813	17	67	70	28309	1000	15700	12970	14540	3000	1000	28801	28855	28884	28971	28928
63004	29000	232	0	0	2	0	0	2	0	0	0	0	0	18	0	1	0	0	4720	28493	0	3	2	23688	4000	1000	3000	1000	3000	5000	15000	2	16134	28387	28946	3	10	4000	3000	4000	28705	28752	1	1	61001	1000	1000	3000	0	0	3003	0	0	0	3	3003	5	0	0	9	0	0	0	13294	9266	7005	3090	0	64	20323	3214	3811	26	65	65	28175	1000	15824	13143	14717	3000	1000	28973	28870	28946	28768	28851
63004	28835	232	0	0	2	0	0	2	0	0	0	0	0	9	0	1	0	0	4648	28454	0	2	0	23764	4000	1000	3000	1000	3000	5000	15002	10	16151	28332	28777	3	10	4000	3000	4000	28734	28768	1	1	61001	1000	1000	3000	0	6	3004	0	0	0	3	3003	5	0	3	9	0	0	0	13206	9293	6906	3180	1	69	20309	3170	3814	26	69	79	28261	1000	15558	12960	14802	3000	1000	28952	28874	28839	28906	28734
63004	28910	231	0	0	2	0	0	2	0	0	0	0	0	9	0	1	0	0	4725	28511	0	3	0	23714	4000	1000	3000	1000	3000	5000	15000	7	16161	28379	28926	3	10	4000	3000	4000	28739	28850	1	1	61001	1000	1000	3005	5	9	3009	0	1	3	8	3004	5	1	4	9	3	1	114	13321	9299	6900	3116	1	70	20342	3203	3809	22	72	71	28264	1000	15635	12981	14477	3000	1000	28884	28763	28887	28910	28965
63004	28743	232	0	0	1	0	0	2	0	0	0	0	0	9	0	1	0	0	4678	28501	1	3	3	23736	4000	1000	3000	1000	3000	5000	15002	7	16115	28347	29062	3	10	4000	3000	4000	28703	28743	1	1	61001	1000	1000	3000	0	6	3004	0	0	0	4	3004	4	1	3	9	0	0	0	13091	9304	6941	3136	0	68	20256	3288	3811	24	71	61	28211	1000	15691	12878	14512	3000	1000	28791	28919	28890	28968	28904

Count: 8

Code:

  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80231	644	1	2	1	0	0	0	1	135	0	1	0	0	0	80051	2	19	19	10	53	320100	80100	240130	80100	240000	678725	3504008	80030	80207	80055	49978	14	50156	320100	200	240000	200	320257	80210	80069	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	36	33	240171	0	0	36	240033	5	1	33	36	0	0	5110	1	16	2	1	80056	0	80000	10	6	240000	80100	80062	80060	80061	80233	80073
240204	80055	621	0	0	0	1	1	0	1	48	0	0	0	0	0	80042	2	19	18	92	25	320100	80161	240000	80100	240000	637561	3510413	80030	80055	80208	50015	3	50138	320100	200	240000	200	320000	80055	80055	1	1	80201	100	99	100	100	80000	80000	0	100	240130	0	36	0	240040	0	8	1052	240164	5	1	33	36	0	2	5110	2	16	2	1	80059	0	80083	6	6	240000	80100	80056	80059	80061	80230	80061
240204	80055	621	0	0	0	0	0	1	0	38	0	1	0	0	2	80196	2	17	19	11	25	320306	80100	240000	80182	240000	648937	3515413	80167	80211	80057	50400	3	50013	320352	200	240000	200	320257	80055	80055	2	1	80201	100	99	100	100	80000	80000	0	100	240000	0	36	0	240163	0	1	37	240033	5	1	33	35	0	0	5110	1	16	1	1	80051	0	80000	10	11	240000	80100	80106	80056	80061	80056	80056
240204	80055	621	0	0	0	0	0	0	0	59	0	0	0	0	0	80040	2	17	18	10	25	320100	80100	240000	80100	240000	641141	3512867	80030	80055	80055	50266	3	50013	320100	200	240000	200	320000	80060	80055	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	36	0	240037	0	0	40	240033	5	1	33	36	0	0	5110	1	16	1	1	80052	0	80000	6	6	240000	80100	80055	80061	80056	80056	80056
240204	80055	620	0	0	0	0	0	0	0	38	0	0	1	0	0	80040	2	19	17	11	25	320100	80100	240000	80100	240000	651144	3500724	80030	80055	80055	50272	3	50013	320100	200	240000	200	320000	80055	80057	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	36	28	240033	0	0	40	240163	5	1	33	0	0	0	5110	1	16	1	1	80058	0	80002	13	11	240000	80100	80069	80065	80072	80069	80066
240204	80065	652	0	0	0	0	0	0	0	66	0	0	0	1	2	80053	2	17	17	18	25	320100	80101	240000	80108	240000	655706	3500736	80043	80363	80865	49989	3	50022	320100	200	240000	200	320000	80064	80064	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	43	0	240042	0	1	44	240040	5	1	40	43	0	0	5110	1	16	1	1	80068	0	80000	10	11	240000	80100	80065	80065	80065	80065	80065
240204	80068	649	0	0	0	1	1	0	0	192	0	0	1	0	0	80044	2	19	19	13	25	320100	80100	240000	80100	240178	563949	3515269	80034	80176	80086	49986	3	50017	320100	200	240000	200	320000	80063	80059	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	36	0	240034	0	1	36	240033	6	1	31	36	0	0	5110	1	16	1	1	80055	0	80000	6	7	240000	80100	80059	80223	80065	80060	80063
240204	80058	653	0	0	0	1	0	20	3	50	0	0	1	0	1	80049	2	19	19	86	25	320100	80100	240000	80100	240000	865582	3507161	80034	80195	80071	49984	3	50017	320100	200	240000	200	320000	80075	80062	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	36	0	240033	0	2	49	240033	5	1	33	36	0	0	5124	1	16	1	1	80199	0	80000	6	6	240000	80100	80073	80060	80063	80062	80160
242420	80080	643	0	0	0	0	0	0	0	59	0	0	0	1	2	80043	2	18	17	12	25	320313	80100	240000	80100	240000	646736	3479227	80034	80245	80060	49982	3	50150	320100	200	240000	200	320000	80228	80059	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	36	0	240033	0	1	877	240033	5	1	33	36	0	0	5110	1	25	1	1	80058	0	80000	6	6	240000	80100	80056	80060	80218	80060	80063
240204	80065	644	0	0	0	0	0	0	0	50	88	0	0	0	0	80201	2	19	19	12	53	320100	80100	240130	80100	240000	623528	3507921	80034	80192	80069	49982	3	50017	320100	200	240000	200	320000	80059	80219	1	1	80201	100	99	100	100	80000	80000	0	100	240000	0	36	33	240040	0	2	853	240130	5	1	33	36	0	0	5110	1	16	1	1	80055	0	80000	6	6	240000	80100	80057	80063	80060	80060	80057

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4c	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80059	621	0	0	1	0	1	1	0	0	45	0	0	0	0	1	80040	2	17	19	0	16	25	320010	80010	240000	80010	240000	663693	3496713	0	1	0	0	80038	80061	80058	50000	3	50045	320010	20	240000	20	320000	80069	80066	2	1	80021	10	9	0	10	10	80000	80000	0	10	240015	15	43	0	240054	0	0	0	59	240041	5	1	0	0	0	0	5020	0	35	16	34	15	80042	80000	10	6	240000	80010	80069	80109	80061	80061	80048
240024	80060	621	0	0	0	0	0	0	0	0	45	0	0	0	0	2	80040	2	0	17	0	19	25	320010	80010	240130	80010	240000	675547	3520969	0	1	0	0	80024	80202	80045	50004	3	50040	320010	20	240000	20	320000	80053	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	36	0	240033	0	0	0	40	240033	5	1	33	43	0	0	5020	0	34	16	34	34	80042	80000	0	6	240000	80010	80061	80065	80061	80056	80056
240024	80060	620	0	0	0	0	0	0	0	0	0	0	0	0	0	1	80040	2	17	17	0	0	25	320201	80010	240000	80010	240000	666680	3519409	0	1	0	0	80042	80060	80055	50010	3	50040	320010	20	240000	20	320000	80060	80062	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	35	0	240033	0	0	0	40	240040	5	0	0	36	0	0	5034	0	15	16	36	34	80060	80000	6	6	240000	80010	80056	80056	80046	80056	80056
240024	80210	621	0	0	0	0	0	0	0	0	45	0	0	0	0	2	80049	3	14	17	0	92	25	320010	80010	240000	80010	240000	675547	3508995	0	1	0	0	80030	80063	80060	50005	3	50035	320010	20	240000	20	320257	80060	80055	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	36	0	240040	0	1	0	43	240000	5	1	0	0	0	0	5020	0	34	16	34	34	80058	80000	0	6	240000	80010	80056	80056	80056	80056	80056
240024	80060	620	0	0	0	0	1	0	0	0	62	0	0	0	0	0	80045	2	17	0	0	20	25	320010	80010	240000	80010	240000	666680	3501161	0	1	0	0	80039	80055	80060	49990	3	50040	320010	20	240000	20	320000	80060	80059	1	1	80021	10	9	0	10	10	80000	80000	4	10	240000	0	36	0	240037	0	0	0	42	240033	5	1	0	36	0	0	5020	0	34	15	34	16	80052	80000	6	6	240000	80010	80056	80056	80203	80056	80046
240024	80061	621	0	0	0	0	1	0	0	0	45	0	0	0	0	2	80040	2	0	17	0	16	25	320010	80010	240000	80010	240000	612348	3519409	0	1	0	0	80035	80062	80060	50010	3	50039	320010	20	240000	20	320000	80056	80056	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	36	33	240040	0	1	0	0	240040	5	1	0	36	0	0	5020	0	34	16	32	13	80057	80000	6	6	240000	80010	80056	80056	80060	80046	80049
240024	80060	620	0	0	0	0	1	1	0	0	45	0	0	0	0	0	80030	2	17	17	0	16	25	320010	80010	240000	80010	240000	666680	3501161	0	1	0	0	80030	80055	80059	50006	3	50064	320010	20	240000	20	320000	80060	80055	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	36	0	240033	0	0	0	44	240033	5	0	40	0	0	0	5034	0	34	16	34	34	80057	80000	10	6	240000	80010	80056	80061	80046	80056	80057
240024	80223	620	0	0	0	0	1	0	0	0	38	0	1	0	0	0	80030	0	19	19	0	9	25	320010	80010	240000	80010	240000	653701	3549999	0	1	0	0	80035	80065	80060	50001	3	50041	320010	20	240193	20	320000	80055	80055	1	1	80021	10	9	0	10	10	80000	80000	1	10	240000	0	36	0	240040	0	1	0	33	240036	5	1	32	36	0	0	5020	0	35	16	34	35	80193	80000	10	6	240000	80010	80062	80064	80062	80061	80055
240024	80061	620	0	0	0	0	0	0	0	0	45	0	1	0	0	2	80040	3	19	19	0	0	25	320010	80010	240000	80010	240000	644738	3487120	0	1	0	0	80030	80060	80066	50000	3	50171	320010	20	240000	20	320000	80065	80045	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	43	0	240033	0	0	0	3	240040	5	1	36	0	0	0	5020	0	17	15	34	15	80042	80000	0	6	240000	80010	80046	80218	80046	80062	80056
240024	80059	620	0	0	0	0	1	1	0	0	38	0	1	0	0	0	80040	1	0	19	0	16	25	320010	80010	240000	80010	240000	633977	3549807	0	1	0	0	80035	80045	80062	50012	3	50024	320010	20	240000	20	320000	80060	80055	1	1	80021	10	9	0	10	10	80000	80000	0	10	240000	0	39	31	240040	0	1	0	40	240040	6	1	33	43	0	0	5020	0	34	16	35	16	80061	80000	10	6	240000	80010	80061	80056	80067	80046	80046

LD1 (multiple, post-index, 3 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations