Firestorm: LD1 (multiple, post-index, 4 regs, 16B) measurements

Code:

  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29477	236	19	0	1	18	0	0	0	0	0	12	0	0	0	0	4663	29170	3	4	23277	5000	1000	4000	1000	4000	5000	20712	7	0	0	16934	28914	29304	3	10	5000	4000	5000	29267	29191	1	1	61001	1000	1000	0	4000	0	11	4006	0	0	0	0	4006	6	1	0	0	0	13197	9566	6982	3146	8	40	20259	3283	3812	13	43	45	28582	1000	16008	13202	14509	4000	1000	29361	29420	29386	29351	29251
64004	29231	236	16	0	0	16	0	0	0	0	0	17	0	0	0	0	4615	29082	4	4	23345	5000	1000	4000	1000	4000	5000	20702	4	0	0	16933	28835	29409	3	10	5000	4000	5000	29294	29166	1	1	61001	1000	1000	1	4000	0	0	4006	0	0	0	6	4006	6	1	6	0	48	13271	9389	6896	3138	10	41	20353	3230	3808	18	44	42	28635	1000	16393	13206	14370	4000	1000	29318	29336	29430	29243	29278
64004	29272	236	14	0	0	12	0	0	0	0	0	12	0	0	0	0	4727	29134	4	0	23319	5000	1000	4000	1000	4000	5000	20718	8	0	0	16920	28852	29415	3	10	5000	4000	5000	29118	29216	1	1	61001	1000	1000	0	4000	0	11	4000	0	0	0	7	4000	0	1	6	0	0	13026	9605	6955	3114	6	43	20325	3187	3810	17	44	42	28653	1000	16086	13161	14579	4000	1000	29379	29392	29449	29319	29319
64004	29360	237	17	0	0	10	0	0	0	0	0	30	0	0	0	0	4705	29236	0	0	23410	5000	1000	4000	1000	4000	5000	20710	0	0	0	16927	28804	29405	3	10	5000	4000	5000	29195	29162	1	1	61001	1000	1000	0	4000	0	11	4006	0	0	0	6	4007	6	1	7	0	0	13215	9423	6927	3137	4	38	20370	3324	3815	10	41	46	28602	1000	16263	13218	14429	4000	1000	29437	29347	29522	29228	29312
64004	29299	236	12	0	1	14	0	1	0	0	0	13	0	0	0	0	4634	29146	4	0	23347	5000	1000	4000	1000	4000	5000	20702	0	0	0	16949	28797	29440	3	10	5000	4000	5000	29345	29250	1	1	61001	1000	1000	0	4000	0	8	4000	0	1	0	2	4000	0	0	0	0	0	13153	9575	6974	3192	7	42	20389	3289	3819	10	46	43	28671	1000	16030	12986	14501	4000	1000	29471	29352	29413	29463	29394
64004	29399	236	17	0	0	16	0	0	0	0	0	8	0	0	0	0	4771	29158	0	0	23397	5000	1000	4000	1000	4000	5000	20709	0	0	0	16959	28834	29294	3	10	5000	4000	5000	29389	29274	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	2	4000	6	0	3	8	0	13319	9295	6917	3176	4	38	20312	3216	3821	9	41	46	28726	1000	15984	13212	14358	4000	1000	29470	29479	29406	29474	29364
64004	29277	235	18	0	0	19	0	0	0	0	0	17	0	0	0	0	4709	29211	0	0	23347	5000	1000	4000	1000	4000	5000	20693	0	0	0	16985	28861	29350	3	10	5000	4000	5000	29360	29264	1	1	61001	1000	1000	0	4000	0	8	4002	0	0	0	3	4000	6	1	0	8	84	13206	9534	6890	3140	7	43	20277	3256	3822	14	47	41	28697	1000	16183	13174	14422	4000	1000	29507	29254	29428	29385	29519
64004	29395	236	16	0	0	17	0	0	0	0	0	5	0	0	0	0	4589	29145	0	0	23318	5000	1000	4000	1000	4000	5000	20700	2	0	0	16937	28816	29262	3	10	5000	4000	5000	29312	29322	1	1	61001	1000	1000	0	4000	0	0	4003	0	0	0	2	4002	5	1	2	0	0	13157	9593	6901	3140	6	41	20492	3240	3821	10	37	37	28725	1000	16387	12994	14629	4000	1000	29310	29405	29509	29282	29315
64004	29431	235	18	0	0	17	0	0	0	0	0	8	0	1	0	0	4625	29248	0	0	23422	5000	1000	4000	1000	4000	5000	20714	0	0	0	16945	28848	29273	3	10	5000	4000	5000	29270	29207	1	1	61001	1000	1000	0	4000	0	0	4000	0	0	0	2	4002	6	1	0	8	0	13145	9371	6915	3159	5	41	20405	3323	3823	13	39	41	28667	1000	16139	13222	14150	4000	1000	29487	29378	29403	29465	29313
64004	29471	236	16	0	0	16	0	0	1	0	0	0	0	0	0	0	4568	29150	0	4	23424	5000	1000	4000	1000	4000	5000	20710	0	0	0	16902	28828	29381	3	10	5000	4000	5000	29374	29207	1	1	61001	1000	1000	0	4000	0	0	4000	0	0	0	2	4000	6	1	2	0	0	13030	9376	6898	3150	3	38	20492	3317	3820	14	40	46	28664	1000	16165	13304	14785	4000	1000	29501	29287	29355	29387	29400

Count: 8

Code:

  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	106730	857	1	0	0	0	50	0	1	0	0	106722	2	4	15	17	51	400100	80100	320130	80100	320178	480494	4734479	0	9	106702	0	106722	106727	26656	3	26710	400100	200	320000	200	400000	106878	106721	1	1	80201	100	99	1	100	100	80000	80000	0	100	320000	0	0	30	320042	0	0	0	0	320164	6	1	34	45	0	0	5110	1	16	1	1	106870	80000	10	6	0	320000	80100	106722	106871	106722	106728	106738
320204	106721	828	0	0	1	0	48	0	0	0	2	106719	2	15	15	93	25	400278	80100	320130	80100	320178	480494	4734479	0	5	106708	0	106876	106727	26745	3	26802	400100	200	320000	200	400000	106879	106728	1	1	80201	100	99	1	100	100	80000	80000	0	100	320000	0	38	0	320034	0	0	0	42	320041	6	1	34	38	0	0	5110	1	25	1	1	106718	80000	10	6	0	320000	80100	106728	106722	106858	106728	106873
320204	106721	827	0	0	1	0	180	0	0	0	2	106864	2	15	15	17	50	400100	80100	320000	80100	320000	480496	4663797	0	0	106834	0	106727	106877	26675	3	26704	400100	200	320192	200	400240	106727	106873	1	1	80201	100	99	1	100	100	80000	80000	0	100	320000	2	38	0	320042	0	0	0	42	320042	6	1	34	45	0	0	5110	1	16	1	1	106718	80000	10	6	0	320000	80100	106728	106730	106728	106731	106728
320204	106727	827	0	0	0	0	48	0	0	1	2	106693	2	9	15	17	25	400100	80100	320000	80100	320000	480493	4734479	0	5	106696	0	106727	106727	26669	3	26710	400100	200	320000	200	400000	106721	106721	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	38	0	320042	0	0	0	34	320042	6	1	34	45	0	0	5109	2	16	1	1	106725	80000	12	6	0	320000	80100	106729	106729	107025	106728	106879
320204	106735	857	0	0	0	0	312	0	0	0	2	106712	2	15	18	17	50	400100	80100	320000	80100	320000	480494	4704308	0	0	107015	0	106727	106727	26675	3	26803	400100	200	320000	200	400000	106879	106708	1	1	80201	100	99	1	100	100	80000	80000	0	100	320000	2	38	0	320042	0	0	0	42	320034	6	1	38	38	2	0	5110	1	16	2	1	106860	80048	10	6	0	320000	80100	106880	106722	106729	106879	106728
320204	106880	827	0	0	0	0	48	0	0	0	0	106712	2	15	0	17	25	400100	80147	320000	80147	320000	480780	4644056	0	1	106875	0	106874	106727	26749	3	26808	400100	200	320000	200	400000	106877	106721	1	1	80201	100	99	0	100	100	80000	80000	1	100	320132	0	41	0	320174	0	0	0	832	320172	6	1	34	45	0	0	5123	1	16	1	1	106724	80000	11	6	0	320000	80100	106728	106877	106728	106728	106728
320204	106771	827	1	0	0	0	48	0	0	0	2	106712	2	15	15	17	25	400100	80100	320000	80100	320000	480494	4734479	0	4	106711	0	106727	106727	26656	3	26710	400100	200	320000	200	400000	106727	106727	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	38	0	320042	0	0	0	42	320042	6	1	34	45	0	0	5110	1	16	1	1	106718	80000	6	6	0	320000	80100	106722	106728	106728	106722	106722
320204	106721	827	0	0	0	0	40	0	0	1	0	106712	2	15	15	0	25	400100	80100	320000	80100	320000	480494	4721339	0	0	106836	0	106875	106727	26675	3	26710	400325	200	320000	200	400000	106727	106870	1	1	80201	100	99	1	100	100	80000	80000	0	100	320130	0	38	0	320042	0	0	0	42	320172	6	1	34	45	0	0	5123	1	16	1	1	106722	80000	10	7036	0	320000	80100	106744	106735	106756	106729	106736
320204	106730	858	1	1	1	0	69	0	1	0	2	106721	3	4	4	23	25	400101	80100	320130	80100	320000	480484	4734672	0	1	106710	0	106735	106736	26683	11	26718	400100	200	324608	200	400000	106731	106735	1	1	80201	100	99	5	100	100	80000	80000	0	100	320000	0	45	0	320042	0	1	0	845	320042	6	1	41	45	0	0	5246	1	17	1	1	106866	80000	14	10	0	320000	80100	106735	106739	106764	106890	106736
320204	106881	867	0	0	0	0	61	88	0	0	2	106720	3	4	4	24	25	400100	80194	320000	80100	320178	480493	4734863	0	2	106849	0	106736	106735	26660	3	26812	400100	200	320000	200	400240	106743	106882	1	1	80201	100	99	5	100	100	80000	80000	0	100	320130	0	45	0	320034	0	1	0	37	320042	6	1	34	45	0	0	5109	1	17	1	1	106723	80000	6	6	0	320000	80100	106732	106727	106730	106725	106876

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	106733	827	0	0	1	1	0	0	69	0	0	0	2	106716	3	4	4	21	25	400010	80010	320000	80010	320000	480042	4734671	0	106706	106731	106735	26679	3	26710	400010	20	320000	20	400000	106727	106731	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	0	45	320042	6	1	0	45	0	0	0	5020	4	16	3	3	106732	80000	14	10	320000	80010	106874	106735	106732	106735	106713
320024	106727	827	0	0	0	0	0	0	47	0	0	0	2	106696	3	4	4	21	25	400010	80010	320000	80010	320000	480044	4734671	0	106706	106731	106731	26682	3	26714	400010	20	320000	20	400000	106731	106728	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	1	0	45	320042	6	1	42	45	0	0	0	5020	4	16	5	5	106732	80000	14	10	320000	80010	107040	106861	106750	106709	106713
320024	106732	828	0	0	0	0	0	0	48	0	0	0	2	106719	3	1	4	0	25	400010	80010	320000	80010	320000	480044	4662421	0	106706	106735	106731	26679	3	26710	400010	20	320000	20	400000	106731	106731	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	1	0	45	320042	6	1	42	0	0	0	0	5020	5	16	3	3	106724	80000	14	10	320000	80010	107035	106745	106745	106709	106732
320024	106735	827	0	0	0	0	0	0	60	0	0	0	0	106716	2	4	4	21	25	400010	80010	320000	80010	320000	480044	4734671	0	106710	106731	106731	26679	3	26714	400010	20	320000	20	400000	106727	106727	1	1	80021	10	9	1	10	10	80000	80000	0	10	320000	2	36	0	320041	0	1	0	42	320041	6	1	42	45	0	1	0	5020	3	16	3	3	106728	80000	14	10	320000	80010	106850	106746	106729	106732	106732
320024	106731	827	0	0	0	0	0	0	48	0	0	0	2	106716	3	1	4	21	25	400010	80010	320000	80010	320000	480044	4734672	0	106706	106731	106731	26679	3	26714	400010	20	320000	20	400000	106731	106708	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	1	0	45	320042	6	1	0	0	0	0	0	5020	4	16	3	3	106724	80000	14	14	320000	80010	107032	106892	106747	106732	106732
320024	106766	827	0	0	0	0	0	0	60	0	0	0	2	106720	3	4	4	21	25	400010	80010	320000	80010	320000	480044	4689029	0	106711	106735	106743	26679	3	26715	400010	20	320000	20	400000	106733	106727	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	0	0	320042	6	1	0	45	0	0	0	5020	4	16	5	3	106724	80000	15	10	320000	80010	107032	106888	106749	106732	106713
320024	106708	827	0	0	0	0	0	0	48	0	0	0	0	106720	3	4	4	21	25	400010	80010	320000	80010	320000	480047	4734479	0	106706	106731	106731	26683	3	26718	400010	20	320000	20	400000	106731	106731	1	1	80021	10	9	1	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	0	0	320042	6	0	42	45	0	0	0	5020	3	16	4	3	106728	80000	14	14	320000	80010	107036	106845	106737	106733	106709
320024	106731	827	0	0	0	0	0	0	48	0	0	0	2	106716	3	4	4	1	25	400010	80010	320000	80010	320000	480044	4734863	0	106706	106731	106731	26679	3	26714	400010	20	320000	20	400000	106735	106731	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320000	0	0	0	0	320000	6	0	42	45	0	0	0	5020	4	16	4	4	106735	80000	0	0	320000	80010	106867	106752	106732	106732	106732
320024	106727	827	0	0	1	0	0	0	48	0	0	0	0	107015	0	4	4	173	79	400365	80104	320130	80057	320356	480609	4669454	1	106975	107029	107033	26827	19	26901	400685	20	320576	20	400240	110069	110196	23	1	80021	10	9	5	10	10	80000	80000	0	10	320780	4	45	210	320780	0	0	1	5907	320952	6	1	42	45	0	0	0	5098	4	34	5	5	107651	80047	10	14	320000	80010	107343	107051	107033	107184	107008
320024	107013	829	1	0	0	0	0	0	0	0	0	0	2	106716	3	0	4	23	25	400010	80010	320000	80010	320000	480044	4734671	0	106706	106739	106735	26679	3	26714	400010	20	320000	20	400000	106735	106730	1	1	80021	10	9	5	10	10	80000	80000	0	10	320019	0	45	0	320042	0	1	0	45	320039	6	1	42	45	0	0	0	5020	3	16	4	3	106730	80000	14	10	320000	80010	106876	106746	106732	106709	106732

LD1 (multiple, post-index, 4 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations