Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 4 regs, 1D)

Test 1: uops

Code:

  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)0e0f181e1f22243a3f43464951schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
640052897223224021110601047382849202023685300010002000100020005000100030201622128423289393103000400040002866428735116100110001000020004200220220024260012885916669483163116320008321138002467692816010001544613184140772000200010002879328894288052882728855
64004288662333402700070104665283600112376230001000200010002000500010000071625728330288403103000400040002873528818116100110001000020004200220220024260013051957968673168117219930320438042561632827310001552213314143392000200010002908828979289192892228903
6400428845232230220001000046382853002223689300010002000100020005000100000111624328378290443103000400040002877728750116100110001000020004200210220024240013246936869443081136419831323138101866722825110001585313252147462000200010002899628904290742898428826
64004289902322501900013000470728533022237983000100020001000200050001000000162492854429005310300040004000288442886411610011000100002000420021049720024240013276935469033213186219758328838061964652823910001545813075149732000200010002895529001290482886828964
64004288592312202600060004603285730222377630001000200010002000500010000091626728344289083103000400040002877928856116100110001000020004200220220022240013103925169543150126820024318538032867572825710001542512794141592000200010002903928991290852904528942
640042884823226029000700047942853902223794300010002000100020005000100000111623028416288073103000400040002874928807116100110001000020004200210020004260013153957368453172117019775323038032061682823410001590613018145352000200010002901828945288542892128943
640042879623225025100400046262854702123692300010002000100020005000100010171624028333289043103000400040002880928778116100110001000120004200210220024240013425923668613090157319683319938142163652836010001573013196145082000200010002886828862289992908829052
640042911223123026000700047232858002223751300010002000100020005000100000121634328462289843103000400040002864428773116100110001000020004200210220024260013101938569533151166820046322138102161672832510001574213173146322000200010002885728902289442896229015
64004290842312602000040004678285720022373730001001200010002000500010000015162452841028934310300040004000287272884611610011000100002000420020022002424001318892206825307186420094327838093562612826410001562313071142762000200010002894728975288492892528931
6400428981231260210004010479228568002235663000100020001000200050001000006162362857028883310300040004000288302869411610011000100002000420001022002404001308292086867313996519915316338052166682836110001603713030145232000200010002892329003289292891228941

Test 2: throughput

Count: 8

Code:

  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1i tlb fill (04)l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f22233a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3202058006964311000000057000280026214140252401008010016000080100160000480499960038080016800418004102823240100200320000200320000800418004111802011009910010080000800001100160011124016004610150160000614740101510911722800388000099160000160000801008004280042800428004280042
32020480041643011000000560002800262015025240100801001600008010016000048049996094908001680041800410323240100200320000200320000800418004111802011009910010080000800000100160011114016004600048160036614840110510921711800388000009160000160000801008004280042800428004280042
32020480041643011010000560102800262131502524010080100160000801001600004804999600541800168004180041032324010020032000020032000080041800411180201100991001008000080000110016001211401600460004816003761100100511121722800388000099160000160000801008004280042800428004280042
320204800416420101000005600038002621414025240100801001600008010016000048049996091518001680041800410323240100200320000200320000800418004111802011009910010080000800001100160011104016004900151160036614740110510911722800388000099160000160000801008004280042800428004280042
3202048004164301000000057000380026215152725240100801001603128010016000048049996087708011580041800410323240100200320000200320000800418004111802011009910010080000800000100160012114016004801047160036014640110510911721800388000099160000160000801008004280042800428004280042
320204800416430100000005600038002621414225240100801001600008010016000048049996089008001680041800410323240100200320000200320000800418004111802011009910010080000800000100160012104016004600148160036004840110511121722800388000009160000160000801008004280042800428004280042
320204800416430100000005600048002621416025240100801001600008010016000048049996087708001680041800410323240100200320000200320000800418004111802011009910010080000800000100160012104316004800148160036614640110510921711800388000099160000160000801008004280042800428004280042
3202048004164301010000056000280026214140252401008010016000080100160000480499960064180016800418004103232401002003200002003200008004180041118020110099100100800008000011001600111140160048100501600366146401005111117218003880000109160000160000801008004280042800428004280042
32020480041643011010000520002800262151502524010080100160000801001600004804999609190800168004180041032324010020032000020032000080041800411180201100991001008000080000010016001111401600470004716003661484011051112173180038800001011160000160000801008004280042800428004280042
320204800416430110000005500038002621514025240100801001600008010016000048049996091918001680041800410323240100200320000200320000800418004111802011009910010080000800000100160011124016004801047160000614740100511121722800388000099160000160000801008004280042800428004280042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f23243a3f4346494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3200258005662011010006600028002621414025240010800101600008001016000048004996087608001680041800410323240010203200002032000080041800411180021109101080000800001101600111140160049000471600376110421015019217228003808000090160000160000800108004280042800428004280042
3200248004162011100005400008002621514025240010800491600788001016000048004996088408001680041800410323240010203200002032000080041800411180021109101080000800000101600111140160010000461600376148401115019217228003808000099160000160000800108004280042800428004280042
320024800416201000000230000800262012025240010800101600008001016000048004996036808001680041800410323240010203200002032000080041800411180021109101080000800000101600101240160049000481600006146401105019417228003818000066160000160000800108004280042800428004280042
3200248004162010000000000080026212140252400108001016000080010160000480049960328080016800418004103232400102032000020320000800418004111800211091010800008000001016001113401600491004716003601474011050392172280038180000116160000160000800108004280042800428004280042
320024800416200000000520002800262012025240010800101600008001016000048004996088708001680041800410323240010203200002032000080041800411180021109101080000800000101600101040160048001111600366111401115019217228003808000090160000160000800108004280042800428004280042
320024800416201000000600001800262121202524001080010160000800101600004800499600290800168004180041032324001020320000203200008004180041118002110910108000080000010160000114016003000030160035614840005019217228003808000000160000160000800108004280042800428004280042
32002480041620100000023000180026212120472400108001016000080010160000480049960361080016800418004103232400102032000020320000800418004111800221091010800008000001016001302516003000051160029613200150195172280038180000106160000160000800108004280042800428004280042
320024801136201000000360001800262014025240010800101600008001016000048004996035908001680111800410323240010203200002032000080041800411180021109101080000800000101600001225160022000331600300030401105042317228003808000099160000160000800108004280042800428004280042
320024800416201100000660000800263000252400108001016000080010160000480049960029080016800418004103232400102032000020320000800418004111800211091010800008000001016000002516001002001600306130330050192172280038180000910160000160000800108004280042800428004280042
320024800416201010000360001800263151502524001080010160000800101600004800499601890800168004180041032324001020320000203200008004180041118002110910108000080000010160000104016003000030160037614840005019217228003808000009160000160000800108004280042800428004280042