Firestorm: LD1 (multiple, post-index, 4 regs, 2D) measurements

Code:

  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
64005	28622	223	7	2	0	1	0	0	1	0	1	0	12	88	0	4783	28544	0	0	0	22660	5000	1000	4000	1000	4004	5000	20715	6	16827	28312	28598	7	10	5000	4000	5005	28497	28472	1	1	61001	1000	1000	0	4000	4	8	4006	0	0	0	791	4004	5	1	4	0	0	0	13069	9616	6930	3220	1	54	19606	3165	3801	33	54	52	28065	1000	15556	12351	13858	4000	1000	28573	28730	28620	28629	28709
64004	28684	222	1	1	0	0	1	0	0	1	0	0	12	0	0	4799	28432	0	0	0	22749	5000	1000	4000	1000	4000	5000	20718	10	16938	28210	28696	3	10	5000	4000	5000	28634	28582	1	1	61001	1000	1000	0	4000	4	11	4006	3	0	0	13	4006	5	1	0	0	0	150	13279	9762	6990	3263	1	61	19705	3250	3803	21	56	51	28159	1000	15193	12483	13686	4000	1000	28712	28702	28639	28676	28790
64004	28491	222	0	1	0	0	1	0	0	0	0	0	0	0	0	4506	28478	0	0	0	22574	5000	1000	4000	1000	4000	5000	20713	15	16898	28301	28634	3	10	5000	4000	5000	28545	28593	1	1	61001	1000	1000	0	4000	0	8	4006	0	0	0	6	4006	0	0	6	11	0	0	13339	9445	6971	3242	0	56	19651	3256	3804	26	54	53	28070	1000	15134	12369	13745	4000	1000	28554	28522	28603	28719	28540
64004	28601	222	0	1	0	0	1	0	0	0	0	0	24	0	0	4697	28355	0	0	0	22764	5000	1000	4000	1000	4000	5000	20714	14	16928	28335	28656	3	10	5000	4000	5000	28523	28525	1	1	61001	1000	1000	0	4000	0	8	4006	0	2	0	0	4000	0	0	4	0	0	0	13124	9416	6990	3190	0	50	19695	3189	3799	18	50	52	28085	1000	15149	12485	13648	4000	1000	28733	28632	28775	28761	28649
64004	28570	223	0	0	0	0	1	0	0	0	0	0	12	0	0	4757	28512	0	4	4	22536	5000	1000	4000	1000	4000	5000	20730	8	16921	28301	28588	3	10	5000	4000	5000	28508	28612	1	1	61001	1000	1000	0	4000	0	12	4006	0	0	0	6	4007	5	0	0	12	0	0	13239	9382	6958	3159	0	61	19566	3157	3805	22	57	49	28126	1000	15531	12423	13858	4000	1000	28696	28705	28665	28638	28628
64004	28596	222	0	0	0	0	1	0	0	0	0	0	0	0	0	4908	28445	0	0	0	22661	5000	1000	4000	1000	4000	5000	20720	13	16938	28311	28670	3	10	5000	4000	5000	28511	28497	1	1	61001	1000	1000	0	4000	0	0	4006	0	0	0	6	4000	5	0	0	0	0	0	13234	9611	6906	3131	0	53	19789	3240	3804	24	53	64	28055	1000	15174	12495	13860	4000	1000	28678	28753	28554	28795	28805
64004	28794	222	0	1	0	0	1	0	0	0	0	0	12	0	0	4761	28496	0	0	0	22557	5000	1000	4000	1000	4000	5000	20713	12	16904	28302	28649	3	10	5000	4000	5000	28572	28600	1	1	61001	1000	1000	0	4000	0	8	4017	0	0	0	12	4006	5	1	6	11	0	0	13183	9507	6980	3208	0	57	19743	3149	3811	20	56	59	28165	1000	15549	12308	13710	4000	1000	28635	28711	28750	28628	28702
64004	28710	222	1	0	0	0	1	0	0	0	0	0	12	0	1	4793	28468	0	0	0	22609	5000	1000	4000	1000	4000	5000	20732	12	16953	28313	28623	3	10	5000	4000	5000	28501	28522	1	1	61001	1000	1000	0	4000	5	12	4006	0	0	0	3	4006	5	1	6	0	0	0	13234	9541	7017	3203	0	55	19734	3221	3804	17	59	56	28119	1000	15408	12692	13569	4000	1000	28795	28719	28684	28676	28629
64004	28750	221	0	1	0	0	1	0	0	0	0	0	12	0	0	4647	28570	0	0	4	22642	5000	1000	4000	1000	4000	5000	20712	6	16923	28312	28500	3	10	5000	4000	5000	28511	28462	1	1	61001	1000	1000	0	4000	0	8	4006	0	2	0	0	4000	0	1	0	12	0	0	13367	9670	6929	3196	0	57	19747	3159	3809	26	53	55	28067	1000	15344	12205	13538	4000	1000	28711	28801	28747	28627	28604
64004	28841	223	0	1	0	0	1	0	0	0	0	0	12	0	0	4811	28599	0	4	4	22644	5000	1000	4000	1000	4000	5000	20723	8	16941	28321	28720	3	10	5000	4000	5000	28631	28510	1	1	61001	1000	1000	0	4000	4	0	4006	0	1	0	7	4000	6	1	0	12	0	0	13417	9553	7064	3209	0	54	19801	3182	3814	21	53	52	28119	1000	15684	12681	13700	4000	1000	28723	28512	28607	28694	28685

Count: 8

Code:

  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	18	19	1e	1f	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	106745	799	1	0	0	0	1	0	0	0	65	0	0	3	106726	2	7	7	21	25	400100	80100	320000	80100	320000	480495	4727743	1	0	0	106711	0	106740	106741	26688	14	26722	400100	200	320000	200	400000	106736	106741	1	1	80201	100	99	0	100	100	80000	80000	0	100	320019	19	45	0	320059	1	1	0	59	320041	6	1	59	45	18	0	0	5109	3	0	1	17	1	1	106737	80000	13	13	2	320000	80100	106738	106737	106737	106742	106737
320204	106736	827	1	0	0	0	1	0	0	0	90	0	0	2	106721	3	7	7	23	25	400101	80100	320000	80100	320000	480496	4700343	1	0	0	106712	0	106740	106737	26685	3	26719	400100	200	320000	200	400000	106736	106736	1	1	80201	100	99	0	100	100	80000	80000	0	100	320018	18	45	0	320059	1	0	0	59	320041	6	1	60	45	18	0	0	5110	3	0	1	17	1	1	106740	80000	13	13	2	320000	80100	106737	106737	106741	106737	106742
320204	106737	827	1	0	1	0	0	0	0	0	66	0	0	2	106721	2	7	7	19	25	400100	80100	320000	80100	320000	480491	4668930	1	0	0	106711	0	106737	106737	26688	3	26722	400100	200	320000	200	400000	106740	106737	1	1	80201	100	99	4	100	100	80000	80000	1	100	320018	20	45	0	320059	0	0	1	59	320041	6	1	57	45	18	0	0	5110	3	4	1	16	1	1	106734	80000	13	13	2	320000	80100	106740	106739	106740	106737	106741
320204	106749	828	1	0	1	0	0	0	0	0	66	0	0	2	106721	2	7	7	20	25	400100	80100	320000	80100	320000	480496	4668227	1	5	0	106711	0	106743	106740	26684	3	26719	400100	200	320000	200	400000	106736	106740	1	1	80201	100	99	4	100	100	80000	80000	0	100	320017	19	45	0	320190	1	1	1	68	320042	6	1	59	45	18	1	0	5109	8	4	1	16	1	1	106733	80000	13	13	2	320000	80100	106741	106739	106737	106738	106737
320204	106736	827	1	0	0	0	0	0	0	0	75	0	0	3	106722	2	7	7	23	25	400100	80100	320000	80100	320000	480496	4727695	1	5	0	106711	0	106738	106736	26757	3	26720	400100	200	320000	200	400000	106736	106887	1	1	80201	100	99	4	100	100	80000	80000	0	100	320019	18	45	0	320059	1	0	0	59	320041	6	1	60	45	18	1	0	5110	8	4	1	17	1	1	106733	80000	13	13	4	320000	80100	106738	106741	106740	106737	106737
320204	106736	827	1	0	2	0	1	0	0	0	65	0	0	2	106722	2	7	7	21	25	400100	80149	320000	80100	320000	480495	4736504	1	5	0	106711	0	106740	106741	26684	3	26718	400100	200	320000	200	400000	106736	106737	1	1	80201	100	99	4	100	100	80000	80000	0	100	320018	18	45	0	320059	0	2	1	62	320041	6	1	60	44	18	3	0	5110	8	4	1	17	1	1	106733	80000	13	13	2	320000	80100	106737	106737	106738	106738	106737
320204	106736	827	1	0	1	0	1	0	0	0	64	0	0	2	106721	2	7	7	25	25	400100	80100	320000	80100	320000	480496	4668227	1	5	0	106844	0	106737	106736	26684	3	26720	400100	200	320000	200	400000	106736	106740	1	1	80201	100	99	4	100	100	80000	80000	0	100	320019	18	51	0	320058	0	0	0	62	320041	6	1	59	45	18	0	0	5110	8	0	1	17	1	1	106733	80000	13	13	2	320000	80100	106737	106737	106737	106741	106737
320204	106745	827	1	0	0	0	1	0	0	0	65	0	0	2	106724	2	7	7	22	25	400100	80100	320000	80100	320000	480496	4668028	1	5	0	106711	0	106740	106743	26688	3	26718	400100	200	320000	200	400000	106736	106736	1	1	80201	100	99	4	100	100	80000	80000	0	100	320018	18	45	30	320059	1	0	0	60	320041	6	1	59	45	18	1	0	5110	8	4	1	17	1	1	106733	80000	13	13	2	320000	80100	106741	106739	106737	106738	106741
320204	106740	827	1	0	1	0	0	0	0	0	65	0	0	3	106726	3	7	7	21	25	400100	80100	320000	80100	320000	480496	4669130	1	5	0	106715	0	106736	106736	26688	11	26718	400100	200	320000	200	400000	106736	106740	1	1	80201	100	99	4	100	100	80000	80000	0	100	320018	18	45	0	320059	1	0	0	62	320042	6	1	59	45	18	0	0	5110	8	4	1	17	1	2	106733	80000	13	13	2	320000	80100	106738	106737	106885	106737	106737
320204	106736	828	1	0	1	0	1	0	0	0	162	0	0	2	106721	3	7	7	21	25	400100	80100	320130	80100	320000	480496	4668930	1	5	1	106712	0	106740	106736	26688	3	26722	400100	200	320000	200	400000	106736	106736	1	1	80201	100	99	4	100	100	80000	80000	0	100	320018	19	45	0	320059	0	0	0	60	320040	6	1	59	45	18	1	0	5109	8	4	1	25	1	1	106734	80000	13	13	2	320000	80100	106737	106742	106737	106738	106738

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	106727	827	0	0	0	0	0	0	0	0	0	108	0	0	0	1	106724	3	15	4	24	25	400010	80010	320000	80010	320000	480044	4734768	0	0	0	106706	107040	106760	26691	3	26717	400010	20	320000	20	400000	106731	106727	1	1	80021	10	9	0	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	0	51	320042	6	1	42	45	0	0	0	0	5020	10	16	0	9	6	106732	80000	14	12	320000	80010	106728	106728	106728	106732	106732
320024	106877	827	0	0	0	0	0	1	1	0	0	48	0	0	0	2	106712	3	4	4	22	25	400010	80010	320000	80010	320000	480044	4734671	0	0	0	106706	107053	106863	26675	3	26714	400010	20	320000	20	400000	106734	106727	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	0	837	320042	6	1	41	45	0	0	0	0	5020	5	16	0	9	8	106728	80000	14	10	320000	80010	106734	106732	106735	106889	106732
320024	106731	827	0	0	0	0	0	0	0	0	0	180	0	1	0	2	106716	3	4	4	27	25	400010	80010	320000	80057	320000	480044	4734816	0	0	0	106710	107038	106877	26679	3	26714	400010	20	320000	20	400000	106731	106727	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	2	45	0	320042	0	0	0	45	320042	6	1	42	45	0	0	0	0	5020	8	16	0	8	8	106732	80000	14	14	320000	80010	106732	106732	106728	106732	106728
320024	106727	827	0	0	0	0	0	0	0	0	0	48	0	0	0	1	106713	3	15	4	21	25	400010	80010	320000	80010	320000	480044	4625188	0	0	0	106706	107040	106855	26683	3	26714	400010	20	320000	20	400000	106887	106727	1	1	80021	10	9	5	10	10	80000	80000	1	10	320000	0	45	0	320042	0	0	0	42	320042	6	1	42	45	0	0	0	0	5020	7	16	1	8	8	106728	80000	14	10	320000	80010	106732	106728	106732	106736	106736
320024	106731	827	0	0	0	0	0	0	0	0	0	47	0	0	0	2	106716	3	4	0	21	25	400010	80010	320000	80010	320000	480044	4734671	0	0	0	106717	107044	106830	26675	3	26718	400010	20	320000	20	400000	106731	106727	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320041	0	0	0	48	320042	6	1	42	45	0	0	0	0	5033	8	16	0	8	9	106735	80000	10	10	320000	80010	106732	106732	106732	106732	106732
320024	106731	828	0	0	0	0	0	0	0	0	4	48	0	0	0	1	106867	3	4	4	21	51	400010	80010	320000	80010	320000	480043	4734671	0	0	0	106702	107043	106843	26675	3	26710	400010	20	320000	20	400000	106734	106762	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	0	42	320042	6	1	42	45	0	0	0	0	5020	8	16	0	5	8	106729	80000	14	10	320000	80010	106732	106732	106881	106732	106736
320024	106731	827	0	0	0	1	0	0	0	0	0	48	0	0	0	2	106712	3	4	4	21	25	400010	80010	320000	80010	320000	480044	4693019	0	0	0	106706	106921	106976	26682	3	26714	400010	20	320000	20	400000	106731	106731	1	1	80021	10	9	5	10	10	80000	80000	0	10	325202	2	45	0	320042	0	0	0	45	320042	6	1	42	45	0	0	0	0	5020	5	16	0	8	7	106733	80000	15	10	320000	80010	106732	106732	106734	106739	106728
320024	106735	857	0	0	0	0	0	0	0	0	0	48	0	0	0	1	106716	3	4	4	21	25	400010	80010	320000	80010	320000	480044	4734671	0	0	0	106702	106990	107116	26682	3	26710	400010	20	320000	20	400000	106881	106731	1	1	80021	10	9	1	10	10	80000	80000	0	10	320000	0	45	0	320042	0	1	0	42	320042	6	1	39	45	0	0	0	0	5020	8	16	0	5	8	106728	80000	18	14	320000	80010	106732	106732	106737	106732	106740
320024	106731	857	0	0	0	0	0	0	0	0	0	48	0	0	0	2	106720	3	4	15	21	25	400010	80010	320000	80010	320000	480044	4734671	0	0	0	106710	106941	106950	26682	3	26725	400010	20	320000	20	400000	106731	106731	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	0	39	320000	6	1	42	45	0	0	0	0	5032	8	16	0	9	5	106729	80000	14	10	320000	80010	106736	106732	106732	106735	106735
320024	106735	857	0	0	0	0	0	0	0	0	1	48	0	0	0	2	106716	3	4	1	21	25	400010	80010	320000	80010	320000	480044	4734671	0	0	0	106709	107073	106926	26679	3	26837	400010	20	320000	20	400000	106727	106727	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	0	790	320042	6	1	42	0	0	0	0	0	5020	9	16	0	8	10	106728	80000	14	10	320000	80010	106732	106736	106880	106732	106732

LD1 (multiple, post-index, 4 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations