Firestorm: LD1 (multiple, post-index, 4 regs, 2S) measurements

Code:

  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0f	18	19	1e	1f	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29771	239	1	22	1	1	18	0	0	0	0	17	0	0	4697	29199	0	0	0	24420	3000	1000	2000	1000	2000	5000	10000	0	16277	28962	29624	3	10	3000	4000	4000	29373	29497	1	1	61001	1000	1000	0	2004	4	4	2006	0	0	1	4	2000	4	0	2	4	2	1	0	13290	9540	6963	3152	8	43	20559	3318	3821	16	48	43	28749	1000	16295	13689	15297	2000	2000	1000	29590	29660	29601	29664	29708
64004	29682	238	1	18	1	0	23	1	0	0	0	23	0	0	4635	28807	0	2	0	23790	3000	1001	2000	1000	2002	5000	10003	7	16312	28632	29059	13	28	3000	4004	4000	29005	28963	2	1	61001	1000	1000	1	2006	2	4	2006	0	0	0	872	2002	4	0	2	8	2	2	0	13191	9422	6965	3147	5	51	19996	3222	3816	19	52	44	28383	1000	16075	13058	14522	2000	2000	1000	29067	29044	29002	29031	29049
64004	29205	233	1	21	2	2	16	0	0	1	2	142	88	0	4631	28744	0	0	2	23854	3000	1001	2002	1001	2002	5000	10084	7	16322	28489	29236	13	72	3000	4004	4004	28994	28990	4	1	61001	1000	1000	0	2005	0	0	2002	0	0	0	2	2002	4	0	4	0	2	0	1998	13010	9223	6837	3136	4	50	20225	3218	3814	14	46	39	28917	1000	15875	13217	14759	2000	2000	1000	28946	28845	28838	28934	28765
64004	28861	232	1	18	1	1	11	1	0	1	0	8	0	0	4728	28509	0	0	0	23554	3000	1000	2000	1000	2000	5000	10000	2	16277	28268	28803	3	10	3000	4000	4000	28660	28698	1	1	61001	1000	1000	0	2003	2	6	2003	0	2	0	5	2000	6	0	4	6	2	0	0	13197	9337	6850	3133	8	45	19914	3223	3814	13	46	42	28267	1000	15910	12975	14555	2000	2000	1000	28986	28968	28813	28866	28849
64004	28943	233	0	15	0	0	19	0	0	0	0	4	0	0	4778	28590	0	2	0	23833	3000	1000	2000	1000	2000	5000	10000	4	16250	28236	28650	3	10	3000	4000	4000	28639	28706	1	1	61001	1000	1000	0	2000	0	4	2002	2	0	0	10	2000	4	0	0	0	0	1	0	13475	9205	6921	3179	7	43	19853	3343	3821	16	47	43	28407	1000	15536	13275	14631	2000	2000	1000	28717	28786	28747	28801	28833
64004	28921	232	1	18	0	0	19	1	0	0	0	36	88	0	4627	28334	0	1	0	23618	3000	1000	2000	1000	2000	5000	10000	11	16244	28393	28992	3	10	3000	4000	4004	28675	28701	1	1	61001	1000	1000	0	2006	0	0	2018	0	0	0	7202	2025	6	0	2	6	0	0	0	13134	9140	6742	2963	7	46	20202	3139	3814	48	52	53	29062	1011	15903	13225	14476	2000	2000	1000	29345	29414	29455	29709	29629
64004	29413	237	0	15	1	1	22	0	0	0	0	8	0	0	4620	28367	0	0	0	23601	3003	1000	2000	1000	2000	5000	10000	4	16247	28457	28749	3	10	3000	4000	4000	28624	28631	1	1	61001	1000	1000	0	2002	3	0	2003	0	0	1	4	2002	6	0	4	4	2	1	0	13130	9327	6937	3193	8	48	19725	3179	3811	14	39	42	28199	1000	15431	12601	14159	2000	2000	1000	28758	28838	28747	28722	28802
64004	28776	223	1	13	0	1	14	1	0	0	0	2	0	0	4626	28450	0	1	2	23719	3000	1000	2000	1000	2000	5000	10000	13	16240	28308	28764	3	10	3000	4000	4000	28622	28588	1	1	61001	1000	1000	0	2002	3	6	2009	0	0	1	8	2002	6	0	2	8	2	1	0	13068	9361	6930	3087	6	41	19781	3221	3814	16	40	41	28246	1000	15633	12868	14238	2000	2000	1000	28763	28717	28835	28694	28664
64004	28629	223	1	20	0	0	17	1	0	0	0	2	0	0	4747	28441	0	0	0	23632	3000	1000	2000	1000	2000	5005	10003	6	16235	28282	28766	9	10	3000	4000	4000	28765	28721	1	1	61001	1000	1000	1	2002	2	0	2004	0	0	2	387	2005	6	0	4	6	2	1	0	13210	9467	6860	3204	9	41	19657	3185	3802	18	39	49	28084	1000	15552	13051	14298	2000	2000	1000	28764	28710	28797	28730	28759
64004	28800	223	1	19	0	2	18	0	0	0	0	179	0	0	4589	28396	0	0	2	23506	3000	1000	2000	1000	2000	5000	10000	13	16244	28378	28839	3	10	3000	4000	4000	28700	28621	1	1	61001	1000	1000	0	2004	3	4	2002	0	1	1	8	2000	4	0	2	8	2	0	0	13325	9452	6879	3086	12	41	19726	3161	3809	16	42	47	28241	1000	15617	12915	14509	2000	2000	1000	28763	28747	28784	28825	28814

Count: 8

Code:

  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80069	621	1	1	0	0	0	0	0	0	0	0	55	0	0	4	80026	2	6	6	3	25	240100	80100	160000	80100	160000	480499	961330	1	0	80016	80041	80041	0	3	23	240217	200	320000	200	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160011	11	0	160050	0	142	0	50	160039	6	1	49	43	11	0	0	5109	2	17	2	2	80038	80000	13	13	160000	160000	80100	80042	80042	80042	80042	80042
320204	80041	621	1	1	1	1	0	1	0	0	0	0	68	0	0	2	80026	1	7	7	3	25	240100	80100	160000	80100	160000	480499	961279	1	0	80093	80042	80041	0	3	23	240100	200	320000	200	320000	80132	80042	1	1	80201	100	99	100	100	80000	80000	0	100	160011	11	43	160051	0	95	1	50	160039	6	1	50	43	10	0	0	5111	2	17	1	2	80038	80000	13	13	160000	160000	80100	80042	80042	80042	80042	80042
320204	80041	620	1	0	0	1	0	1	0	0	0	0	56	0	0	1	80026	2	6	6	6	25	240100	80100	160000	80100	160000	480499	964122	1	0	80079	80041	80041	0	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160086	11	43	160051	0	110	0	51	160039	6	1	50	43	10	1	0	5111	2	17	1	2	80038	80039	13	13	160000	160000	80100	80043	80042	80042	80042	80044
320204	80041	620	1	1	0	0	1	0	0	0	0	1	55	0	0	2	80026	2	7	7	3	25	240100	80100	160000	80100	160000	480499	961273	1	0	80016	80041	80041	0	3	23	240217	200	320000	200	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160012	11	43	160049	1	145	0	49	160039	6	1	50	43	11	1	0	5109	1	17	2	2	80038	80000	13	13	160000	160000	80100	80042	80042	80042	80042	80042
320204	80041	620	1	1	0	0	1	0	0	0	0	0	56	0	0	2	80026	2	6	7	3	25	240100	80100	160000	80100	160000	480499	961273	1	0	80016	80041	80041	0	3	23	240100	200	320000	200	320000	80041	80132	1	1	80201	100	99	100	100	80000	80000	0	100	160012	11	43	160051	0	81	0	50	160039	6	1	50	43	10	0	0	5111	2	17	1	2	80038	80000	13	13	160000	160000	80100	80042	80042	80042	80042	80090
320204	80041	620	1	1	0	0	1	0	0	0	0	0	56	0	0	2	80026	2	6	6	3	25	240100	80100	160000	80100	160000	480499	961310	1	0	80016	80041	80041	0	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160011	11	43	160049	0	128	0	49	160039	6	1	50	43	11	0	0	5109	1	17	2	2	80038	80039	13	13	160000	160000	80100	80044	80042	80042	80042	80042
320204	80041	621	1	0	1	1	0	1	0	0	1	0	68	0	0	3	80026	2	6	6	3	25	240100	80100	160000	80100	160000	480499	961315	1	0	80016	80041	80041	0	3	67	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160011	11	43	160123	0	51	0	52	160039	6	1	49	43	11	0	0	5109	1	17	2	1	80038	80000	13	13	160000	160000	80100	80042	80042	80042	80042	80042
320204	80041	621	1	1	0	0	1	0	0	0	0	0	67	0	0	3	80026	2	7	7	3	25	240100	80100	160000	80100	160000	480499	961305	1	0	80016	80041	80041	0	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160012	11	43	160048	0	85	1	54	160039	6	1	50	43	10	0	0	5109	2	17	1	2	80038	80000	13	13	160000	160000	80100	80126	80042	80042	80042	80042
320204	80041	620	1	1	1	0	0	1	0	0	0	0	68	0	0	3	80026	2	6	6	30	25	240100	80100	160000	80100	160000	480499	961289	1	0	80016	80041	80041	0	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160012	10	43	160051	0	84	1	53	160039	6	1	50	43	10	0	0	5111	2	17	1	2	80038	80000	13	13	160000	160000	80100	80133	80042	80042	80042	80042
320204	80041	621	1	1	0	1	1	1	0	0	0	0	55	0	0	2	80026	3	7	7	3	25	240100	80100	160000	80100	160092	480499	964112	1	0	80016	80132	80041	23	9	23	240217	200	320156	200	320156	80130	80041	1	1	80201	100	99	100	100	80000	80000	0	100	160084	14	43	160194	0	82	0	595	160039	6	1	50	43	11	0	0	5134	2	25	2	2	80116	80039	13	13	160000	160000	80100	80225	80134	80132	80226	80131

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80055	642	1	0	0	0	0	0	1	0	0	53	0	0	2	80026	3	14	14	0	25	240010	80010	160000	80010	160000	480049	960364	0	80016	0	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160010	11	40	160123	0	49	1	48	160036	6	1	47	40	0	0	5019	2	17	3	3	80038	80000	10	9	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	642	1	0	1	0	0	0	0	0	0	52	0	0	3	80026	2	14	12	0	25	240010	80010	160000	80010	160000	480049	960874	0	80016	0	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160011	11	40	160049	0	9	0	14	160037	0	1	21	43	11	0	5019	3	17	2	2	80038	80000	0	8	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	643	1	0	1	0	0	0	0	0	0	53	0	0	1	80026	1	14	14	0	25	240010	80010	160000	80010	160000	480049	960043	0	80016	0	80041	80041	0	3	23	240010	20	320156	20	320000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160011	11	0	160047	0	52	1	0	160037	6	0	48	40	11	1	5019	2	17	2	2	80038	80000	0	0	160000	160000	80010	80042	80042	80042	80042	80043
320024	80041	643	1	0	0	0	0	0	0	0	0	56	0	0	2	80026	2	15	14	0	25	240010	80010	160000	80010	160000	480049	960885	0	80016	3	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160013	10	40	160048	0	86	0	46	160036	6	1	22	40	11	1	5019	3	17	3	3	80038	80000	9	6	160000	160000	80010	80042	80042	80042	80042	80048
320024	80041	643	1	0	0	0	1	0	0	0	0	12	0	0	3	80026	0	14	0	0	25	240010	80010	160000	80010	160000	480049	960026	0	80016	0	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160011	12	40	160046	0	36	1	25	160000	6	1	46	0	10	1	5019	2	17	2	2	80038	80000	9	9	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	643	1	0	0	0	1	0	1	0	0	99	0	0	0	80026	3	0	14	0	25	240010	80010	160000	80010	160000	480049	960946	0	80093	0	80131	80041	0	3	23	240010	20	320000	20	320000	80132	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160012	10	40	160048	0	79	0	48	160102	0	1	49	37	11	0	5019	2	25	2	2	80116	80000	9	0	160000	160000	80010	80042	80042	80042	80133	80062
320024	80041	643	1	0	0	0	0	0	0	1	0	55	0	0	1	80116	0	14	14	27	48	240010	80049	160000	80010	160000	480049	960331	0	80016	0	80041	80131	0	3	66	240010	20	320156	20	320000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160085	10	40	160048	0	47	1	596	160036	6	1	48	43	10	0	5019	2	26	2	2	80038	80039	0	0	160000	160000	80010	80132	80132	80042	80132	80046
320024	80041	643	1	0	0	0	0	0	0	1	0	10	0	0	2	80116	0	13	14	0	25	240244	80010	160156	80051	160000	480049	962856	0	80170	0	80221	80041	0	8	23	240127	20	320000	20	320156	80041	80041	2	1	80021	10	9	0	10	10	80000	80000	0	10	160011	11	40	160050	0	56	1	586	160036	6	1	22	0	10	0	5031	2	17	2	3	80116	80000	9	7	160000	160000	80010	80042	80042	80222	80042	80042
320024	80135	642	1	0	0	0	0	0	0	0	1	78	88	0	2	80116	2	0	12	27	47	240244	80010	160156	80010	160156	480049	963725	0	80093	0	80041	80130	0	7	23	240010	20	320156	20	320156	80131	80224	2	1	80021	10	9	0	10	10	80000	80000	0	10	160086	11	40	160262	0	9	0	1090	160108	6	1	48	40	11	0	5031	2	34	3	3	80194	80078	9	9	160000	160000	80010	80131	80221	80225	80131	80132
320024	80131	645	1	0	1	0	0	0	0	0	0	55	0	0	0	80026	2	14	14	0	25	240010	80010	160000	80010	160000	480049	960330	0	80016	0	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	0	10	10	80000	80000	0	10	160010	12	40	160050	0	27	0	46	160036	6	1	49	40	11	1	5019	3	17	4	3	80038	80000	10	9	160000	160000	80010	80042	80042	80042	80042	80060

LD1 (multiple, post-index, 4 regs, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations