Firestorm: LD1 (multiple, post-index, 4 regs, 4H) measurements

Code:

  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
64005	28340	212	1	26	0	3	24	0	0	0	7	0	0	5046	27875	0	0	1	23287	3000	1000	2000	1000	2000	5000	10001	18	16214	0	27909	28247	3	10	3000	4000	4000	27989	28031	1	1	61001	1000	1000	2000	0	4	2005	0	1	0	2	2000	4	0	8	4	0	0	14178	10306	7250	3414	10	61	19217	3384	3807	17	58	57	27904	1000	14031	12097	13008	2000	2000	1000	28341	28184	28123	28390	28003
64004	28283	211	0	24	0	0	23	0	0	0	2	0	0	5069	28165	0	1	0	23130	3000	1000	2000	1000	2000	5000	10003	13	16203	0	27887	28132	3	10	3000	4000	4000	28164	28164	1	1	61001	1000	1000	2000	0	4	2002	0	0	0	5	2000	4	0	2	6	0	0	14164	10324	7231	3458	10	57	19173	3394	3812	17	60	61	27865	1000	14424	12102	13117	2000	2000	1000	28311	28311	28203	28526	28228
64004	28287	212	0	26	0	0	20	0	0	0	7	0	0	5220	28084	0	1	0	23102	3000	1000	2000	1001	2000	5000	10003	15	16239	3	28110	28345	3	10	3000	4000	4000	28201	28210	1	1	61001	1000	1000	2000	0	4	2002	0	2	0	2	2002	4	0	0	6	0	0	13802	10193	7207	3429	9	61	19212	3396	3815	7	61	60	28058	1000	14528	12307	13080	2000	2000	1000	28199	28283	28245	28557	28325
64004	28336	211	0	24	0	0	23	0	0	0	12	0	0	5087	28001	0	0	2	22996	3000	1000	2000	1000	2000	5000	10000	14	16246	0	27951	28263	3	10	3000	4000	4000	28110	28232	1	1	61001	1000	1000	2003	3	4	2002	0	0	0	5	2000	0	0	2	4	2	0	13986	10298	7274	3456	9	60	19201	3377	3815	10	54	55	27929	1000	13971	12049	13054	2000	2000	1000	28393	28482	28249	28396	28262
64004	28270	211	0	25	0	0	21	0	0	0	57	0	0	5257	27934	0	1	2	23143	3000	1000	2000	1000	2000	5000	10001	11	16232	0	27861	28239	3	10	3000	4000	4000	28098	28037	1	1	61001	1000	1000	2000	3	6	2005	0	2	1	2	2000	4	0	2	6	2	1	13956	10213	7162	3303	8	61	19331	3434	3814	10	59	62	27893	1000	14243	12207	13127	2000	2000	1000	28306	28301	28181	28629	28288
64004	28209	212	0	22	0	0	25	1	0	0	2	1	0	5179	27909	2	0	0	23097	3000	1000	2000	1000	2000	5000	10003	13	16247	0	27948	28301	3	10	3000	4000	4000	28334	28049	1	1	61001	1000	1000	2000	0	4	2002	0	1	0	0	2000	4	0	4	4	0	0	13738	10266	7088	3425	9	54	19250	3334	3813	9	58	62	28060	1000	14613	12191	13277	2000	2000	1000	28296	28365	28255	28541	28344
64004	28321	212	0	27	0	0	23	0	0	0	12	0	0	5209	28054	0	0	1	23141	3000	1000	2000	1000	2000	5000	10002	14	16243	0	27872	28310	3	10	3000	4000	4000	28238	28247	1	1	61001	1000	1000	2000	0	6	2000	0	4	0	2	2002	4	0	4	4	0	0	14015	10260	7207	3385	10	57	19359	3381	3813	14	52	58	27933	1000	14693	12186	13305	2000	2000	1000	28118	28242	28280	28339	28261
64004	28304	211	1	21	0	0	21	0	0	0	5	0	0	5155	27973	2	0	1	23157	3000	1000	2000	1000	2000	5000	10012	1	16270	0	28152	28286	3	10	3000	4000	4000	28191	28192	1	1	61001	1000	1000	2000	0	4	2000	0	2	0	4	2000	2	0	4	2	0	0	13803	10009	7259	3429	12	55	19511	3410	3822	20	55	57	27890	1000	14431	12438	13057	2000	2000	1000	28438	28208	28205	28468	28328
64004	28290	211	1	20	0	0	23	0	0	0	4	0	0	5108	28114	0	0	1	22948	3000	1000	2000	1000	2000	5000	10000	9	16245	0	28032	28372	3	10	3000	4000	4000	28410	28159	1	1	61001	1000	1000	2000	0	4	2005	0	45	0	2	2000	4	0	4	4	0	0	13563	10175	7257	3436	13	51	19264	3313	3812	11	55	63	27973	1000	14326	12200	13399	2000	2000	1000	28297	28221	28206	28352	28322
64004	28352	212	0	20	0	0	22	0	0	0	5	0	0	5020	27990	0	0	1	23142	3000	1000	2000	1000	2000	5000	10003	14	16269	0	28109	28196	3	10	3000	4000	4000	28148	28371	1	1	61001	1000	1000	2000	2	4	2003	0	17	0	3	2000	4	1	4	4	0	0	14267	9980	7210	3374	12	61	19317	3387	3810	17	60	57	27938	1000	14776	12227	13378	2000	2000	1000	28160	28290	28347	28303	28343

Count: 8

Code:

  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8
  ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320205	80069	643	0	1	0	0	1	0	0	0	0	0	54	0	0	1	80026	11	8	0	0	25	240100	80139	160000	80100	160000	480499	961168	1	0	0	80016	80041	80041	0	3	29	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	58	160047	0	0	48	160014	6	1	47	45	0	0	0	0	5111	5	4	1	17	2	2	80038	0	80000	10	10	160000	160000	80100	80042	80042	80042	80047	80042
320204	80041	643	0	0	0	0	0	0	0	0	0	0	53	0	0	2	80026	10	9	16	7	25	240100	80100	160000	80100	160000	480499	961276	1	5	0	80016	80041	80041	0	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	58	160047	1	0	67	160024	6	1	34	44	11	1	0	0	5111	5	4	2	16	2	1	80045	0	80000	10	10	160000	160000	80100	80042	80047	80049	80047	80049
320204	80041	643	1	0	1	0	0	0	0	0	0	0	83	0	0	1	80026	24	4	18	35	73	240217	80180	160000	80181	160078	480730	971748	1	5	2	80170	80223	80137	51	7	72	240217	200	320312	200	320468	80136	80136	3	1	80201	100	99	1	100	100	80000	80000	0	100	160226	14	57	160284	0	3	1150	160198	6	1	65	44	10	0	0	0	5159	5	4	1	35	2	2	80199	0	80039	10	10	160000	160000	80100	80138	80227	80227	80133	80494
320204	81670	654	0	0	1	1	1	1	0	0	2	3	329	264	0	2	80208	10	9	17	83	48	240807	80217	160156	80178	160156	480731	966523	1	5	0	80170	80219	80132	23	20	302	240217	200	320312	200	320000	80041	80132	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	57	160047	0	0	48	160120	6	1	47	43	0	0	0	0	5109	0	0	1	17	2	1	80038	0	80000	10	0	160000	160000	80100	80042	80042	80042	80048	80042
320204	80041	643	0	0	0	0	1	0	1	0	0	0	53	88	0	1	80026	10	8	17	2	25	240100	80100	160000	80100	160078	480499	961442	1	5	0	80016	80041	80041	0	3	23	240100	200	320000	200	320000	80135	80041	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	57	160047	0	0	597	160047	6	1	48	43	0	0	0	0	5123	5	3	2	17	2	2	80038	0	80000	10	10	160000	160000	80100	80042	80133	80042	80047	80134
320204	80131	643	0	1	0	0	1	0	0	0	0	1	65	0	0	2	80026	10	0	0	2	25	240100	80100	160000	80100	160000	480499	961190	0	5	0	80016	80041	80041	0	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	43	160047	2	0	50	160048	6	0	47	0	0	0	0	0	5111	5	3	2	17	2	2	80038	0	80000	10	0	160000	160000	80100	80042	80042	80042	80047	80042
320204	80042	643	0	0	0	0	1	0	0	0	0	0	53	0	0	1	80026	10	9	16	38	25	240100	80100	160000	80100	160000	480499	960204	1	5	0	80016	80041	80041	4	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	57	160180	1	1	70	160123	6	1	62	44	11	0	0	0	5111	5	4	1	16	2	2	80043	0	80000	10	10	160000	160000	80100	80047	80049	80047	80113	80047
320204	80046	642	1	0	1	0	1	0	0	0	0	0	83	0	0	2	80031	16	4	18	290	25	240100	80100	160000	80100	160000	480498	960277	1	0	0	80016	80108	80041	0	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	49	160045	3	0	47	160046	6	1	44	41	0	0	0	1	5111	0	0	2	17	1	2	80038	0	80000	6	6	160000	160000	80100	80042	80042	80042	80042	80042
320204	80041	643	0	1	0	0	0	0	0	0	0	0	65	0	0	1	80026	11	15	23	0	25	240100	80100	160000	80100	160000	480499	960705	0	0	0	80016	80041	80041	0	3	23	240100	200	320000	200	320000	80041	80041	1	1	80201	100	99	0	100	100	80000	80000	0	100	160000	0	49	160045	1	0	51	160045	6	1	46	41	0	0	0	0	5109	0	0	1	17	1	3	80038	0	80039	15	6	160000	160000	80100	80141	80140	80132	80243	80042
320204	80041	643	0	0	0	0	0	0	1	0	0	0	661	88	0	1	80026	11	14	22	0	25	240100	80100	160000	80100	160000	480499	960704	0	0	0	80016	80041	80041	0	3	23	240100	200	320000	200	320468	80041	80041	2	1	80201	100	99	0	100	100	80000	80000	0	100	160362	0	49	160405	1	0	3093	160329	6	1	45	41	0	2	0	0	5111	0	0	2	17	1	2	80038	0	80000	6	6	160000	160000	80100	80078	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
320025	80042	621	1	0	0	1	0	1	0	0	0	0	56	0	0	2	80026	2	6	6	3	25	240010	80010	160000	80010	160000	480049	961425	1	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160011	12	43	160051	0	1	1	49	160039	6	1	50	43	11	1	0	5019	8	17	19	19	80038	80000	13	13	160000	160000	80010	80045	80042	80042	80042	80042
320024	80041	621	1	0	0	0	0	0	0	0	0	0	58	0	0	2	80026	2	5	6	3	25	240010	80010	160000	80010	160000	480049	961279	0	0	80093	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160010	12	44	160050	0	31	0	53	160039	6	1	50	43	10	0	0	5019	17	17	18	9	80039	80000	14	13	160000	160000	80010	80042	80043	80044	80042	80042
320024	80041	630	1	0	0	0	0	1	2	1	0	0	66	0	0	2	80026	3	15	10	0	25	240010	80010	160000	80010	160000	480049	960914	0	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160012	10	40	160046	0	0	0	48	160037	6	1	50	40	11	1	0	5019	17	17	18	17	80038	80000	9	9	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	620	1	0	1	1	0	0	0	0	0	0	52	0	0	2	80026	2	14	13	0	25	240010	80010	160000	80010	160000	480049	960019	0	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160011	11	40	160048	0	1	1	47	160036	6	1	48	0	10	0	0	5019	19	17	10	19	80038	80000	9	9	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	620	1	0	0	1	0	0	0	0	0	0	54	0	0	2	80026	3	15	14	0	25	240010	80010	160000	80010	160000	480049	960946	0	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160011	12	40	160049	0	0	1	46	160036	0	1	47	40	11	0	0	5019	19	17	19	19	80038	80000	9	9	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	620	1	0	1	0	0	0	0	0	0	0	54	0	0	2	80026	2	15	15	0	25	240010	80010	160000	80010	160000	480049	961004	0	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	1	10	160011	11	0	160047	0	0	0	47	160036	6	1	47	40	10	0	0	5019	17	17	18	17	80038	80000	9	9	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	621	1	0	1	0	0	0	0	0	0	0	165	0	0	2	80026	2	14	14	0	25	240010	80010	160000	80010	160000	480049	960884	0	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160011	10	40	160010	0	1	0	47	160037	0	0	46	40	10	0	0	5019	18	17	15	18	80038	80000	10	9	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	621	1	0	0	1	0	0	0	0	0	0	55	0	0	2	80026	3	14	0	0	25	240010	80010	160000	80010	160000	480049	960884	0	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160012	11	40	160049	0	1	0	47	160037	6	0	46	40	11	0	0	5019	9	17	18	18	80038	80000	0	9	160000	160000	80010	80042	80042	80042	80042	80222
320024	80041	621	1	0	1	0	0	0	0	0	0	0	52	0	0	2	80026	2	14	0	0	25	240010	80010	160000	80010	160000	480049	960874	0	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160011	13	40	160048	0	1	1	46	160037	6	1	48	40	11	1	0	5019	18	17	10	17	80038	80000	0	9	160000	160000	80010	80042	80042	80042	80042	80042
320024	80041	620	1	0	0	0	0	0	0	0	0	0	52	0	0	2	80026	2	14	15	0	25	240010	80010	160000	80010	160000	480049	960874	1	0	80016	80041	80041	0	3	23	240010	20	320000	20	320000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	160012	12	40	160048	0	0	0	46	160036	6	1	47	40	11	0	0	5019	9	17	14	18	80038	80000	9	12	160000	160000	80010	80042	80042	80042	80042	80042

LD1 (multiple, post-index, 4 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations