Firestorm: LD1 (multiple, post-index, 4 regs, 4S) measurements

Code:

  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	ce	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
64005	29470	237	2	2	2	0	0	0	0	0	132	4718	29218	0	0	4	22905	5000	1000	4000	1001	4000	5000	20704	1	16935	28481	28817	3	10	5000	4004	5000	28845	28882	1	1	61001	1000	1000	1	4000	11	4006	0	0	4003	5	1	4	8	1	0	0	13310	9477	7121	3265	2	39	19727	3180	3817	17	41	39	28151	1000	15162	12450	13661	4000	1000	28760	28650	28602	28618	28670
64004	28760	222	0	0	1	0	1	0	0	0	9	4817	28473	0	0	4	22671	5000	1000	4000	1000	4000	5000	20719	5	16955	28362	28741	3	10	5000	4000	5000	28520	28639	1	1	61001	1000	1000	0	4000	8	4000	0	2	4002	6	1	4	8	0	0	0	13170	9499	6982	3175	1	34	19798	3170	3824	19	43	43	28231	1000	15518	12425	13902	4000	1000	28698	28694	28730	28742	28709
64004	28697	222	0	1	0	0	0	1	0	0	0	4719	28624	2	0	0	22821	5000	1000	4000	1000	4000	5005	20700	4	16949	28255	28733	3	10	5000	4000	5000	28540	28549	1	1	61001	1000	1000	0	4000	8	4000	0	0	4000	5	1	0	0	0	0	0	13151	9356	6956	3206	0	45	19715	3214	3822	15	40	43	28260	1000	15589	12397	13715	4000	1000	28682	28714	28803	28826	28779
64004	28746	223	0	0	1	1	0	0	0	0	8	4803	28645	0	0	0	22671	5000	1000	4000	1000	4000	5000	20709	5	16949	28339	28708	3	10	5000	4000	5000	29027	28967	1	1	61001	1000	1000	1	4000	0	4007	0	0	4002	6	1	6	4	0	0	14	13927	10246	7023	3165	0	50	19689	3317	3835	18	41	46	28366	1000	15453	12561	13945	4000	1000	28911	28922	28797	28893	28782
64004	28847	223	0	0	0	0	0	0	0	0	8	4683	28696	2	4	0	22575	5000	1000	4000	1000	4000	5000	20723	5	16957	28067	28439	3	10	5000	4000	5000	28445	28510	1	1	61001	1000	1000	0	4000	8	4000	0	0	4003	0	1	0	0	0	0	0	13299	9640	7139	3426	0	41	19648	3186	3829	16	35	35	28209	1000	15514	12000	13229	4000	1000	28504	28577	28566	28447	28400
64004	28607	220	2	0	1	0	0	0	0	0	0	4746	28387	2	0	4	22599	5000	1000	4000	1000	4000	5000	20714	6	16981	28256	28855	3	10	5000	4000	5000	28461	28599	1	1	61001	1000	1000	0	4000	8	4006	0	2	4000	6	1	0	0	0	0	0	13280	9383	7017	3174	1	39	19621	3219	3828	21	36	41	28103	1000	15100	12106	13154	4000	1000	28543	28421	28738	28700	28623
64004	28340	222	0	0	0	0	0	0	0	0	0	4953	28585	0	0	0	22502	5000	1000	4000	1000	4000	5000	20722	4	16945	28387	28775	3	10	5000	4000	5000	28600	28494	1	1	61001	1000	1000	1	4000	8	4000	0	0	4000	0	1	6	0	0	0	0	13374	9933	7126	3175	0	41	19795	3325	3825	17	41	39	28032	1000	14718	12149	13129	4000	1000	28447	28611	28723	28553	28570
64004	28697	221	0	1	0	0	0	0	0	0	13	4885	28399	0	0	0	22486	5000	1000	4000	1000	4000	5000	20713	6	16968	28264	28629	3	10	5000	4000	5000	28446	28582	1	1	61001	1000	1000	0	4000	8	4006	0	0	4000	0	1	4	0	0	0	0	13138	9341	6981	3094	0	36	19683	3139	3820	12	39	39	28190	1000	15512	12411	13668	4000	1000	28678	28668	28746	28602	28624
64004	28650	222	1	0	0	0	0	0	1	0	8	4886	28656	0	0	0	22709	5000	1000	4000	1000	4000	5000	20716	4	16934	28393	28766	3	10	5000	4000	5000	28673	28527	1	1	61001	1000	1000	1	4000	0	4000	0	3	4003	0	1	4	0	0	0	0	13158	9287	6958	3105	0	36	20145	3150	3829	13	44	36	28428	1000	15284	12522	13679	4000	1000	28626	28710	28651	28712	28689
64004	28599	220	0	1	1	0	0	0	0	1	897	4729	28709	0	4	0	22951	5000	1000	4000	1000	4000	5000	20706	2	16933	28690	29040	3	10	5000	4000	5000	28065	28334	1	1	61001	1000	1000	1	4000	8	4002	0	3	4007	0	1	4	8	0	0	0	13801	10295	7209	3382	0	37	19652	3436	3827	12	38	41	27944	1000	14676	12278	13375	4000	1000	28333	28291	28402	28511	28318

Count: 8

Code:

  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	61	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	106731	827	0	0	0	0	0	0	180	0	0	0	2	106714	3	1	4	21	25	400100	80100	320000	80100	320000	480494	4734866	0	0	0	106706	106715	106708	26679	3	26718	400100	200	320192	200	400000	106731	106727	1	1	80201	100	99	5	100	100	80000	80000	0	100	320000	0	45	0	320042	0	0	42	320042	6	1	41	45	0	0	0	0	5110	0	0	1	16	1	1	106728	80001	10	10	0	320000	80100	106736	106736	106756	106732	106728
320204	106735	827	0	0	0	0	0	0	48	0	0	0	1	106997	3	4	4	21	25	400100	80100	320000	80100	320000	480494	4734767	0	0	0	106687	106731	106735	26656	3	26714	400100	200	320000	200	400000	106731	106731	1	1	80201	100	99	5	100	100	80000	80000	0	100	320000	0	45	0	320042	0	0	42	320042	6	1	42	45	0	0	0	0	5110	0	0	1	17	1	1	106724	80003	14	14	0	320000	80100	106709	106732	106880	106728	106732
320204	106731	827	0	0	0	0	0	0	60	0	0	0	1	106875	0	4	4	23	25	400100	80100	320000	80147	320000	480494	4732183	0	0	0	106816	106731	106731	26687	3	26710	400100	200	320000	200	400000	106735	106727	1	1	80201	100	99	5	100	100	80000	80000	0	100	320132	0	58	0	320053	0	0	54	320054	6	1	55	44	0	0	0	0	5110	0	0	1	17	1	1	106736	80053	14	14	0	320000	80100	106732	106734	106732	106733	106713
320204	106727	827	0	0	0	0	0	0	48	0	0	0	2	106847	3	4	1	0	25	400100	80100	320000	80100	320000	480775	4734671	0	0	0	106706	106708	106735	26679	3	26714	400100	200	320192	200	400000	106731	106727	1	1	80201	100	99	5	100	100	80000	80000	0	100	320522	0	45	0	320042	2	0	0	320042	0	1	42	45	0	0	0	0	5110	5	4	1	16	1	1	106732	80001	0	14	0	320000	80100	106736	106728	106728	106728	106884
320204	106731	827	0	0	1	1	0	0	48	0	1	0	1	106869	3	4	4	21	25	400100	80100	320000	80100	320000	480495	4665926	0	0	0	106710	106731	106735	26679	3	26714	400100	200	320000	200	400000	106731	106731	1	1	80201	100	99	5	100	100	80000	80000	0	100	320000	0	45	0	320039	0	0	39	320042	6	1	0	45	0	0	0	0	5110	0	0	1	16	1	1	106728	80003	14	10	0	320000	80100	106732	106740	106732	106740	106732
320204	106708	827	0	0	0	0	0	0	48	0	0	0	2	107034	3	0	15	23	25	400100	80100	320000	80100	320000	480494	4655251	0	0	0	106706	106735	106735	26679	3	26714	400100	200	320000	200	400000	106727	106737	1	1	80201	100	99	5	100	100	80000	80000	0	100	320000	0	45	0	320042	1	0	42	320042	6	1	41	45	0	0	0	0	5110	0	0	1	16	1	1	106732	80011	14	14	0	320000	80100	106732	106732	106732	106728	106736
320204	106708	829	0	0	0	0	0	0	48	0	0	0	2	106995	3	4	4	21	25	400278	80147	320000	80194	320356	480494	4685321	0	0	7	106841	107030	107029	26868	11	27016	400550	200	320192	200	400480	107183	107034	3	1	80201	100	99	5	100	100	80000	80000	1	100	320130	2	45	33	320434	0	2	1617	320432	6	1	42	45	0	0	0	0	5147	0	0	1	34	1	1	106998	81103	10	10	1	320000	80100	106930	107036	106886	107188	107186
320204	107185	829	1	0	0	0	1	2	325	176	0	0	1	107170	2	4	4	2	25	400100	80100	320000	80100	320000	480494	4734671	0	0	0	106706	106735	106708	26679	3	26714	400100	200	320000	200	400000	106735	106727	1	1	80201	100	99	5	100	100	80000	80000	0	100	320000	0	45	0	320042	0	0	42	320041	6	1	42	45	0	0	0	0	5110	0	0	1	16	1	1	106734	80004	10	14	0	320000	80100	106732	106712	106736	106732	106713
320204	106731	827	0	0	0	0	0	0	57	0	0	0	2	106869	0	4	4	21	25	400100	80100	320130	80100	320000	480494	4734479	0	0	0	106706	106731	106727	26659	3	26714	400100	200	320000	200	400000	106731	106727	1	1	80201	100	99	6	100	100	80000	80000	0	100	320000	0	45	0	320042	0	0	42	320042	6	1	38	45	0	0	0	0	5110	0	0	1	16	1	1	106732	80004	0	15	0	320000	80100	106732	106737	106732	106728	106713
320204	106731	827	0	0	0	0	0	0	48	0	0	0	2	106848	3	4	4	23	25	400100	80100	320000	80100	320000	480494	4734479	0	0	0	106706	106731	106735	26679	3	26714	400100	200	320000	200	400000	106731	106727	1	1	80201	100	99	0	100	100	80000	80000	0	100	320000	0	0	0	320042	0	0	42	320042	6	1	42	45	0	0	0	0	5110	0	0	1	16	1	1	106728	80003	10	10	0	320000	80100	106737	106732	106732	106732	106732

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	106732	827	1	0	0	0	1	0	0	0	40	0	0	2	106717	2	18	0	17	25	400010	80010	320000	80010	320000	480047	4655056	0	106707	106732	106732	26675	3	26710	400010	20	320000	20	400000	106732	106732	1	1	80021	10	9	0	10	10	80000	80000	0	10	320000	18	0	0	320000	1	0	0	58	320000	6	1	18	44	18	1	0	5019	1	5	16	3	4	106729	80000	9	9	1	320000	80010	106733	106733	106733	106733	106733
320024	106732	828	1	0	1	0	0	0	0	0	65	0	0	2	106720	2	18	15	17	25	400010	80010	320000	80010	320000	480026	4708681	0	106707	106732	106732	26680	3	26715	400010	20	320000	20	400000	106732	106732	1	1	80021	10	9	0	10	10	80000	80000	0	10	320018	19	38	0	320058	1	1	1	58	320041	6	0	18	0	18	2	0	5020	0	3	16	3	3	106729	80000	0	9	1	320000	80010	106735	106733	106733	106715	106733
320024	106732	828	1	0	0	1	0	0	0	0	0	0	0	2	106717	2	0	18	1	25	400010	80010	320000	80010	320000	480046	4734479	0	106707	106713	106713	26676	3	26715	400010	20	320000	20	400000	106732	106713	1	1	80021	10	9	0	10	10	80000	80000	0	10	320000	19	44	0	320042	0	1	1	58	320000	6	1	58	0	18	1	1	5019	0	3	16	4	4	106711	80000	9	9	1	320000	80010	106733	106733	106715	106733	106733
320024	106732	827	1	0	0	1	0	0	0	0	65	0	0	2	106717	2	18	18	1	25	400010	80010	320000	80010	320000	480042	4680790	0	106710	106714	106714	26680	3	26697	400010	20	320000	20	400000	106732	106732	1	1	80021	10	9	0	10	10	80000	80000	0	10	320019	18	44	0	320058	0	0	0	59	320042	6	1	35	44	0	1	0	5020	0	7	16	3	3	106729	80000	0	10	1	320000	80010	106733	106733	106733	106739	106733
320024	106732	827	1	0	1	0	0	0	0	0	65	0	0	2	106699	2	15	18	16	25	400010	80010	320000	80010	320000	480047	4734479	0	106689	106732	106713	26681	3	26715	400010	20	320000	20	400000	106732	106732	1	1	80021	10	9	0	10	10	80000	80000	0	10	320000	19	44	0	320042	1	0	1	42	320041	6	1	58	44	18	1	0	5020	0	3	16	3	3	106729	80000	9	9	1	320000	80010	106733	106722	106733	106734	106737
320024	106736	827	1	0	0	0	0	0	0	0	65	0	0	2	106717	2	0	15	17	25	400010	80010	320000	80010	320000	480043	4706976	0	106702	106732	106732	26680	3	26715	400010	20	320000	20	400000	106737	106732	1	1	80021	10	9	4	10	10	80000	80000	0	10	320019	18	41	0	320058	0	0	0	2147	320000	6	1	58	44	18	1	0	5097	2	3	25	4	3	106737	80000	9	10	1	320000	80010	106741	106756	106728	106715	106737
325397	107454	857	1	1	1	0	1	1	0	0	65	0	0	2	106717	3	18	18	16	25	400010	80010	320000	80010	320000	480026	4662214	0	106707	106732	106732	26680	3	26715	400010	20	320000	20	400000	106732	106736	1	1	80021	10	9	1	10	10	80000	80000	0	10	320000	18	44	0	320058	1	0	0	18	320041	6	1	58	44	18	0	0	5020	0	3	16	3	3	106729	80000	0	9	1	320000	80010	106733	106728	106715	106733	106733
320024	106732	827	1	0	1	1	0	0	0	0	66	0	0	3	106724	3	18	18	21	25	400010	80058	320130	80010	320000	480324	4708681	0	107095	107544	106746	26704	25	26981	400010	20	320000	20	400000	106737	106740	1	1	80021	10	9	0	10	10	80000	80000	0	10	320019	18	38	0	320059	1	0	2	59	320040	0	0	18	44	18	2	0	5019	0	4	16	4	4	106729	80000	9	9	1	320000	80010	106715	106714	106733	106733	106733
320024	106732	800	1	0	0	1	0	0	0	0	48	0	1	0	106699	3	15	18	16	25	400010	80010	320000	80010	320000	480047	4734479	0	106695	106732	106732	26680	3	26715	400010	20	320000	20	400000	106732	106732	1	1	80021	10	9	0	10	10	80000	80000	0	10	320000	18	0	0	320000	0	0	0	0	320041	6	1	18	44	18	1	0	5019	0	4	17	4	3	106729	80000	9	9	1	320000	80010	106733	106715	106733	106733	106733
320024	106713	799	1	1	1	1	0	0	0	0	64	0	0	0	106765	2	18	0	17	25	400010	80010	320000	80010	320000	480041	4669265	0	106702	106730	106739	26684	3	26700	400010	20	320000	20	400000	106714	106732	1	1	80021	10	9	0	10	10	80000	80000	1	10	320018	18	38	0	320059	0	0	0	62	320039	6	1	56	0	0	1	1	5020	0	2	16	4	3	106729	80000	9	9	0	320000	80010	106733	106733	106728	106733	106728

LD1 (multiple, post-index, 4 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations