Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8 nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 3.000
Integer unit issues: 1.000
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 24 | 3a | 3f | 43 | 46 | 49 | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 5e | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | c9 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
64005 | 29010 | 233 | 25 | 0 | 0 | 20 | 0 | 1 | 0 | 0 | 0 | 28 | 0 | 0 | 4666 | 28477 | 0 | 0 | 2 | 23591 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10004 | 0 | 10 | 16219 | 28265 | 28936 | 8 | 10 | 3000 | 4000 | 4000 | 28781 | 28724 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 6 | 2000 | 0 | 2 | 0 | 2 | 2002 | 0 | 0 | 2 | 6 | 0 | 0 | 13139 | 9542 | 6960 | 3162 | 14 | 52 | 19646 | 3223 | 3812 | 22 | 52 | 52 | 28172 | 1000 | 15980 | 13043 | 14518 | 2000 | 2000 | 1000 | 28719 | 28762 | 28787 | 28866 | 28861 |
64004 | 28870 | 231 | 19 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 4805 | 28639 | 0 | 1 | 1 | 23636 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10000 | 0 | 5 | 16242 | 28363 | 28824 | 3 | 10 | 3000 | 4000 | 4000 | 28792 | 28878 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 4 | 2002 | 0 | 0 | 0 | 0 | 2002 | 4 | 0 | 2 | 4 | 0 | 0 | 13100 | 9581 | 6925 | 3198 | 8 | 55 | 19875 | 3161 | 3818 | 23 | 57 | 57 | 28253 | 1000 | 15748 | 13126 | 14518 | 2000 | 2000 | 1000 | 28930 | 28955 | 28961 | 28859 | 28864 |
64004 | 28804 | 231 | 23 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 4623 | 28594 | 0 | 0 | 0 | 23727 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10000 | 0 | 10 | 16220 | 28296 | 28781 | 3 | 10 | 3000 | 4000 | 4000 | 28681 | 28614 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 4 | 2002 | 0 | 1 | 0 | 0 | 2000 | 4 | 0 | 2 | 4 | 0 | 0 | 13011 | 9356 | 6891 | 3141 | 10 | 51 | 19818 | 3210 | 3821 | 12 | 53 | 53 | 28328 | 1000 | 15785 | 12997 | 14515 | 2000 | 2000 | 1000 | 28835 | 28783 | 28904 | 28856 | 28869 |
64004 | 28935 | 233 | 18 | 0 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 4682 | 28551 | 0 | 0 | 2 | 23752 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10003 | 0 | 10 | 16241 | 28441 | 28605 | 3 | 10 | 3000 | 4000 | 4000 | 28748 | 28753 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 4 | 2002 | 0 | 0 | 0 | 0 | 2002 | 0 | 0 | 0 | 4 | 0 | 0 | 13208 | 9304 | 6926 | 3102 | 10 | 53 | 19909 | 3215 | 3810 | 19 | 53 | 53 | 28233 | 1000 | 15858 | 12941 | 14419 | 2000 | 2000 | 1000 | 28794 | 28921 | 28824 | 28951 | 28812 |
64004 | 28847 | 231 | 25 | 0 | 0 | 20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4627 | 28527 | 0 | 0 | 0 | 23659 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10000 | 0 | 10 | 16233 | 28432 | 28959 | 3 | 10 | 3000 | 4000 | 4000 | 28777 | 28718 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 4 | 2000 | 0 | 0 | 0 | 0 | 2000 | 0 | 0 | 2 | 4 | 0 | 0 | 13204 | 9555 | 6977 | 3173 | 10 | 54 | 19899 | 3237 | 3828 | 20 | 50 | 52 | 28274 | 1000 | 15494 | 13135 | 14165 | 2000 | 2000 | 1000 | 28811 | 28853 | 28845 | 29013 | 28734 |
64004 | 28929 | 231 | 23 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 4688 | 28568 | 0 | 2 | 0 | 23621 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10000 | 0 | 9 | 16224 | 28411 | 28854 | 3 | 10 | 3000 | 4000 | 4000 | 28713 | 28743 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 6 | 2000 | 0 | 0 | 0 | 0 | 2000 | 4 | 0 | 0 | 6 | 0 | 0 | 13076 | 9353 | 6902 | 3192 | 11 | 54 | 19867 | 3389 | 3819 | 29 | 55 | 59 | 28290 | 1000 | 15695 | 12962 | 14285 | 2000 | 2000 | 1000 | 28816 | 28913 | 29020 | 28911 | 29020 |
64004 | 28943 | 233 | 19 | 0 | 0 | 10 | 0 | 1 | 1 | 0 | 0 | 137 | 0 | 0 | 4648 | 28555 | 0 | 0 | 0 | 23592 | 3000 | 1000 | 2002 | 1000 | 2000 | 5000 | 10000 | 0 | 10 | 16261 | 28304 | 28847 | 3 | 27 | 3000 | 4000 | 4004 | 28714 | 28805 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 4 | 2000 | 0 | 0 | 0 | 2 | 2000 | 4 | 0 | 2 | 0 | 0 | 0 | 13143 | 9214 | 6854 | 3143 | 14 | 60 | 19763 | 3283 | 3814 | 24 | 49 | 59 | 28284 | 1000 | 15846 | 13081 | 14574 | 2000 | 2000 | 1000 | 28856 | 28833 | 28932 | 28924 | 28933 |
64004 | 28818 | 232 | 22 | 1 | 0 | 23 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 4819 | 28569 | 0 | 0 | 0 | 23582 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10000 | 0 | 5 | 16267 | 28482 | 28883 | 3 | 10 | 3000 | 4000 | 4000 | 28716 | 28811 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 0 | 2000 | 0 | 0 | 0 | 3 | 2000 | 0 | 0 | 0 | 6 | 0 | 0 | 13165 | 9206 | 6866 | 3134 | 5 | 47 | 19893 | 3220 | 3824 | 23 | 50 | 54 | 28233 | 1000 | 15407 | 12817 | 14567 | 2000 | 2000 | 1000 | 28964 | 28909 | 28902 | 28966 | 28858 |
64004 | 28743 | 233 | 22 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 1 | 4 | 0 | 0 | 4591 | 28524 | 0 | 0 | 0 | 23690 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10072 | 0 | 1 | 16256 | 28384 | 28793 | 7 | 10 | 3000 | 4000 | 4000 | 28707 | 28771 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 4 | 2002 | 0 | 1 | 0 | 0 | 2000 | 2 | 0 | 0 | 4 | 0 | 0 | 13373 | 9481 | 6892 | 3081 | 12 | 60 | 19913 | 3219 | 3814 | 20 | 50 | 48 | 28285 | 1000 | 15443 | 13142 | 14543 | 2000 | 2000 | 1000 | 28818 | 29026 | 28915 | 28836 | 28738 |
64004 | 28776 | 232 | 19 | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4647 | 28505 | 0 | 0 | 0 | 23678 | 3000 | 1000 | 2000 | 1000 | 2000 | 5000 | 10000 | 0 | 4 | 16241 | 28447 | 28855 | 3 | 28 | 3000 | 4000 | 4000 | 28742 | 28764 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 2000 | 0 | 4 | 2002 | 0 | 0 | 0 | 0 | 2000 | 4 | 0 | 2 | 4 | 0 | 0 | 12986 | 9345 | 6923 | 3137 | 12 | 51 | 19784 | 3250 | 3811 | 18 | 50 | 51 | 28225 | 1000 | 15625 | 13036 | 14414 | 2000 | 2000 | 1000 | 28771 | 28890 | 28750 | 28786 | 28952 |
Count: 8
Code:
ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8 ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8 ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8 ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8 ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8 ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8 ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8 ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x6], x8
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch cond mispred nonspec (c5) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320205 | 80042 | 643 | 1 | 0 | 2 | 0 | 0 | 1 | 0 | 0 | 66 | 0 | 0 | 0 | 2 | 80026 | 2 | 14 | 15 | 0 | 25 | 240100 | 80100 | 160078 | 80100 | 160000 | 482444 | 1035378 | 0 | 80016 | 80041 | 80041 | 0 | 3 | 23 | 240217 | 200 | 320000 | 200 | 320156 | 80041 | 80132 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160011 | 11 | 40 | 160118 | 0 | 1 | 0 | 61 | 160037 | 6 | 1 | 47 | 40 | 10 | 1 | 0 | 0 | 5121 | 1 | 17 | 1 | 1 | 80038 | 80039 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80042 | 80042 |
320204 | 80041 | 652 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 79 | 0 | 0 | 0 | 2 | 80026 | 2 | 15 | 15 | 27 | 25 | 240100 | 80100 | 160000 | 80100 | 160000 | 480499 | 963842 | 0 | 80016 | 80041 | 80041 | 61 | 3 | 23 | 240100 | 200 | 320000 | 200 | 320000 | 80131 | 80041 | 2 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160012 | 11 | 40 | 160119 | 0 | 1 | 0 | 50 | 160036 | 6 | 1 | 47 | 40 | 10 | 1 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80039 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80134 | 80042 | 80042 |
320204 | 80041 | 652 | 1 | 2 | 1 | 1 | 0 | 1 | 0 | 0 | 329 | 0 | 0 | 0 | 2 | 80026 | 2 | 13 | 14 | 0 | 25 | 240100 | 80100 | 160000 | 80100 | 160000 | 480499 | 960928 | 0 | 80016 | 80041 | 80132 | 0 | 9 | 23 | 240100 | 200 | 320156 | 200 | 320000 | 80131 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160011 | 14 | 40 | 160048 | 1 | 0 | 1 | 50 | 160036 | 6 | 1 | 46 | 40 | 10 | 1 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80000 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80042 | 80042 |
320204 | 80041 | 643 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 54 | 0 | 0 | 0 | 2 | 80026 | 3 | 14 | 14 | 27 | 74 | 240451 | 80217 | 160078 | 80100 | 160000 | 480499 | 963729 | 0 | 80016 | 80041 | 80041 | 0 | 3 | 23 | 240100 | 200 | 320000 | 200 | 320000 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160012 | 12 | 40 | 160192 | 0 | 2 | 1 | 49 | 160037 | 6 | 1 | 46 | 40 | 10 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80000 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80042 | 80042 |
320204 | 80042 | 643 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 227 | 0 | 0 | 0 | 2 | 80026 | 2 | 15 | 14 | 0 | 25 | 240100 | 80100 | 160000 | 80100 | 160000 | 480499 | 960879 | 1 | 80016 | 80041 | 80041 | 0 | 3 | 23 | 240100 | 200 | 320000 | 200 | 320000 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160010 | 11 | 40 | 160048 | 0 | 0 | 0 | 54 | 160036 | 6 | 1 | 47 | 40 | 10 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80000 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80043 | 80042 |
320204 | 80041 | 643 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 56 | 0 | 0 | 0 | 2 | 80026 | 2 | 14 | 14 | 0 | 25 | 240100 | 80100 | 160000 | 80100 | 160000 | 480499 | 960877 | 0 | 80016 | 80041 | 80041 | 0 | 3 | 23 | 240100 | 200 | 320000 | 200 | 320000 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160011 | 10 | 42 | 160046 | 0 | 0 | 0 | 49 | 160037 | 6 | 1 | 48 | 39 | 11 | 1 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80000 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80042 | 80042 |
320204 | 80041 | 643 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 59 | 0 | 0 | 0 | 2 | 80026 | 2 | 15 | 14 | 0 | 25 | 240100 | 80100 | 160000 | 80100 | 160000 | 480499 | 961160 | 0 | 80101 | 80041 | 80041 | 0 | 3 | 23 | 240100 | 200 | 320000 | 200 | 320000 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160011 | 12 | 43 | 160049 | 0 | 1 | 0 | 46 | 160036 | 6 | 1 | 48 | 42 | 11 | 2 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80000 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80042 | 80042 |
320204 | 80041 | 643 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 68 | 0 | 0 | 0 | 2 | 80026 | 2 | 15 | 14 | 0 | 25 | 240100 | 80100 | 160000 | 80100 | 160000 | 480499 | 961188 | 0 | 80016 | 80041 | 80041 | 0 | 3 | 23 | 240100 | 200 | 320000 | 200 | 320000 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160011 | 11 | 40 | 160048 | 0 | 1 | 1 | 50 | 160039 | 6 | 1 | 46 | 40 | 11 | 1 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80000 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80042 | 80042 |
320204 | 80041 | 643 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 68 | 0 | 0 | 0 | 2 | 80026 | 2 | 15 | 14 | 0 | 25 | 240100 | 80100 | 160000 | 80100 | 160000 | 480499 | 960889 | 0 | 80017 | 80041 | 80041 | 0 | 3 | 23 | 240100 | 200 | 320000 | 200 | 320000 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160011 | 11 | 40 | 160047 | 1 | 1 | 0 | 49 | 160037 | 6 | 1 | 47 | 40 | 11 | 0 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80000 | 10 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80042 | 80042 |
320204 | 80041 | 643 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 68 | 0 | 0 | 0 | 2 | 80026 | 1 | 14 | 15 | 0 | 25 | 240100 | 80100 | 160000 | 80100 | 160000 | 480499 | 960884 | 0 | 80016 | 80041 | 80041 | 0 | 3 | 23 | 240100 | 200 | 320000 | 200 | 320000 | 80041 | 80041 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 100 | 160010 | 10 | 40 | 160048 | 0 | 1 | 0 | 54 | 160038 | 6 | 1 | 47 | 0 | 11 | 1 | 0 | 0 | 5109 | 1 | 17 | 1 | 1 | 80038 | 80000 | 9 | 9 | 160000 | 160000 | 80100 | 80042 | 80042 | 80042 | 80042 | 80042 |
Result (median cycles for code divided by count): 1.0005
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 24 | 3a | 3f | 43 | 46 | 49 | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | 67 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | c2 | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | e7 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
320025 | 80055 | 643 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 59 | 0 | 1 | 0 | 2 | 80026 | 2 | 14 | 14 | 0 | 25 | 240010 | 80010 | 160000 | 80010 | 160000 | 480049 | 960916 | 0 | 80016 | 0 | 80041 | 80041 | 0 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 160011 | 10 | 40 | 160048 | 2 | 0 | 11 | 160036 | 0 | 1 | 48 | 0 | 11 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 0 | 80000 | 9 | 9 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80042 | 80042 | 80042 |
320024 | 80041 | 642 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 57 | 0 | 0 | 0 | 0 | 80026 | 0 | 14 | 14 | 0 | 25 | 240010 | 80010 | 160000 | 80010 | 160000 | 480049 | 960030 | 0 | 80016 | 0 | 80041 | 80041 | 0 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 25 | 160030 | 1 | 0 | 32 | 160029 | 6 | 0 | 0 | 27 | 0 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 1 | 80000 | 10 | 0 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80042 | 80061 | 80042 |
320024 | 80041 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 47 | 0 | 0 | 0 | 1 | 80026 | 2 | 12 | 12 | 0 | 25 | 240010 | 80010 | 161870 | 80714 | 160000 | 480049 | 960369 | 0 | 80016 | 0 | 80111 | 80041 | 0 | 8 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 25 | 160030 | 0 | 0 | 21 | 160029 | 6 | 1 | 22 | 0 | 0 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 1 | 80000 | 10 | 6 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80042 | 80061 | 80042 |
320024 | 80041 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 38 | 0 | 0 | 0 | 1 | 80026 | 2 | 12 | 12 | 0 | 25 | 240010 | 80010 | 160000 | 80010 | 160000 | 480049 | 960000 | 0 | 80016 | 0 | 80041 | 80041 | 0 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 33 | 160030 | 0 | 0 | 29 | 160030 | 0 | 1 | 22 | 33 | 0 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 0 | 80000 | 10 | 0 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80042 | 80042 | 80042 |
320024 | 80041 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 1 | 80026 | 2 | 12 | 12 | 38 | 25 | 240010 | 80010 | 160000 | 80010 | 160000 | 480049 | 960196 | 0 | 80093 | 0 | 80041 | 80041 | 0 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 25 | 160101 | 1 | 0 | 22 | 160030 | 6 | 1 | 21 | 25 | 0 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 1 | 80000 | 10 | 6 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80042 | 80042 | 80042 |
320024 | 80041 | 642 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 80026 | 2 | 15 | 14 | 43 | 25 | 240010 | 80010 | 160000 | 80010 | 160000 | 480049 | 960904 | 0 | 80016 | 0 | 80041 | 80041 | 0 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160085 | 10 | 40 | 160048 | 0 | 0 | 47 | 160000 | 0 | 1 | 46 | 40 | 11 | 0 | 0 | 5019 | 1 | 17 | 1 | 2 | 80038 | 0 | 80000 | 9 | 9 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80513 | 80042 | 80042 |
320024 | 80041 | 643 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 72 | 0 | 0 | 0 | 2 | 80026 | 0 | 14 | 0 | 10 | 25 | 240010 | 80010 | 160000 | 80010 | 160000 | 480281 | 960023 | 0 | 80016 | 0 | 80041 | 80041 | 0 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160069 | 10 | 33 | 160032 | 0 | 0 | 29 | 160024 | 6 | 1 | 21 | 37 | 0 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 0 | 80000 | 10 | 12 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80042 | 80042 | 80042 |
320024 | 80041 | 643 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 0 | 0 | 1 | 80026 | 0 | 12 | 12 | 0 | 50 | 240010 | 80010 | 160000 | 80010 | 160000 | 480049 | 960342 | 0 | 80016 | 0 | 80041 | 80041 | 23 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 0 | 160032 | 0 | 0 | 0 | 160021 | 0 | 1 | 22 | 33 | 0 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 1 | 80000 | 10 | 6 | 0 | 160000 | 160000 | 80010 | 80042 | 80046 | 80042 | 80042 | 80042 |
320024 | 80041 | 643 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 80026 | 2 | 12 | 12 | 0 | 25 | 240010 | 80010 | 160000 | 80010 | 160000 | 480049 | 960179 | 0 | 80016 | 0 | 80041 | 80041 | 0 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 25 | 160000 | 0 | 0 | 30 | 160030 | 6 | 1 | 29 | 33 | 0 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 0 | 80000 | 10 | 12 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80047 | 80042 | 80042 |
320024 | 80041 | 642 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 36 | 0 | 0 | 0 | 1 | 80026 | 2 | 12 | 12 | 0 | 25 | 240010 | 80010 | 160000 | 80010 | 160000 | 480049 | 960338 | 0 | 80016 | 0 | 80041 | 80041 | 0 | 3 | 23 | 240010 | 20 | 320000 | 20 | 320000 | 80041 | 80041 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 160000 | 0 | 0 | 160030 | 1 | 0 | 30 | 160030 | 6 | 1 | 29 | 33 | 0 | 0 | 0 | 5019 | 1 | 17 | 1 | 1 | 80038 | 0 | 80000 | 0 | 0 | 0 | 160000 | 160000 | 80010 | 80042 | 80042 | 80042 | 80042 | 80042 |