Firestorm: LD1 (multiple, post-index, 4 regs, 8H) measurements

Code:

  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.000

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
64005	28747	224	4	0	0	0	3	0	0	0	0	0	12	0	0	4828	28480	0	4	3	22609	5000	1000	4000	1000	4000	5000	20716	7	16956	28292	28818	3	10	5000	4000	5000	28623	28559	1	1	61001	1000	1000	0	4000	8	4003	0	0	2	4000	5	1	6	8	0	0	13406	9544	7032	3224	1	66	19702	3119	3815	23	66	66	3	28239	1000	15524	12766	13722	4000	1000	28935	28690	28736	28849	28813
64004	28482	223	1	1	0	0	1	0	0	0	0	0	8	0	0	4771	28460	0	4	0	22732	5000	1000	4000	1000	4000	5000	20703	4	16961	28396	28785	3	10	5000	4000	5000	28733	28655	1	1	61001	1000	1000	0	4000	8	4003	0	0	2	4002	6	1	4	0	0	0	13420	9587	6945	3265	0	66	19736	3171	3819	18	68	66	3	28123	1000	15580	12750	13584	4000	1000	28727	28612	28645	28731	28724
64004	28692	222	2	1	0	0	1	0	0	0	0	0	0	0	0	4784	28652	0	0	0	22784	5000	1000	4000	1000	4000	5000	20713	6	16942	28411	28785	3	10	5000	4000	5000	28639	28675	1	1	61001	1000	1000	0	4000	8	4002	0	0	0	4003	6	1	4	12	0	0	13387	9427	6989	3230	1	66	19759	3207	3819	27	70	64	3	28155	1000	15435	12299	13707	4000	1000	28739	28864	28666	28564	28709
64004	28686	223	2	1	0	0	1	0	0	0	0	0	8	0	0	4761	28734	0	3	4	22744	5000	1000	4000	1000	4000	5000	20715	8	16931	28389	28753	3	10	5000	4000	5000	28656	28692	1	1	61001	1000	1000	1	4000	0	4000	0	0	0	4002	6	1	4	8	0	0	13076	9489	6917	3082	0	65	19774	3145	3816	17	71	66	2	28249	1000	15382	12610	14182	4000	1000	28836	28686	28755	28722	28758
64004	29625	226	1	1	0	0	1	0	0	0	0	0	0	0	0	4866	28622	0	0	0	22761	5000	1000	4000	1000	4000	5000	20717	4	16926	28438	28761	3	10	5000	4000	5000	28702	28771	1	1	61001	1000	1000	0	4000	8	4000	0	0	224	4002	4	0	4	8	0	0	13434	9546	6992	3193	0	67	19803	3160	3816	18	64	70	3	28222	1000	15311	12518	13954	4000	1000	28783	28734	28767	28761	28690
64004	28869	223	1	1	0	0	0	0	0	0	0	0	12	88	0	4795	28446	0	0	0	22813	5000	1000	4000	1000	4000	5000	20706	2	16948	28275	28844	3	10	5000	4000	5000	28696	28595	1	1	61001	1000	1000	0	4000	8	4000	0	0	5	4006	6	1	0	0	0	0	13321	9520	7037	3223	0	91	19858	3175	3819	21	78	71	3	28160	1000	15307	12405	13838	4000	1000	28660	28771	28806	28701	28711
64004	28799	223	3	0	1	0	1	0	0	0	0	0	12	0	0	4841	28594	2	0	0	22709	5000	1000	4000	1000	4000	5000	20715	3	16959	28383	28729	3	10	5000	4000	5000	28628	28705	1	1	61001	1000	1000	0	4000	0	4000	0	0	4	4002	0	0	4	8	0	0	13295	9354	7006	3162	0	60	19739	3163	3820	21	61	71	3	28181	1000	15639	12548	13906	4000	1000	28773	28882	28814	28743	28746
64004	28811	223	1	1	0	0	1	0	0	0	0	0	0	0	0	4850	28645	0	0	4	22770	5000	1000	4000	1000	4000	5000	20731	1	16929	28305	28817	3	10	5000	4000	5000	28606	28524	1	1	61001	1000	1000	0	4000	8	4006	0	0	0	4006	0	0	4	12	0	0	13194	9415	6990	3246	0	63	19704	3199	3810	13	65	65	3	28203	1000	15560	12761	13997	4000	1000	28599	28708	28891	28691	28767
64004	28696	222	1	1	0	0	1	0	0	0	0	0	12	0	0	4844	28574	0	4	3	22785	5000	1000	4000	1000	4000	5000	20717	3	16922	28297	28765	3	10	5000	4004	5000	28738	28614	1	1	61001	1000	1000	0	4000	8	4000	0	0	13	4006	6	0	0	0	0	0	13220	9316	6995	3165	0	66	19829	3197	3815	25	69	66	3	28140	1000	15276	12750	14072	4000	1000	28826	28702	28584	28802	28735
64004	28766	224	2	0	0	0	0	0	0	0	0	0	0	0	0	4749	28620	0	4	3	22556	5000	1000	4000	1000	4000	5000	20720	4	16947	28347	28795	3	10	5000	4000	5000	28690	28742	1	1	61002	1000	1000	1	4000	0	4000	0	0	6	4006	6	0	0	12	0	0	13276	9482	7023	3223	0	66	19785	3208	3810	26	65	67	3	28151	1000	15193	12628	13739	4000	1000	28682	28802	28774	28767	28708

Count: 8

Code:

  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320205	106736	827	1	0	1	1	1	0	0	0	65	0	1	0	0	0	106728	0	18	18	1	25	400100	80100	320000	80100	320000	480497	4678230	0	106707	106714	106717	26662	3	26719	400100	200	320000	200	400000	106732	106732	1	1	80202	100	99	0	100	100	80000	80000	0	100	320018	18	44	0	320059	1	0	0	59	320040	0	1	58	0	18	1	0	0	0	5110	1	17	1	1	106710	80000	9	9	1	320000	80100	106736	106715	106747	106733	106733
320204	106732	828	1	0	0	0	1	0	0	0	65	0	1	0	0	2	106708	2	18	18	17	25	400100	80100	320000	80100	320000	480476	4710870	0	106707	106736	106819	26881	3	26715	400100	200	320000	200	400000	106732	106732	1	1	80201	100	99	1	100	100	80000	80000	0	100	320019	18	0	0	320058	1	0	0	2457	320000	6	1	59	44	18	0	0	0	0	5109	1	17	1	1	106733	80000	9	0	0	320000	80100	106733	106733	106737	106733	106747
320204	106732	828	1	1	0	0	0	1	0	0	18	0	0	0	0	0	106699	0	0	18	16	25	400100	80100	320000	80100	320000	480473	4727551	0	106707	106713	106735	26688	3	26719	400100	200	320000	200	400000	106732	106732	1	1	80201	100	99	0	100	100	80000	80000	0	100	320018	19	44	0	320059	0	0	0	62	320040	0	1	59	44	18	0	0	0	0	5109	1	17	1	1	106729	80000	9	9	1	320000	80100	106733	106737	106733	106714	106733
320204	106732	827	1	0	0	1	0	0	0	0	30	0	0	0	0	0	106699	2	18	18	17	25	400100	80100	320000	80100	320000	480476	4708681	0	106689	106714	106714	26685	3	26714	400100	200	320000	200	400000	106732	106732	1	1	80201	100	99	0	100	100	80000	80000	0	100	320019	18	43	0	320059	0	0	2	58	320041	0	0	59	45	18	0	0	0	0	5109	1	16	1	1	106729	80000	9	9	1	320000	80100	106733	106718	106715	106733	106715
320204	106732	827	1	1	0	0	1	1	0	0	76	0	0	0	0	2	106699	0	18	9	16	25	400100	80100	320000	80100	320000	480496	4667884	0	106688	106713	106732	26681	3	26696	400100	200	320000	200	400000	106714	106713	1	1	80201	100	99	0	100	100	80000	80000	0	100	320018	18	43	0	320059	0	0	0	59	320041	6	1	59	44	18	1	0	0	0	5109	1	17	1	1	106711	80000	9	9	1	320000	80100	106733	106715	106735	106733	106733
320204	106732	827	1	0	0	0	0	0	0	0	18	0	0	1	0	0	106699	0	18	18	16	25	400100	80100	320000	80100	320000	480498	4678230	0	106707	106736	106732	26680	3	26714	400100	200	320000	200	400000	106732	106713	1	1	80201	100	99	0	100	100	80000	80000	0	100	320020	18	45	0	320018	0	0	0	58	320041	6	1	59	0	18	0	0	0	0	5110	1	16	1	1	106729	80000	9	9	1	320000	80100	106733	106737	106714	106715	106733
320204	106805	827	1	0	0	0	0	0	0	0	65	0	0	0	0	2	106717	3	18	18	16	25	400100	80100	320000	80100	320000	480497	4706976	0	106707	106732	106742	26679	3	26714	400100	200	320000	200	400000	106732	106732	1	1	80201	100	99	0	100	100	80000	80000	0	100	320018	18	44	0	320018	0	0	1	18	320040	6	1	59	44	18	0	0	0	0	5109	1	16	1	1	106729	80000	9	9	0	320000	80100	106737	106737	106733	106733	106733
320204	106732	827	1	0	0	0	0	0	0	0	64	0	0	0	0	3	106717	3	18	18	0	25	400100	80100	320000	80100	320000	473948	4706976	0	106707	106732	106736	26680	3	26719	400100	200	320000	200	400000	106732	106732	1	1	80201	100	99	0	100	100	80000	80000	0	100	320018	18	0	0	320059	0	0	2	58	320041	6	1	59	44	18	0	0	0	0	5110	1	16	1	1	106714	80000	9	9	0	320000	80100	106733	106733	106733	106733	106733
320204	106714	828	1	1	1	1	0	1	0	0	64	0	0	1	0	1	106717	2	18	18	16	25	400100	80100	320000	80100	320000	480474	4669265	0	106707	106732	106717	26663	3	26715	400100	200	320000	200	400000	106732	106732	1	1	80201	100	99	0	100	100	80000	80000	0	100	320018	18	44	0	320058	0	0	0	59	320041	0	0	58	44	18	0	0	0	0	5109	1	17	1	1	106729	80000	9	9	1	320000	80100	106733	106714	106733	106733	106733
320204	106732	827	1	0	0	0	0	0	0	0	64	0	0	0	0	2	106699	3	18	0	16	25	400100	80100	320000	80100	320000	480497	4669265	0	106707	106732	106732	26680	3	26697	400100	200	320000	200	400000	106732	106732	1	1	80201	100	99	0	100	100	80000	80000	0	100	320018	18	0	31	320059	0	0	0	853	320171	6	1	58	44	18	0	0	0	0	5121	1	26	1	1	106729	80049	9	9	0	320000	80100	106883	106714	106715	106884	106715

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
320025	106729	827	0	1	0	1	1	0	0	48	0	1	0	2	106693	3	4	4	17	25	400010	80010	320000	80010	320000	480042	4735007	0	0	106710	106731	106727	26680	3	26714	400010	20	320000	20	400000	106731	106727	1	1	80021	10	9	1	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	3	320042	6	1	42	45	0	5019	10	16	10	9	106729	80000	14	10	320000	80010	106732	106709	106709	106732	106732
320024	106735	828	0	0	0	1	1	0	0	48	0	0	0	2	106716	3	4	0	17	25	400010	80010	320000	80010	320000	480024	4690417	0	0	106706	106735	106733	26682	3	26691	400010	20	320000	20	400000	106731	106727	1	1	80021	10	9	0	10	10	80000	80000	1	10	320000	0	0	0	320000	0	0	41	320042	6	1	42	0	0	5020	10	16	8	11	106724	80000	10	0	320000	80010	106732	106709	106732	106728	106732
320024	106727	827	0	0	0	0	0	0	0	48	0	1	0	1	106723	3	4	15	22	25	400010	80010	320000	80010	320000	480044	4716548	0	0	106715	106736	106736	26685	3	26710	400010	22	323456	20	400000	106731	106727	1	1	80021	10	9	5	10	10	80000	80000	1	10	320000	0	45	0	320042	0	0	6	320000	6	1	41	45	0	5020	11	16	10	8	106731	80000	14	10	320000	80010	106709	106732	106709	106732	106728
320024	106708	827	0	0	0	0	0	0	0	0	0	1	0	2	106696	3	0	15	2	25	400010	80010	320000	80010	320000	480044	4666415	0	0	106702	106727	106731	26732	3	26695	400010	20	320000	20	400000	106719	106883	1	1	80021	10	9	1	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	42	320042	6	0	42	45	0	5019	10	16	12	12	106709	80000	14	0	320000	80010	106728	106732	106728	106713	106709
320024	106708	828	0	0	0	0	0	1	0	48	0	1	0	2	106716	0	15	4	17	25	400010	80010	320000	80010	320000	480048	4735155	0	0	106706	106731	106731	26679	12	26691	400010	20	320000	20	400000	106708	106708	1	1	80021	10	9	5	10	10	80000	80000	1	10	320000	0	45	0	320042	0	0	837	320042	6	1	0	45	0	5020	11	16	7	12	106724	80000	10	10	320000	80010	106861	106728	106728	106728	106728
320024	106727	828	0	0	0	1	1	0	0	48	0	1	0	0	106712	3	4	15	21	25	400188	80010	320000	80010	320000	480046	4668227	0	0	106711	106713	106713	26662	3	26710	400235	20	320000	20	400000	106731	106712	1	1	80021	10	9	5	10	10	80000	80000	1	10	320000	0	45	0	320000	0	0	45	320172	6	1	42	45	0	5020	13	16	7	9	106728	80000	10	10	320000	80010	106732	106732	106732	106736	106732
320024	106731	827	0	0	0	1	0	0	0	0	88	0	0	2	106732	3	4	0	19	25	400010	80010	320130	80010	320000	480048	4734671	0	0	106843	106708	106735	26656	3	26714	400010	20	320000	20	400000	106731	106727	1	1	80021	10	9	1	10	10	80000	80000	0	10	320000	0	45	0	320042	0	0	42	320042	6	1	0	0	0	5020	8	16	10	8	106732	80000	0	14	320000	80010	106732	106732	106733	106729	106728
320024	106855	827	0	0	0	0	1	0	0	21	0	0	1	0	106716	3	4	4	0	34	400010	80010	320000	80010	320000	480044	4734671	0	0	106706	106729	106727	26735	3	26718	400010	20	320000	20	400000	106731	106908	1	1	80021	10	9	0	10	10	80000	80000	1	10	320000	0	0	0	320042	0	0	0	320042	6	1	42	45	0	5020	10	17	9	9	106732	80000	10	10	320000	80010	106728	106732	106732	106732	106709
320024	106708	827	0	0	0	1	1	1	0	48	0	0	1	2	106720	0	4	4	95	25	400010	80010	320000	80010	320000	480048	4734671	0	0	106683	106731	106731	26656	3	26714	400010	20	320000	20	400000	106708	106727	1	1	80021	10	9	1	10	10	80000	80000	0	10	320000	0	45	0	320042	1	0	0	320042	6	1	42	45	0	5032	11	16	10	10	106728	80000	10	0	320000	80010	106888	106732	106739	106740	106728
320024	106727	827	0	0	0	1	1	0	0	12	0	0	1	0	106869	3	4	0	0	50	400010	80010	320000	80010	320000	480046	4655056	0	0	106712	106737	106736	26688	3	26784	400010	20	320000	20	400000	106731	106708	1	1	80021	10	9	5	10	10	80000	80000	0	10	320000	0	0	0	320042	0	0	42	320000	6	0	42	0	0	5019	7	16	13	10	106705	80000	14	0	320000	80010	106732	106732	106882	106732	106732

LD1 (multiple, post-index, 4 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations