Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1 { v0.d }[1], [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.001
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.001
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | 0e | 0f | 1e | 22 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
62005 | 29426 | 221 | 25 | 22 | 1 | 0 | 4 | 0 | 4554 | 28762 | 0 | 0 | 17353 | 2001 | 1002 | 1000 | 1000 | 1000 | 5000 | 11899 | 5 | 22695 | 29071 | 29294 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29161 | 29237 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 3 | 1000 | 0 | 0 | 3 | 1002 | 2 | 1 | 0 | 0 | 13582 | 9251 | 6857 | 3062 | 9 | 89 | 20841 | 3087 | 3814 | 21 | 66 | 65 | 28410 | 16343 | 13954 | 15345 | 1000 | 1000 | 29330 | 29360 | 29402 | 29429 | 29214 |
62004 | 29353 | 219 | 23 | 27 | 0 | 0 | 0 | 0 | 4629 | 28892 | 0 | 0 | 17241 | 2002 | 1002 | 1000 | 1000 | 1000 | 5000 | 11907 | 4 | 22600 | 29029 | 29286 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29170 | 29149 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 2 | 1000 | 0 | 0 | 0 | 1000 | 3 | 1 | 3 | 0 | 13078 | 9245 | 6802 | 3003 | 14 | 64 | 20807 | 3061 | 3813 | 16 | 65 | 62 | 28457 | 16218 | 14183 | 15322 | 1000 | 1000 | 29347 | 29309 | 29374 | 29176 | 29432 |
62004 | 29335 | 220 | 25 | 20 | 0 | 0 | 0 | 0 | 4582 | 28845 | 0 | 0 | 17296 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11941 | 0 | 22647 | 29086 | 29204 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29091 | 29145 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 3 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 3 | 0 | 13219 | 9168 | 6843 | 3059 | 15 | 65 | 20688 | 3055 | 3818 | 18 | 64 | 67 | 28467 | 16250 | 13877 | 15262 | 1000 | 1000 | 29366 | 29356 | 29312 | 29355 | 29482 |
62004 | 29289 | 220 | 24 | 25 | 0 | 0 | 0 | 0 | 4639 | 28846 | 0 | 0 | 17327 | 2001 | 1000 | 1000 | 1000 | 1000 | 5000 | 11944 | 0 | 22633 | 29112 | 29191 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29126 | 29145 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 2 | 1000 | 0 | 0 | 597 | 1001 | 0 | 0 | 2 | 0 | 12831 | 9418 | 6862 | 3149 | 14 | 60 | 20697 | 3047 | 3815 | 13 | 64 | 62 | 28358 | 16481 | 14105 | 15236 | 1000 | 1000 | 29358 | 29320 | 29305 | 29290 | 29329 |
62004 | 29428 | 220 | 27 | 20 | 0 | 0 | 0 | 0 | 4647 | 28818 | 1 | 0 | 17363 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11935 | 4 | 22662 | 29131 | 29334 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29138 | 29132 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1000 | 0 | 0 | 0 | 1000 | 3 | 0 | 0 | 0 | 12966 | 9328 | 6747 | 3050 | 8 | 63 | 20776 | 3060 | 3813 | 12 | 74 | 62 | 28379 | 16293 | 13774 | 15209 | 1000 | 1000 | 29266 | 29301 | 29363 | 29225 | 29358 |
62004 | 29412 | 220 | 24 | 29 | 0 | 0 | 8 | 0 | 4595 | 28813 | 1 | 0 | 17273 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11954 | 3 | 22634 | 29143 | 29276 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29161 | 29316 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 3 | 0 | 12924 | 9277 | 6864 | 3013 | 10 | 63 | 20711 | 3104 | 3813 | 14 | 67 | 63 | 28450 | 16227 | 13867 | 15256 | 1000 | 1000 | 29386 | 29315 | 29357 | 29336 | 29293 |
62004 | 29333 | 219 | 24 | 35 | 0 | 1 | 0 | 1 | 4596 | 28825 | 1 | 0 | 17319 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11903 | 0 | 22638 | 29110 | 29419 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29112 | 29056 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 3 | 1000 | 0 | 0 | 0 | 1000 | 3 | 0 | 0 | 0 | 12965 | 9252 | 6854 | 3097 | 11 | 62 | 20605 | 3116 | 3815 | 14 | 64 | 67 | 28434 | 16138 | 13815 | 15221 | 1000 | 1000 | 29280 | 29218 | 29288 | 29267 | 29220 |
62004 | 29277 | 220 | 20 | 21 | 0 | 0 | 2 | 0 | 4635 | 28894 | 0 | 0 | 17308 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11943 | 3 | 22573 | 29088 | 29268 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29140 | 29109 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 1002 | 0 | 0 | 0 | 1001 | 2 | 0 | 2 | 0 | 13517 | 9248 | 6810 | 3109 | 13 | 63 | 20666 | 3284 | 3811 | 18 | 60 | 65 | 28409 | 15934 | 13911 | 15410 | 1000 | 1000 | 29295 | 29239 | 29359 | 29314 | 29275 |
62004 | 29328 | 220 | 27 | 24 | 0 | 0 | 0 | 0 | 4541 | 28829 | 0 | 1 | 17196 | 2000 | 1001 | 1000 | 1000 | 1000 | 5000 | 11907 | 0 | 22641 | 29035 | 29348 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29205 | 29116 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 1001 | 0 | 0 | 0 | 1000 | 3 | 0 | 0 | 0 | 12982 | 9191 | 6936 | 3078 | 14 | 64 | 20667 | 3229 | 3811 | 17 | 69 | 63 | 28376 | 16344 | 13984 | 15168 | 1000 | 1000 | 29263 | 29367 | 29260 | 29295 | 29358 |
62004 | 29362 | 219 | 19 | 22 | 0 | 0 | 0 | 1 | 4647 | 28794 | 0 | 1 | 17310 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11944 | 8 | 22654 | 29069 | 29148 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 29167 | 29156 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 1000 | 0 | 0 | 3 | 1001 | 2 | 0 | 3 | 0 | 12930 | 9202 | 6862 | 3083 | 9 | 63 | 20680 | 3149 | 3811 | 11 | 64 | 62 | 28679 | 16353 | 13940 | 15324 | 1000 | 1000 | 29255 | 29434 | 29355 | 29391 | 29404 |
Chain cycles: 3
Code:
ld1 { v0.d }[1], [x6] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 11.0051
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60205 | 140051 | 1049 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140027 | 140051 | 140051 | 131797 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 2 | 126 | 2 | 2 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140036 | 140036 | 140052 | 140052 | 140036 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140027 | 140051 | 140035 | 131797 | 0 | 3 | 132399 | 60425 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 2 | 126 | 2 | 2 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140036 | 140052 | 140036 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140020 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6692947 | 14310939 | 1 | 140027 | 140051 | 140099 | 131797 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 2 | 126 | 3 | 2 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140036 | 140052 | 140052 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70100 | 40100 | 20002 | 10000 | 30100 | 20000 | 10055 | 1263814 | 6693734 | 14310939 | 1 | 140027 | 140035 | 140051 | 131797 | 0 | 3 | 132382 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140035 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 1 | 0 | 3 | 10000 | 1 | 0 | 0 | 0 | 3210 | 2 | 126 | 2 | 2 | 139663 | 40000 | 0 | 10 | 10 | 10000 | 10000 | 40100 | 140036 | 140052 | 140052 | 140052 | 140052 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70100 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140027 | 140051 | 140035 | 131797 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140035 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 2 | 126 | 2 | 2 | 139560 | 40000 | 0 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140036 | 140036 | 140052 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140027 | 140051 | 140051 | 131797 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3210 | 2 | 127 | 3 | 3 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140052 | 140052 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 140020 | 139411 | 129363 | 25 | 70102 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6692947 | 14308701 | 1 | 140027 | 140051 | 140051 | 131793 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140056 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3210 | 3 | 127 | 3 | 3 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140052 | 140052 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129347 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693734 | 14310939 | 0 | 140027 | 140051 | 140051 | 131797 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140035 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 2 | 126 | 2 | 2 | 139559 | 40000 | 10 | 0 | 10 | 10000 | 10000 | 40100 | 140036 | 140036 | 140052 | 140052 | 140036 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693734 | 14310939 | 0 | 140028 | 140051 | 140051 | 131797 | 0 | 3 | 132382 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140054 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 3 | 126 | 2 | 2 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140036 | 140052 | 140036 | 140052 | 140052 |
60204 | 140106 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 140036 | 139411 | 129364 | 25 | 70100 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6692947 | 14310939 | 0 | 140011 | 140035 | 140051 | 131797 | 0 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3210 | 3 | 126 | 3 | 3 | 139559 | 40000 | 0 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140052 | 140052 |
Result (median cycles for code, minus 3 chain cycles): 11.0047
retire uop (01) | cycle (02) | 03 | l1i tlb fill (04) | mmu table walk data (08) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60025 | 140047 | 1048 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140413 | 139397 | 129362 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6693878 | 14325829 | 1 | 140026 | 140050 | 140050 | 131815 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140050 | 140047 | 2 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3140 | 0 | 11 | 113 | 9 | 13 | 139554 | 40000 | 0 | 6 | 6 | 10000 | 10000 | 40010 | 140036 | 140036 | 140051 | 140036 | 140051 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 140035 | 139397 | 129347 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264429 | 6692947 | 14321442 | 1 | 140026 | 140035 | 140050 | 131814 | 0 | 3 | 132420 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3140 | 0 | 8 | 113 | 8 | 11 | 139569 | 40000 | 9 | 6 | 9 | 10000 | 10000 | 40010 | 140051 | 140036 | 140048 | 140048 | 140048 |
60024 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 140032 | 139401 | 129347 | 25 | 70012 | 40010 | 20000 | 10001 | 30010 | 20000 | 10000 | 1264443 | 6693538 | 14325829 | 1 | 140011 | 140035 | 140050 | 131818 | 0 | 3 | 132437 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 3140 | 0 | 10 | 111 | 13 | 10 | 139569 | 40000 | 9 | 0 | 9 | 10000 | 10000 | 40010 | 140036 | 140051 | 140051 | 140036 | 140036 |
60024 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 562 | 0 | 0 | 0 | 0 | 140032 | 139394 | 129347 | 25 | 70012 | 40010 | 20002 | 10002 | 30010 | 20000 | 10000 | 1264429 | 6692947 | 14326033 | 1 | 140023 | 140047 | 140035 | 131815 | 0 | 3 | 132420 | 60010 | 30020 | 10000 | 20125 | 60020 | 10000 | 30000 | 140054 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 0 | 11 | 113 | 11 | 11 | 139569 | 40000 | 0 | 0 | 0 | 10000 | 10000 | 40010 | 140051 | 140051 | 140051 | 140036 | 140036 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 140020 | 139397 | 129362 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6692947 | 14325829 | 1 | 140026 | 140050 | 140035 | 131803 | 0 | 3 | 132420 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 0 | 3140 | 0 | 11 | 111 | 12 | 13 | 139569 | 40000 | 9 | 6 | 0 | 10000 | 10000 | 40010 | 140051 | 140051 | 140051 | 140036 | 140036 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 140043 | 139394 | 129348 | 25 | 70012 | 40010 | 20000 | 10000 | 30152 | 20000 | 10000 | 1264477 | 6693538 | 14325829 | 1 | 140011 | 140050 | 140047 | 131815 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140050 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 0 | 11 | 113 | 12 | 12 | 139569 | 40000 | 9 | 6 | 6 | 10000 | 10000 | 40010 | 140051 | 140036 | 140051 | 140051 | 140036 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140020 | 139402 | 129347 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264429 | 6692947 | 14321442 | 1 | 140026 | 140055 | 140050 | 131803 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 10000 | 4 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 0 | 13 | 113 | 11 | 9 | 139569 | 40000 | 0 | 0 | 0 | 10000 | 10000 | 40010 | 140036 | 140051 | 140051 | 140051 | 140051 |
60024 | 140047 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 140034 | 139394 | 129359 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264429 | 6693902 | 14321442 | 1 | 140023 | 140050 | 140051 | 131818 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 10001 | 0 | 0 | 10000 | 1 | 0 | 0 | 0 | 3140 | 0 | 9 | 113 | 13 | 14 | 139554 | 40000 | 9 | 6 | 9 | 10000 | 10000 | 40010 | 140051 | 140051 | 140036 | 140048 | 140051 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 140035 | 139397 | 129362 | 25 | 70012 | 40010 | 20000 | 10000 | 30010 | 20000 | 10000 | 1264429 | 6693685 | 14326112 | 1 | 140031 | 140050 | 140050 | 131803 | 0 | 3 | 132420 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140050 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10001 | 0 | 1 | 10000 | 1 | 0 | 0 | 0 | 3140 | 0 | 12 | 111 | 10 | 7 | 139569 | 40000 | 9 | 9 | 9 | 10000 | 10000 | 40010 | 140051 | 140036 | 140036 | 140036 | 140036 |
60025 | 140053 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 140020 | 139397 | 129359 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6692947 | 14326112 | 1 | 140011 | 140050 | 140050 | 131818 | 0 | 3 | 132433 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140050 | 140035 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 0 | 10 | 113 | 10 | 12 | 139554 | 40000 | 0 | 0 | 9 | 10000 | 10000 | 40010 | 140051 | 140052 | 140051 | 140051 | 140051 |
Count: 8
Code:
ld1 { v0.d }[1], [x6] ld1 { v0.d }[1], [x6] ld1 { v0.d }[1], [x6] ld1 { v0.d }[1], [x6] ld1 { v0.d }[1], [x6] ld1 { v0.d }[1], [x6] ld1 { v0.d }[1], [x6] ld1 { v0.d }[1], [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 2.0006
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4e | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | branch mispred nonspec (cb) | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160205 | 160052 | 1199 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 41 | 0 | 1 | 0 | 1 | 160037 | 2 | 18 | 18 | 159686 | 12 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421810 | 22939240 | 160033 | 160052 | 160052 | 139687 | 3 | 140010 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160052 | 160052 | 1 | 1 | 80202 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80000 | 0 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 5110 | 0 | 0 | 4 | 16 | 1 | 1 | 160049 | 0 | 0 | 6 | 2 | 80000 | 80000 | 100 | 160041 | 160041 | 160041 | 160053 | 160053 |
160204 | 160052 | 1199 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 1 | 0 | 1 | 160037 | 2 | 18 | 18 | 159686 | 12 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421017 | 22938147 | 160033 | 160052 | 160052 | 139687 | 3 | 140010 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160052 | 160040 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80000 | 0 | 0 | 35 | 80000 | 6 | 1 | 35 | 39 | 1 | 5110 | 0 | 0 | 1 | 16 | 1 | 1 | 160049 | 0 | 6 | 0 | 2 | 80000 | 80000 | 100 | 160053 | 160053 | 160053 | 160053 | 160053 |
160204 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 1 | 0 | 1 | 160037 | 0 | 18 | 18 | 159686 | 11 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421810 | 22939240 | 160021 | 160052 | 160040 | 139687 | 3 | 140010 | 160100 | 200 | 80000 | 80171 | 200 | 80000 | 160000 | 160052 | 160052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 35 | 80036 | 6 | 0 | 35 | 39 | 0 | 5138 | 3 | 0 | 1 | 16 | 1 | 1 | 160049 | 0 | 6 | 6 | 2 | 80000 | 80000 | 100 | 160053 | 160041 | 160053 | 160053 | 160053 |
160204 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 160037 | 2 | 18 | 0 | 159686 | 12 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421810 | 22939240 | 160033 | 160052 | 160052 | 139687 | 3 | 140010 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160052 | 160052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 35 | 80000 | 6 | 1 | 35 | 0 | 0 | 5110 | 0 | 0 | 1 | 16 | 1 | 1 | 160037 | 0 | 6 | 6 | 2 | 80000 | 80000 | 100 | 160053 | 160053 | 160053 | 160041 | 160053 |
160204 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 0 | 0 | 1 | 160037 | 2 | 18 | 18 | 159690 | 11 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421810 | 22939240 | 160033 | 160052 | 160052 | 139687 | 3 | 140010 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160052 | 160052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 5110 | 0 | 0 | 1 | 16 | 1 | 1 | 160049 | 0 | 0 | 0 | 2 | 80000 | 80000 | 100 | 160053 | 160053 | 160053 | 160053 | 160053 |
160204 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 1 | 0 | 1 | 160025 | 2 | 18 | 18 | 159686 | 0 | 25 | 160102 | 100 | 80014 | 80000 | 100 | 80000 | 80000 | 500 | 421810 | 22939228 | 160033 | 160052 | 160052 | 139687 | 3 | 140010 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160052 | 160052 | 3 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 35 | 80035 | 6 | 1 | 0 | 39 | 0 | 5110 | 0 | 0 | 1 | 16 | 1 | 1 | 160037 | 0 | 6 | 6 | 2 | 80000 | 80000 | 100 | 160053 | 160053 | 160053 | 160053 | 160053 |
160204 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 160037 | 2 | 18 | 18 | 159690 | 12 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421810 | 22939203 | 160033 | 160052 | 160052 | 139687 | 3 | 140010 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160052 | 160052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80000 | 0 | 0 | 35 | 80035 | 6 | 1 | 35 | 0 | 0 | 5110 | 0 | 0 | 1 | 16 | 1 | 1 | 160037 | 0 | 6 | 0 | 0 | 80000 | 80000 | 100 | 160041 | 160053 | 160053 | 160053 | 160053 |
160204 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 160037 | 2 | 18 | 18 | 159686 | 12 | 25 | 160100 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421810 | 22939240 | 160033 | 160052 | 160052 | 139687 | 3 | 140010 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160048 | 160060 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 38 | 80035 | 6 | 1 | 35 | 39 | 0 | 5110 | 0 | 0 | 1 | 16 | 1 | 1 | 160037 | 0 | 6 | 6 | 2 | 80000 | 80000 | 100 | 160053 | 160041 | 160041 | 160053 | 160041 |
160204 | 160052 | 1198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 0 | 0 | 1 | 160037 | 2 | 18 | 18 | 159690 | 11 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421017 | 22939240 | 160021 | 160052 | 160040 | 139687 | 3 | 139998 | 160100 | 200 | 80000 | 80000 | 200 | 80171 | 160000 | 160052 | 160052 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 0 | 0 | 80000 | 0 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 5110 | 0 | 0 | 1 | 16 | 1 | 1 | 160049 | 0 | 6 | 0 | 2 | 80000 | 80000 | 100 | 160053 | 160053 | 160053 | 160041 | 160041 |
160204 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 41 | 0 | 1 | 0 | 1 | 160037 | 0 | 0 | 0 | 159686 | 12 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421017 | 22939240 | 160021 | 160040 | 160040 | 139687 | 3 | 139998 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160052 | 160100 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 5110 | 0 | 0 | 1 | 16 | 1 | 1 | 160049 | 0 | 6 | 0 | 2 | 80000 | 80000 | 100 | 160053 | 160053 | 160053 | 160053 | 160053 |
Result (median cycles for code divided by count): 2.0006
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | 09 | 0e | 18 | 19 | 1e | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4e | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | st unit uop (a7) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | l1d tlb miss nonspec (c1) | cf | d0 | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160025 | 160052 | 1199 | 0 | 1 | 0 | 0 | 0 | 45 | 1 | 0 | 2 | 160025 | 2 | 18 | 18 | 159684 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422066 | 22938147 | 1 | 160033 | 0 | 160052 | 160052 | 139709 | 3 | 140032 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160040 | 160052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80039 | 0 | 0 | 0 | 0 | 80039 | 6 | 0 | 35 | 0 | 0 | 5020 | 0 | 0 | 7 | 16 | 4 | 7 | 160053 | 10 | 6 | 4 | 80000 | 80000 | 10 | 160057 | 160057 | 160041 | 160107 | 160041 |
160024 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 2 | 160086 | 2 | 12 | 12 | 159690 | 16 | 25 | 160012 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 50 | 422066 | 22939240 | 1 | 160021 | 0 | 160056 | 160052 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 0 | 35 | 80035 | 6 | 1 | 35 | 39 | 0 | 5020 | 0 | 0 | 3 | 16 | 7 | 6 | 160049 | 0 | 6 | 4 | 80000 | 80000 | 10 | 160057 | 160057 | 160057 | 160057 | 160041 |
160024 | 160040 | 1199 | 0 | 0 | 0 | 0 | 0 | 41 | 1 | 0 | 2 | 160025 | 2 | 18 | 12 | 159690 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 421085 | 22939240 | 1 | 160021 | 0 | 160056 | 160056 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 80000 | 0 | 39 | 0 | 80035 | 0 | 0 | 0 | 39 | 80039 | 0 | 0 | 35 | 39 | 0 | 5020 | 0 | 1 | 8 | 16 | 9 | 7 | 160053 | 0 | 6 | 0 | 80000 | 80000 | 10 | 160057 | 160057 | 160057 | 160041 | 160041 |
160024 | 160240 | 1199 | 0 | 0 | 0 | 0 | 2 | 45 | 0 | 0 | 2 | 160025 | 2 | 12 | 12 | 159690 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 421878 | 22938147 | 0 | 160037 | 0 | 160056 | 160052 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160040 | 160052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80040 | 0 | 1 | 0 | 39 | 80039 | 6 | 1 | 35 | 43 | 0 | 5020 | 0 | 0 | 4 | 16 | 4 | 4 | 160053 | 10 | 6 | 4 | 80000 | 80000 | 10 | 160041 | 160041 | 160041 | 160057 | 160041 |
160024 | 160040 | 1199 | 0 | 0 | 0 | 0 | 0 | 65 | 0 | 0 | 3 | 160041 | 2 | 12 | 12 | 159690 | 0 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422109 | 22939240 | 1 | 160037 | 0 | 160040 | 160056 | 139697 | 3 | 140020 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160052 | 160040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 0 | 0 | 80039 | 0 | 0 | 0 | 39 | 80035 | 6 | 0 | 39 | 0 | 0 | 5020 | 0 | 0 | 5 | 16 | 4 | 7 | 160053 | 10 | 10 | 0 | 80000 | 80000 | 10 | 160053 | 160057 | 160057 | 160057 | 160057 |
160024 | 160052 | 1199 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 160041 | 2 | 12 | 12 | 159684 | 0 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 421085 | 22938147 | 0 | 160037 | 0 | 160056 | 160056 | 139713 | 3 | 140020 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80039 | 0 | 0 | 0 | 0 | 80039 | 6 | 0 | 35 | 39 | 0 | 5020 | 0 | 0 | 8 | 16 | 4 | 4 | 160103 | 10 | 6 | 4 | 80000 | 80000 | 10 | 160053 | 160091 | 160041 | 160053 | 160041 |
160024 | 160040 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 160041 | 2 | 0 | 12 | 159684 | 12 | 25 | 160012 | 10 | 80000 | 80000 | 10 | 80000 | 80000 | 50 | 421085 | 22938147 | 1 | 160033 | 0 | 160052 | 160056 | 139713 | 3 | 140020 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160061 | 160061 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80019 | 20 | 0 | 0 | 80019 | 1 | 0 | 2 | 21 | 80000 | 6 | 1 | 57 | 42 | 19 | 5020 | 0 | 0 | 8 | 16 | 4 | 3 | 160043 | 9 | 9 | 2 | 80000 | 80000 | 10 | 160062 | 160062 | 160047 | 160047 | 160062 |
160024 | 160061 | 1199 | 1 | 0 | 0 | 0 | 0 | 65 | 1 | 0 | 2 | 160103 | 0 | 18 | 12 | 159684 | 0 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422066 | 22939240 | 1 | 160033 | 0 | 160056 | 160040 | 139697 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80000 | 0 | 0 | 0 | 39 | 80000 | 0 | 1 | 39 | 43 | 0 | 5020 | 0 | 0 | 4 | 16 | 4 | 4 | 160037 | 10 | 6 | 4 | 80000 | 80000 | 10 | 160057 | 160057 | 160106 | 160053 | 160053 |
160024 | 160040 | 1199 | 0 | 0 | 0 | 0 | 0 | 45 | 1 | 0 | 2 | 160037 | 2 | 12 | 12 | 159684 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 421085 | 22938147 | 1 | 160021 | 0 | 160056 | 160056 | 139697 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160040 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80039 | 0 | 0 | 0 | 0 | 80039 | 6 | 1 | 35 | 0 | 0 | 5020 | 0 | 0 | 8 | 16 | 3 | 4 | 160037 | 10 | 6 | 4 | 80000 | 80000 | 10 | 160041 | 160053 | 160053 | 160053 | 160053 |
160024 | 160056 | 1199 | 0 | 0 | 0 | 0 | 0 | 45 | 1 | 0 | 2 | 160031 | 2 | 18 | 18 | 159685 | 15 | 25 | 160012 | 10 | 80004 | 80000 | 10 | 80000 | 80000 | 50 | 422410 | 22940044 | 0 | 160042 | 0 | 160061 | 160061 | 139718 | 3 | 140041 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160040 | 160052 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 39 | 0 | 80000 | 0 | 0 | 0 | 12 | 80039 | 6 | 0 | 35 | 0 | 0 | 5020 | 0 | 0 | 8 | 16 | 3 | 5 | 160103 | 6 | 6 | 2 | 80000 | 80000 | 10 | 160057 | 160057 | 160041 | 160053 | 160053 |