Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1 { v0.s }[1], [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 2.000
Issues: 2.001
Integer unit issues: 0.000
Load/store unit issues: 1.000
SIMD/FP unit issues: 1.001
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 1e | 22 | 24 | 3a | 3f | 46 | 49 | 51 | schedule uop (52) | schedule simd uop (54) | schedule ldst uop (55) | dispatch simd uop (57) | dispatch ldst uop (58) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 5f | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd load (98) | inst ldst (9b) | 9d | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | bb | l1d cache miss ld nonspec (bf) | c2 | cf | d0 | d2 | l1i cache miss demand (d3) | l1i tlb miss demand (d4) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
62005 | 28619 | 214 | 12 | 0 | 10 | 0 | 0 | 0 | 1 | 1 | 0 | 4923 | 28253 | 0 | 0 | 16166 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11917 | 3 | 22720 | 27933 | 28549 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 28439 | 28015 | 1 | 1 | 61001 | 1000 | 1000 | 1 | 1000 | 2 | 1000 | 0 | 0 | 1 | 1000 | 2 | 0 | 0 | 0 | 13506 | 10312 | 7235 | 3529 | 8 | 50 | 19618 | 3418 | 3819 | 20 | 44 | 43 | 27889 | 13817 | 13160 | 13110 | 1000 | 1000 | 28442 | 28110 | 28117 | 28255 | 28157 |
62004 | 28036 | 214 | 14 | 0 | 13 | 0 | 1 | 0 | 2 | 1 | 0 | 5272 | 28281 | 1 | 1 | 16130 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11925 | 9 | 22691 | 27934 | 28467 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 28154 | 28555 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1001 | 0 | 0 | 0 | 1000 | 2 | 1 | 2 | 0 | 13332 | 10367 | 7297 | 3505 | 10 | 46 | 19328 | 3433 | 3812 | 13 | 46 | 39 | 27849 | 15211 | 12298 | 12938 | 1000 | 1000 | 28228 | 28308 | 28047 | 28080 | 28545 |
62004 | 28440 | 211 | 14 | 0 | 10 | 0 | 0 | 0 | 2 | 0 | 0 | 4911 | 28201 | 0 | 0 | 16125 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11904 | 2 | 22665 | 28009 | 28099 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 28265 | 28115 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 2 | 0 | 13799 | 10459 | 7334 | 3524 | 10 | 47 | 19991 | 3434 | 3822 | 20 | 41 | 43 | 27855 | 13768 | 12378 | 13103 | 1000 | 1000 | 28024 | 28056 | 28033 | 28086 | 28478 |
62004 | 28095 | 212 | 17 | 0 | 15 | 0 | 0 | 1 | 2 | 1 | 0 | 5018 | 27940 | 0 | 0 | 16059 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11938 | 1 | 22705 | 27975 | 28034 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 28365 | 28129 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1000 | 0 | 0 | 3 | 1001 | 2 | 0 | 2 | 0 | 13922 | 9857 | 7222 | 3252 | 6 | 48 | 19933 | 3561 | 3811 | 14 | 49 | 49 | 27992 | 13905 | 12227 | 14453 | 1000 | 1000 | 28104 | 28530 | 28173 | 28216 | 28219 |
62004 | 28082 | 214 | 23 | 0 | 14 | 0 | 0 | 0 | 2 | 0 | 0 | 5362 | 27856 | 0 | 0 | 15982 | 2000 | 1001 | 1000 | 1000 | 1000 | 5000 | 11926 | 5 | 22710 | 28357 | 28267 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 28400 | 28689 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1001 | 0 | 0 | 3 | 1000 | 0 | 0 | 2 | 0 | 14191 | 10577 | 7270 | 3254 | 7 | 43 | 20031 | 3423 | 3811 | 12 | 41 | 42 | 27907 | 13816 | 12173 | 13355 | 1000 | 1000 | 27995 | 28536 | 28400 | 28591 | 28038 |
62004 | 28015 | 209 | 14 | 0 | 17 | 0 | 0 | 0 | 2 | 0 | 0 | 5221 | 27861 | 1 | 1 | 16209 | 2001 | 1001 | 1000 | 1000 | 1000 | 5000 | 11924 | 11 | 22712 | 28034 | 28402 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 28154 | 28089 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1001 | 0 | 0 | 4 | 1001 | 2 | 0 | 2 | 0 | 14028 | 9836 | 7277 | 3270 | 4 | 38 | 19870 | 3473 | 3819 | 15 | 43 | 39 | 27996 | 13935 | 12453 | 12823 | 1000 | 1000 | 28512 | 28155 | 28318 | 28185 | 28011 |
62004 | 28483 | 212 | 14 | 0 | 14 | 0 | 0 | 0 | 6 | 1 | 0 | 5273 | 27798 | 0 | 0 | 16469 | 2000 | 1001 | 1000 | 1000 | 1000 | 5000 | 11925 | 5 | 22678 | 27989 | 28117 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 28124 | 28043 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 0 | 1000 | 0 | 0 | 2 | 1000 | 1 | 1 | 1 | 0 | 14103 | 9828 | 7301 | 3498 | 10 | 39 | 19389 | 3495 | 3822 | 14 | 36 | 38 | 27803 | 14715 | 11983 | 13793 | 1000 | 1000 | 28033 | 28135 | 28154 | 28033 | 28022 |
62004 | 28105 | 211 | 11 | 0 | 15 | 0 | 0 | 0 | 2 | 1 | 0 | 5327 | 27846 | 0 | 0 | 16029 | 2002 | 1002 | 1000 | 1000 | 1000 | 5000 | 11931 | 6 | 22732 | 27873 | 27960 | 3 | 10 | 2000 | 1001 | 1000 | 1000 | 2000 | 27994 | 28114 | 2 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1000 | 0 | 0 | 1 | 1001 | 1 | 1 | 2 | 0 | 14084 | 10647 | 7299 | 3529 | 7 | 36 | 19427 | 3482 | 3815 | 14 | 44 | 45 | 27753 | 14188 | 12232 | 12742 | 1000 | 1000 | 28168 | 28000 | 27995 | 28025 | 28030 |
62004 | 28094 | 210 | 10 | 0 | 11 | 0 | 0 | 0 | 2 | 0 | 0 | 5344 | 27893 | 0 | 0 | 16062 | 2000 | 1001 | 1000 | 1000 | 1000 | 5000 | 11929 | 8 | 22714 | 28232 | 28104 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 28442 | 27996 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1001 | 1 | 0 | 0 | 1000 | 2 | 0 | 2 | 0 | 14059 | 10477 | 7156 | 3523 | 5 | 44 | 19541 | 3433 | 3812 | 14 | 44 | 45 | 27838 | 14179 | 12778 | 14412 | 1000 | 1000 | 28075 | 28325 | 28460 | 28103 | 28079 |
62004 | 28048 | 211 | 17 | 0 | 13 | 0 | 0 | 0 | 2 | 0 | 0 | 5318 | 27966 | 0 | 0 | 16223 | 2001 | 1000 | 1000 | 1000 | 1000 | 5000 | 11928 | 8 | 22705 | 28361 | 28043 | 3 | 10 | 2000 | 1000 | 1000 | 1000 | 2000 | 27907 | 28105 | 1 | 1 | 61001 | 1000 | 1000 | 0 | 1000 | 2 | 1000 | 0 | 0 | 0 | 1000 | 2 | 0 | 1 | 0 | 13526 | 10409 | 7231 | 3541 | 6 | 36 | 19531 | 3435 | 3814 | 15 | 43 | 42 | 27812 | 14146 | 12153 | 12807 | 1000 | 1000 | 28069 | 28010 | 28141 | 28082 | 28079 |
Chain cycles: 3
Code:
ld1 { v0.s }[1], [x6] fmov x0, d0 eor x8, x8, x0 eor x8, x8, x0 add x6, x6, x8
mov x0, 1 mov x1, 2 mov x8, 0
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 3 chain cycles): 11.0051
retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 24 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60205 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693734 | 14310939 | 1 | 140030 | 0 | 140051 | 140051 | 131797 | 3 | 132405 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 126 | 1 | 1 | 139559 | 40000 | 10 | 10 | 0 | 10000 | 10000 | 40100 | 140052 | 140036 | 140052 | 140052 | 140052 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140039 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140011 | 0 | 140051 | 140051 | 131797 | 3 | 132403 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140035 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 126 | 1 | 1 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140036 | 140052 |
60204 | 140035 | 1049 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 140020 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14308701 | 1 | 140027 | 3 | 140051 | 140051 | 131797 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 17 | 1 | 1 | 139554 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140052 | 140036 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 1 | 0 | 0 | 140020 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140027 | 0 | 140051 | 140051 | 131797 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 3210 | 1 | 127 | 1 | 1 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140102 | 140052 | 140052 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 40 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70100 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693734 | 14310939 | 1 | 140027 | 0 | 140051 | 140051 | 131797 | 3 | 132580 | 60100 | 30200 | 10000 | 20000 | 60518 | 10159 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 0 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 126 | 1 | 1 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140052 | 140036 |
60204 | 140035 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129347 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140027 | 0 | 140051 | 140051 | 131797 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 126 | 2 | 1 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140517 | 140139 | 140152 | 140052 | 140052 |
60204 | 140248 | 1052 | 1 | 0 | 0 | 0 | 0 | 0 | 88 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140027 | 0 | 140051 | 140051 | 131797 | 3 | 132400 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140035 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 126 | 1 | 1 | 139559 | 40000 | 10 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140052 | 140036 |
60204 | 140051 | 1049 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70100 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1263803 | 6693734 | 14310939 | 1 | 140027 | 0 | 140051 | 140051 | 131797 | 3 | 132399 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140102 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 1 | 1 | 0 | 3210 | 1 | 126 | 1 | 1 | 139559 | 40000 | 0 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140052 | 140052 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70102 | 40100 | 20002 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 1 | 140027 | 0 | 140051 | 140051 | 131793 | 3 | 132423 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10000 | 1 | 10000 | 0 | 0 | 10000 | 0 | 1 | 0 | 3210 | 1 | 126 | 1 | 1 | 139546 | 40000 | 0 | 10 | 10 | 10000 | 10000 | 40100 | 140052 | 140052 | 140052 | 140052 | 140052 |
60204 | 140051 | 1049 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 140036 | 139411 | 129363 | 25 | 70102 | 40100 | 20000 | 10000 | 30100 | 20000 | 10000 | 1264020 | 6693734 | 14310939 | 0 | 140027 | 0 | 140051 | 140051 | 131797 | 3 | 132560 | 60100 | 30200 | 10000 | 20000 | 60200 | 10000 | 30000 | 140051 | 140051 | 1 | 1 | 50201 | 100 | 99 | 100 | 40100 | 10000 | 10000 | 0 | 100 | 10002 | 1 | 10000 | 0 | 0 | 10000 | 1 | 0 | 0 | 3210 | 1 | 126 | 1 | 1 | 139559 | 40000 | 10 | 10 | 0 | 10000 | 10000 | 40100 | 140092 | 140056 | 140038 | 140052 | 140052 |
Result (median cycles for code, minus 3 chain cycles): 11.0047
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3f | 4d | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6b | 6d | 6e | map stall dispatch (70) | int prf full (71) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | l1d cache miss ld nonspec (bf) | c2 | branch cond mispred nonspec (c5) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
60025 | 140047 | 1048 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 140032 | 139394 | 129359 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6693538 | 14325829 | 0 | 140023 | 0 | 140047 | 140048 | 131815 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 4 | 113 | 2 | 2 | 139566 | 40000 | 0 | 6 | 6 | 10000 | 10000 | 40010 | 140048 | 140048 | 140048 | 140048 | 140048 |
60024 | 140047 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 140032 | 139394 | 129359 | 25 | 70012 | 40035 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6693538 | 14325829 | 0 | 140316 | 0 | 140047 | 140047 | 131815 | 0 | 3 | 132430 | 60010 | 30663 | 10000 | 20000 | 60020 | 10000 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 1 | 2 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 113 | 2 | 2 | 139566 | 40000 | 6 | 6 | 6 | 10000 | 10000 | 40010 | 140048 | 140048 | 140048 | 140048 | 140048 |
60024 | 140047 | 1049 | 0 | 0 | 0 | 1 | 1 | 2 | 0 | 1 | 0 | 1 | 0 | 140032 | 139394 | 129359 | 25 | 70012 | 40010 | 20002 | 10005 | 30010 | 20000 | 10000 | 1264443 | 6693538 | 14325829 | 0 | 140023 | 0 | 140047 | 140047 | 131815 | 0 | 3 | 132521 | 60010 | 30020 | 10000 | 20000 | 60020 | 10215 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 111 | 2 | 2 | 139567 | 40000 | 6 | 6 | 9 | 10000 | 10000 | 40010 | 140051 | 140337 | 140051 | 140048 | 140051 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 140032 | 139394 | 129359 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264452 | 6693538 | 14339627 | 0 | 140023 | 0 | 140047 | 140047 | 131815 | 0 | 3 | 132598 | 60010 | 30342 | 10107 | 20428 | 60020 | 10000 | 30000 | 140048 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 2 | 2 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 113 | 2 | 2 | 139566 | 40000 | 6 | 6 | 6 | 10000 | 10000 | 40010 | 140048 | 140048 | 140048 | 140036 | 140051 |
60024 | 140047 | 1049 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 140032 | 139394 | 129405 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6693538 | 14325829 | 0 | 140023 | 0 | 140047 | 140047 | 131815 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30161 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3168 | 2 | 113 | 2 | 2 | 139566 | 40000 | 6 | 6 | 9 | 10000 | 10000 | 40010 | 140048 | 140048 | 140048 | 140051 | 140048 |
60024 | 140054 | 1048 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 140032 | 139394 | 129347 | 25 | 70010 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264477 | 6693538 | 14325829 | 0 | 140011 | 0 | 140035 | 140047 | 131818 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10054 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 1 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 113 | 2 | 2 | 139623 | 40000 | 6 | 6 | 0 | 10000 | 10000 | 40010 | 140048 | 140048 | 140048 | 140048 | 140048 |
60024 | 140047 | 1049 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 140032 | 139394 | 129359 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20105 | 10000 | 1264477 | 6693538 | 14325829 | 0 | 140023 | 0 | 140047 | 140048 | 131815 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 0 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 113 | 2 | 2 | 139619 | 40000 | 6 | 6 | 6 | 10000 | 10000 | 40010 | 140048 | 140048 | 140048 | 140048 | 140048 |
60024 | 140050 | 1049 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 13 | 0 | 1 | 0 | 140032 | 139394 | 129359 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20108 | 10000 | 1264443 | 6693538 | 14325829 | 0 | 140023 | 0 | 140047 | 140047 | 131815 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 1 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 113 | 2 | 2 | 139566 | 40000 | 6 | 6 | 6 | 10000 | 10000 | 40010 | 140048 | 140036 | 140048 | 140051 | 140048 |
60024 | 140047 | 1049 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 140032 | 139395 | 129360 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6692947 | 14325829 | 0 | 140024 | 0 | 140035 | 140047 | 131815 | 0 | 3 | 132420 | 60010 | 30020 | 10000 | 20000 | 60344 | 10000 | 30000 | 140047 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 0 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 1 | 1 | 0 | 0 | 3140 | 2 | 113 | 2 | 2 | 139566 | 40000 | 6 | 6 | 6 | 10000 | 10000 | 40010 | 140036 | 140051 | 140048 | 140048 | 140048 |
60024 | 140047 | 1049 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 140032 | 139394 | 129359 | 25 | 70012 | 40010 | 20002 | 10000 | 30010 | 20000 | 10000 | 1264443 | 6692947 | 14325829 | 0 | 140023 | 0 | 140047 | 140035 | 131815 | 0 | 3 | 132430 | 60010 | 30020 | 10000 | 20000 | 60020 | 10000 | 30000 | 140048 | 140047 | 1 | 1 | 50021 | 10 | 9 | 10 | 40010 | 10000 | 10000 | 1 | 10 | 10000 | 0 | 1 | 10000 | 0 | 0 | 0 | 10000 | 0 | 1 | 0 | 0 | 3140 | 2 | 113 | 2 | 2 | 139569 | 40000 | 0 | 6 | 6 | 10000 | 10000 | 40010 | 140048 | 140048 | 140051 | 140036 | 140048 |
Count: 8
Code:
ld1 { v0.s }[1], [x6] ld1 { v0.s }[1], [x6] ld1 { v0.s }[1], [x6] ld1 { v0.s }[1], [x6] ld1 { v0.s }[1], [x6] ld1 { v0.s }[1], [x6] ld1 { v0.s }[1], [x6] ld1 { v0.s }[1], [x6]
mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 2.0007
retire uop (01) | cycle (02) | 03 | l1d tlb fill (05) | 09 | l2 tlb miss data (0b) | 0e | 0f | 18 | 19 | 1e | 1f | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4e | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160205 | 160056 | 1199 | 0 | 1 | 0 | 2 | 0 | 0 | 0 | 57 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421998 | 22939559 | 1 | 160037 | 160056 | 160056 | 139691 | 3 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160053 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 160057 | 160057 | 160057 | 160057 | 160057 |
160204 | 160056 | 1198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421998 | 22939547 | 1 | 160037 | 160056 | 160056 | 139691 | 3 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80130 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160053 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 160057 | 160057 | 160057 | 160057 | 160057 |
160204 | 160056 | 1200 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 504 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 9 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421017 | 22939547 | 1 | 160037 | 160056 | 160056 | 139691 | 3 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 1 | 100 | 80000 | 0 | 43 | 0 | 80039 | 1 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160133 | 2 | 10 | 10 | 4 | 80000 | 80000 | 100 | 160426 | 160181 | 160289 | 160120 | 160057 |
160204 | 160056 | 1198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 12 | 159690 | 16 | 25 | 160100 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 421998 | 22941088 | 1 | 160037 | 160056 | 160056 | 139691 | 3 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 298 | 80039 | 0 | 0 | 42 | 80169 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160053 | 0 | 0 | 10 | 4 | 80000 | 80000 | 100 | 160057 | 160057 | 160057 | 160057 | 160057 |
160204 | 160056 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 422041 | 22939575 | 1 | 160037 | 160056 | 160056 | 139691 | 3 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 2 | 0 | 46 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160053 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 160057 | 160057 | 160057 | 160057 | 160057 |
160204 | 160056 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 422028 | 22939547 | 1 | 160037 | 160056 | 160056 | 139691 | 3 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160037 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 160057 | 160057 | 160057 | 160057 | 160041 |
160204 | 160056 | 1198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 511 | 422041 | 22939575 | 1 | 160037 | 160056 | 160056 | 139691 | 18 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80000 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160053 | 0 | 0 | 10 | 0 | 80000 | 80000 | 100 | 160057 | 160041 | 160057 | 160041 | 160057 |
160204 | 160056 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 160025 | 2 | 12 | 12 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 422028 | 22939559 | 1 | 160037 | 160056 | 160056 | 139691 | 3 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160053 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 160057 | 160057 | 160041 | 160057 | 160057 |
160204 | 160056 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 0 | 160025 | 2 | 12 | 12 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80000 | 80000 | 500 | 422028 | 22939547 | 1 | 160037 | 160056 | 160056 | 139691 | 17 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160040 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 1 | 100 | 80000 | 0 | 43 | 0 | 80039 | 0 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 1 | 5110 | 2 | 16 | 2 | 2 | 160053 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 160057 | 160057 | 160057 | 160057 | 160057 |
160204 | 160056 | 1198 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 45 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 16 | 25 | 160102 | 100 | 80002 | 80000 | 100 | 80150 | 80000 | 500 | 422041 | 22939547 | 0 | 160021 | 160056 | 160056 | 139691 | 3 | 140014 | 160100 | 200 | 80000 | 80000 | 200 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80201 | 100 | 99 | 100 | 100 | 80000 | 80000 | 0 | 100 | 80000 | 0 | 43 | 0 | 80039 | 1 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 0 | 5110 | 2 | 16 | 2 | 2 | 160053 | 0 | 10 | 10 | 4 | 80000 | 80000 | 100 | 160057 | 160057 | 160057 | 160057 | 160057 |
Result (median cycles for code divided by count): 2.0007
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 0e | 0f | 18 | 1e | 1f | 22 | 23 | 3a | 3f | 43 | 46 | 49 | 4e | 4f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd load (98) | inst ldst (9b) | 9d | 9f | l1d tlb access (a0) | l1d cache miss ld (a3) | a5 | ld unit uop (a6) | l1d cache writeback (a8) | ac | af | b5 | b6 | bb | l1d cache miss ld nonspec (bf) | c2 | branch cond mispred nonspec (c5) | cf | d2 | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ea | eb | ec | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160025 | 160056 | 1199 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 44 | 0 | 1 | 0 | 1 | 160041 | 2 | 1 | 12 | 159690 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422394 | 22939547 | 0 | 160037 | 160056 | 160060 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 1 | 10 | 80000 | 43 | 0 | 80039 | 0 | 40 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 5020 | 0 | 18 | 16 | 8 | 11 | 160053 | 10 | 10 | 4 | 80000 | 80000 | 10 | 160057 | 160057 | 160057 | 160041 | 160057 |
160024 | 160060 | 1199 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 19 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422841 | 22939575 | 1 | 160037 | 160056 | 160056 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 0 | 80039 | 0 | 38 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 5020 | 0 | 6 | 16 | 11 | 8 | 160053 | 10 | 10 | 4 | 80000 | 80000 | 10 | 160061 | 160057 | 160057 | 160057 | 160057 |
160024 | 160056 | 1198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 160045 | 2 | 1 | 12 | 159684 | 19 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422419 | 22946559 | 1 | 160037 | 160040 | 160056 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 0 | 80039 | 2 | 42 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 5020 | 0 | 11 | 16 | 11 | 8 | 160053 | 10 | 10 | 4 | 80000 | 80000 | 10 | 160041 | 160057 | 160057 | 160057 | 160061 |
160024 | 160056 | 1199 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 160534 | 2 | 12 | 0 | 159684 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422599 | 22939575 | 0 | 160037 | 160056 | 160060 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160040 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 0 | 80038 | 0 | 38 | 80039 | 6 | 1 | 0 | 43 | 0 | 0 | 5020 | 0 | 14 | 16 | 10 | 6 | 160057 | 10 | 10 | 0 | 80000 | 80000 | 10 | 160057 | 160057 | 160057 | 160057 | 160057 |
160024 | 160040 | 1199 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 57 | 0 | 0 | 0 | 0 | 160045 | 2 | 12 | 12 | 159684 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422113 | 22939575 | 0 | 160037 | 160060 | 160056 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160040 | 160060 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 0 | 80039 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 5020 | 0 | 9 | 16 | 9 | 10 | 160053 | 10 | 10 | 4 | 80000 | 80000 | 10 | 160061 | 160057 | 160057 | 160057 | 160041 |
160024 | 160056 | 1199 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 44 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 1 | 159684 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422509 | 22939547 | 0 | 160037 | 160056 | 160056 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 0 | 0 | 80039 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 2 | 0 | 5020 | 0 | 9 | 16 | 8 | 11 | 160135 | 10 | 10 | 4 | 80000 | 80000 | 10 | 160057 | 160057 | 160246 | 160057 | 160119 |
160024 | 160056 | 1198 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 45 | 686 | 0 | 0 | 1 | 160025 | 2 | 1 | 12 | 159478 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422419 | 22939547 | 0 | 160037 | 160056 | 160056 | 139717 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 0 | 80039 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 5020 | 0 | 9 | 16 | 9 | 9 | 160053 | 14 | 14 | 4 | 80000 | 80000 | 10 | 160057 | 160057 | 160061 | 160057 | 160057 |
160024 | 160056 | 1199 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 160041 | 2 | 12 | 1 | 159684 | 19 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422118 | 22948297 | 0 | 160037 | 160056 | 160056 | 139713 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 0 | 80038 | 0 | 39 | 80040 | 6 | 0 | 39 | 43 | 0 | 0 | 5020 | 0 | 8 | 16 | 8 | 11 | 160053 | 10 | 0 | 4 | 80000 | 80000 | 10 | 160057 | 160057 | 160057 | 160057 | 160061 |
160024 | 160056 | 1198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 45 | 0 | 0 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 19 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422619 | 22939559 | 1 | 160037 | 160040 | 160056 | 139713 | 3 | 140040 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 0 | 80038 | 0 | 39 | 80039 | 6 | 1 | 38 | 43 | 0 | 1 | 5020 | 3 | 12 | 16 | 7 | 9 | 160053 | 14 | 14 | 4 | 80000 | 80000 | 10 | 160057 | 160057 | 160057 | 160057 | 160061 |
160024 | 160056 | 1199 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 60 | 0 | 1 | 0 | 1 | 160041 | 2 | 12 | 12 | 159684 | 16 | 25 | 160012 | 10 | 80002 | 80000 | 10 | 80000 | 80000 | 50 | 422384 | 22939547 | 1 | 160037 | 160056 | 160056 | 139717 | 3 | 140036 | 160010 | 20 | 80000 | 80000 | 20 | 80000 | 160000 | 160056 | 160056 | 1 | 1 | 80021 | 10 | 9 | 10 | 10 | 80000 | 80000 | 0 | 10 | 80000 | 43 | 0 | 80038 | 0 | 39 | 80039 | 6 | 1 | 39 | 43 | 0 | 0 | 5041 | 0 | 8 | 16 | 9 | 9 | 160037 | 14 | 10 | 4 | 80000 | 80000 | 10 | 160107 | 160057 | 160061 | 160057 | 160057 |