Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (single, post-index, S)

Test 1: uops

Code:

  ld1 { v0.s }[1], [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.002

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e22243a3f43464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5e5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)91inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2c9cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
62005289922341230230000040046972845711016851300210001001100010001000100050005000119900162257428639289633103000100010002000200028714286761161001010001000010000010010021002210001310995326969313095420199316237991443492825610001569012657136431000100010002868228766286842866628754
620042878523202002000000400475228393100168153002100010011000100010001000500050001195301822600285882869631030001000100020002000287182863811610010100010001100004100200110022200013133932669453081105220189320738062249502833110001566112458136341000100010002882428776289522875128732
6200428784233023021000001004683285011021671030011000100210001000100010005000500011952072257528632287813103000100010002000200028716286261161001010001000010000410020011001023001324594326910320984720114321738091149512821410001553712715137991000100010002879428850288572883928895
62004287982320230190010030047362842721016955300210001002100010001000100050005000119290622699288102878531030001000100020002000288012866211610010100010000100004100210210032130013341940269203156124620282324738111345482829110001551012648139451000100010002887628828287572877528710
62004287042320240250000040045572855111216868300210001001100010001000100050005000119610422604287062880431030001000100020002000287872871711610010100010000100004100200510022230013141933768743188124420325329838091351512831110001553412364141391000100010002900228821287562886428927
6200428978232011018000004104725283501121676030011000100210001000100010005000500011969082260328752289243103000100010002000200028771287311161001010001000010000410022021002230001320394976911312785120232319338081845472822210001554612629141051000100010002880328947289192886228965
62004288062310220170110040047762842910016782300110001002100010001000100050005000119770522647286772887031030001000100020002000287902869511610010100010000100000100100110012130012991952269303138134620209324938141347472821110001555812861140771000100010002870128945288282890328827
6200428872231023021010004004878283941011679330021000100210001000100010005000500011949072261828568289153103000100010002000200028816286771161001010001000110000310030011002210001338793596887315774520257327038161541532810610001563212607140761000100010002889928851287522874928781
62004288592320210210100020048002840810116786300210001002100010001000100050005000119500522634286352887431030001000100020002000287902864611610010100010000100003100100110012130961311494456970309185220245327938101151482816010001564012644140281000100010002881728840287262869528855
6200428862231028020000003004752283871011671830021000100210001000100010005000500011963082265828731286643103000100010002000200028743288081161001010001000010000410010021001212001319192516952316254520066323338112145412836110001573412545138631000100010002889728926288812885628770

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.s }[1], [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

retire uop (01)cycle (02)03l1d tlb fill (05)l2 tlb miss data (0b)0e0f18191e1f233a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
602051400471086000100130001400371395712580102501002000210000401002000010000124563753045651071021001400260140050140035131949313243170100302001000020000602002000030000140036140047115020110099100401001000010000110010000001000000010000001000032331931113971450000999100001000050100140036140051140036140051140051
60204140050108500000010001400351395712580102501002000210000401002000010000124562553044871071021001400260140050140050131964313243170100302001000020000604422000030000140049140047115020110099100401001000010000010010000011000010010000101001032101931113971450000960100001000050100140051140051140051140146140051
60204140050108600100010001400351395562580102501002000010000401002000010000124560753039271071021001400260140050140050131964313242870361304471000020000602002000030242140051140050115020110099100401001000010000010010000011000300010000101000032101931113971950010969100001000050100140054140051140053140143140053
60204140050108600000010001401311396152580102501002000010000401002000010000124560753039271071021001400690140050140050131949313243070360302001000020000602002000030000140035140050115020110099100401001000010000010010000001000010310001101000032101931113971450000999100001000050100140150140036140052140051140036
6020414005010860001000000140062139559258010250109200001000040100200001003812456115304487107102100140026014005014005013196415132434701003020010000200006020020000300001401411400471150201100991004010010000100000100100000110000100100001010000321011461113971450000969100001000050100140053140048140051140051140048
6020414005210850011001300014003913957125801025010020003100404605221897100401245637530448710709276014001101400501400501319493132416701003020010000200006020020000300001401221400351150201100991004010010000100000100100000110000003100000010000321011081113969950000966100001000050100140054140048140051140225140051
60204140050108600110010001400371395712580102501002000010000401002007910000124563753044111071021001400110140035140035131961313243170100302001000020000602002000030000140140140050115020110099100401001000010000010010000011000030010000100000032101931113969950000907100001000050100140036140051140054140052140051
60204140050108600000010001400381395732580102501122000210000401002000010000124563753045651071021001400260140050140052131966313243170100302001000020080602002000030000140038140047215020110099100401001000010000010010001111000100110000110110032101931113980750000909100001000050100140042140057140057140134140057
6020414005610861000101400014004213957725801045010020004100014010020000100001245607530448710709276014002301400501400501319613132432701003020010040200006020020000300001400501400481150201100991004010010000100000100100000110000203175100011010200328111211313991550020999100001000050100140322140215140410140241140230
6020414031610880100242652640014030513968977801315013120011100024052320319100391254409531090110715160014023601403351402221320354713246370882303261000020000602002000030000140047140050115020110099100401001000010000110010000011000000010000101000032101931113971450000969100001000050100140051140036140051140051140051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f23243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2c3branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
600251400471125000010003000014003913965425800125001020002100004001020000100001245753530692210717109014002301400501400501319983132456759763002010000200006002020000300001400351400481150021109104001010000100000101000001100000001000111400003140003884413972250000999100001000050010140051140051140051140051140051
6002414005011250000000048800014003713963925800105001020002100004015120000100001245788530750410717109014002601400501400471319863132455700103002010000200006002020082300001404831403901150021109104001010000100000101000101100030001000011000003140004884413972250000969100001000050010140054140053140051140051140051
6002414004711240000100015000014003713963925800125001020002100004001020000100001248705530739010717343014002931400501400531319973132443700103002010000208066860020564300001400501400351150021109104001010000100000101000001100000001000001000003140003883313972250000696100001000050010140051140052140052140048140051
600241401431125000001001000014002113965625800125001020000100004001020000100001245788530754210717109014002601400501400501319953132458700103002010000200006002020000300001400511400831150021109104001010000100000101000001100001001000011000003140003883313972150000990100001000050010140051140051140048140051140053
6002414005311240000000016000014003313963925800125001020002100004001020000100001245788530750410717109014002301400501400501319983132458700103002010000200006002020000300001400501400541150021109104001010000100000101000100100000001000010000003140004884413971850000909100001000050010140048140051140048140036140051
6002414005011250000000040000140037139639258001250010200021000040010200001000012457885307504107164790140033314005014005013199831324587001030020100002000060020200003000014005114004711500211091040010100001000001010000011000020010000110000031400038833139723500001100100001000050010140051140051140051140036140050
6002414005011250000000021000014004213965425800125001020002100004001020000100001245761530758210717109014002701400471400471319983132458700103002010000200006002020000300001400381400501150021109104001010000100000101000001100002001000011000003140003884413972150000969100001000050010140051140051140051140051140036
600241400931125000000001360000140041139654258001250010200001000140010200001000012457885306922107171090140023014005014005013199831324587001030020100002000060020200003000014003514004711500211091040010100001000001010000011000000310000110000131400048844139721500009612100001000050010140051140051140051140048140052
6002414005111240000000018800014003213965425800125001020002100004015220000100001245788530739010717109014002301400501400351319993132458700103002010000200006002020000300001400501400471150021109104001010000100000101000101100020001000011000003140003884413970650000069100001000050010140048140051140051140051140051
600241400351125000000007001014003313965425800125001020002100014001020000100001245788530890010717341014001101400501400501319983132459700103002010000200806002020000300001400551400471150021109104001010000100000101000001100000001000011000003164004883313972250000999100001000050010140051140051140054140051140052

Test 3: throughput

Count: 8

Code:

  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  ld1 { v0.s }[1], [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfl1i cache miss demand (d3)d5map dispatch bubble (d6)dadbddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020516005612850010110029000001600441661595587252401028010080002800008010080152800005307745289582293609101600401600591600591396940314001724057220080000800002001600001600001600591600561180201100991001008000080000110080000020080017002178001761172305110011600111600561800001010800008000080100160060160061160060160060160057
1602041600591285000100003000000160044160159590725240102801008000080000801008000080000530934529153229360910160040160059160059139694031400202401002008000080000200160000160000160059160056118020110099100100800008000001008000001908001501015801456114190511001160011160056180000010800008000080100160060160057160060160060160057
16020416012712860010000030000001600441061595966252401028010080014800008010080000800005317265290302293609101600601600401600561396780314004024010020280000800002001600001600001600401600571180201100991001008000080000010080000019080149000238001561152105110011600111600560800001410800008000080100160060160041160131160060160057
16020416006012860000000149000001600450661595965252401028010080002800008010080000800005309545298082293609101600791600591600591396940314001724057220080000800002001600001600001600561600561180201100991001008000080000010080000221080015012380017611600511001160011160057180000013800008000080100160060160060160041160060160057
160204160056128500000000290000016004406615959672524010280100800028000080100800008000053172652906422936091016004016004016005913969403140017240100200800008000020016000016000016005916005911802011009910010080000800000100800000008001600020798001661152105110011600211600370800001313800008000080100160057160057160060160060160057
16020416005612850010010026000001600441661595967252404078010080002800008010080000800005307905290302293669501600371600561600571396910314001724010020080000800002001600001600001601301600401180201100991001008000080000010080000021080016010158001761152105110011600111600580800001010800008000080100160060160057160060160060160057
16020416005912860000000026000001600441661595965252401028010080002801308010080000800005307745290302293194901600401600561600561396919314001424010020080000800002001600001600001600591600561180201100991001008000080000010080000005980015000198001761142305110011600111600530800001313800008000080100160057160132160060160057160057
160204160059128600000100255000001600611661594560252401028026080002802608010080152800005431945298012292881101600401600591601821396811131400392401002008016480000202160000160328160059160126118020110099100100800008000001008000001908014600020958001561142105130011600111600561801601313800008000080100160132160041160131160060160129
160204160198128500000001348800001601151061594606252404078010080014800008026080000801635307825422882293229901601151602701603401394843677140100241988200818008618720216124016065416041216018451802011009910010080000800000100801300191788027711262068040761021051510428600421602160804801013800008000080100160254160342160267160271160271
160204160253128800010000340000016004416615959672524010280100800028000080100800008000053079052903122936091016004016005916005913969403140018240100200800008000020016000016000016005916005611802011009910010080000800000100800000190800170002080017011421251101511600711600531800001010800008000080100160060160060160060160057160060

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f2223243f4346494e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160025160061124000010001900001600461601596008252400148001080004800008001080000800005303775298562292028416003601603341600551396840314003324001020800008000020160000160000160055160053118002110910108000080000010800000008001300013800196110170000050205165416005208000096800008000080010160056160041160056160041160056
1600241600531241101000031000016004606615960010252400148001080004800008001080000800005303775293652293544816003601600551600551397120314003524001020800008000020160000160000160055160053118002110910108000080000010800000008000000012800180113170000050205164416005208000099800008000080010160056160056160060160056160041
1600241600551241000110015010016004016615958852524001280010800028000080010800008000054385152973822935452160090016005516005313971203014003524001020800008000020160000160000160053160053118002110910108000080000010800000008001300098000960101400000502051655160037180000139800008000080010160056160041160056160041160056
1600241600531240000000019000016004016615958462524001280010800028000080010800008000053078552978522935460160036016005516004013971203140035240010208000080000201600001600001600551600531180021109101080000800000108000001708001500013800106010170000050205164516005318000090800008000080010160056160041160041160056160056
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