Firestorm: LD2R (1D) measurements

Code:

  ld2r { v0.1d, v1.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.008

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	24	3a	3f	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	28719	214	2	1	0	1	1	1	1	0	0	4	1	0	5138	27988	1	1	16238	3008	2008	1000	2000	1000	5000	23886	3	0	5	22719	28203	28183	3	10	3000	1000	2000	1000	2000	28055	27987	1	1	61001	1000	1000	0	1002	1	3	1004	1	3	1	1001	2	2	3	1	1	14044	10105	7283	3304	45	19530	3465	3813	10	33	41	27866	14671	12447	13099	1000	2000	28221	28333	28150	28309	28216
63004	28381	210	0	1	0	1	0	0	1	0	0	4	1	0	5218	27926	1	1	16003	3008	2008	1000	2000	1000	5000	23869	4	1	8	22756	28090	28158	3	10	3000	1000	2000	1000	2000	28164	28269	1	1	61001	1000	1000	0	1003	3	3	1005	0	2	2	1001	2	2	3	1	0	14071	10513	7319	3527	28	19580	3399	3816	13	37	37	27780	14310	12436	12916	1000	2000	28397	28192	28129	28107	28117
63004	28356	211	0	1	0	1	0	0	1	0	0	4	1	0	5301	27866	0	0	16298	3006	2008	1000	2000	1000	5000	23856	5	1	0	22762	28204	28290	3	10	3000	1000	2000	1000	2000	28099	28168	1	1	61001	1000	1000	0	1003	3	3	1003	0	2	2	1000	2	2	2	1	2	13694	10430	7291	3412	37	19496	3318	3814	13	40	35	27837	13818	12590	13191	1000	2000	28574	28378	28180	28184	28242
63004	28072	213	0	1	0	1	0	0	1	0	0	4	1	0	5251	27983	1	0	16232	3008	2008	1000	2000	1000	5000	23886	3	0	9	22779	28142	28197	3	10	3000	1000	2000	1000	2000	28318	28135	1	1	61001	1000	1000	0	1002	2	3	1003	1	1	2	1001	2	2	3	1	2	13559	10357	7384	3513	34	19477	3430	3819	17	39	39	27812	14274	12431	13527	1000	2000	28222	28245	28276	28105	28025
63004	28124	209	0	1	0	1	0	0	1	0	0	4	1	0	5145	28027	0	1	16221	3008	2008	1000	2000	1000	5000	23896	4	1	8	22782	28095	28343	3	10	3000	1000	2000	1000	2000	28111	28174	1	1	61001	1000	1000	0	1004	3	3	1003	0	1	1	1000	2	2	3	1	0	13755	10424	7037	3557	37	19573	3389	3820	12	41	37	27814	14150	12849	13536	1000	2000	28344	28415	28335	28309	28497
63004	28293	211	0	1	0	0	0	0	1	0	0	4	1	0	5041	28001	1	0	16087	3006	2008	1000	2000	1000	5000	23888	4	0	8	22728	28123	28571	3	10	3003	1000	2000	1000	2000	28098	28255	1	1	61001	1000	1000	0	1001	3	3	1003	2	2	1	1000	2	2	3	1	2	13618	10147	7247	3473	36	19498	3341	3816	11	39	40	27896	14024	12576	12882	1000	2000	28489	28259	28196	28414	28224
63004	28272	211	0	1	0	1	0	0	1	0	0	2	1	0	5046	27990	1	0	16212	3008	2008	1000	2000	1000	5000	23888	4	0	0	22764	27996	28207	3	10	3000	1000	2000	1000	2000	28026	28207	1	1	61001	1000	1000	0	1001	3	3	1002	0	2	2	1001	1	2	3	1	2	13708	9997	7259	3484	41	19348	3400	3822	14	42	38	27804	14839	12407	14103	1000	2000	28337	28314	28341	28313	28105
63004	28149	211	0	1	0	1	0	0	1	0	0	3	1	0	5115	27954	0	1	16023	3008	2008	1000	2000	1000	5000	23890	3	1	9	22753	27995	28123	3	10	3000	1000	2000	1000	2000	28293	28068	1	1	61001	1000	1000	0	1003	3	2	1005	0	0	2	1001	2	2	1	1	2	14257	10318	7205	3354	36	19453	3458	3819	13	34	38	27879	14141	12543	13022	1000	2000	28345	28290	28134	28318	28083
63004	28191	214	1	1	0	1	0	0	0	0	0	4	1	0	5127	27885	1	1	15904	3008	2008	1000	2000	1000	5000	23872	0	0	8	22808	28024	28057	3	10	3000	1000	2000	1000	2000	28417	28333	1	1	61001	1000	1000	0	1003	2	3	1002	0	2	1	1001	1	2	3	1	2	14055	10145	7201	3267	32	19490	3430	3812	10	41	36	27848	14905	12920	12921	1000	2000	28596	28325	28191	28229	28283
63004	28048	211	1	1	0	1	0	0	1	0	0	4	0	0	5204	28116	0	1	16188	3008	2004	1000	2000	1000	5000	23886	4	1	8	22814	28005	28040	3	10	3000	1000	2000	1000	2000	28297	28194	1	1	61001	1000	1000	1	1003	3	3	1003	0	2	1	1001	2	2	3	1	2	13792	10405	7252	3231	38	19478	3514	3817	15	43	41	27796	14202	12306	13381	1000	2000	28454	28316	28246	28463	28150

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.1d, v1.1d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140035	1049	0	0	0	0	0	0	0	0	0	0	0	140020	139431	139338	129341	25	80100	40100	30000	10000	30100	30000	10000	1264328	6692791	20081263	1	140011	0	140047	140047	130531	0	3	131118	70100	30200	10000	30000	60200	10000	30000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3246	2	128	2	1	139544	40000	9	0	0	10000	20000	40100	140054	140051	140052	140051	140051
70204	140050	1049	0	0	0	0	0	0	0	0	0	0	0	140035	139534	139325	129341	25	80103	40100	30003	10000	30100	30000	10000	1264342	6692791	20079451	0	140027	0	140050	140050	130558	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140050	140047	1	1	50202	100	99	100	40100	10000	10000	1	100	10000	0	1	10001	0	0	0	10000	1	1	0	0	0	3210	2	153	1	2	139563	40000	0	0	0	10000	20000	40100	140051	140036	140051	140036	140051
70204	140053	1049	0	0	0	0	0	0	13	0	1	0	0	140035	139404	139325	129341	25	80103	40100	30000	10000	30100	30000	10000	1264310	6693535	20081263	1	140023	0	140047	140052	130566	0	3	131146	70100	30200	10000	30000	60200	10000	30000	140047	140051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3210	2	128	2	2	139544	40000	9	6	9	10000	20000	40100	140070	140055	140051	140051	140060
70204	140050	1049	0	0	0	0	0	0	1	0	1	0	0	140082	139534	139343	129356	25	80100	40100	30003	10000	30100	30000	10000	1264319	6693679	20081697	1	140026	0	140035	140035	130558	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140050	140035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	55	0	3	10000	1	1	0	0	0	3210	2	128	1	2	139559	40000	9	0	9	10000	20000	40100	140051	140048	140048	140048	140051
70204	140035	1049	0	0	0	1	0	0	0	0	0	0	0	140020	139534	139325	129356	25	80103	40100	30000	10000	30100	30000	10000	1264319	6693535	20079451	1	140026	0	140050	140050	130558	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	4	10000	0	0	0	0	0	3210	1	128	2	2	139544	40000	0	0	9	10000	20000	40100	140056	140051	140051	140049	140051
70204	140050	1049	0	0	1	1	0	0	0	0	0	0	0	140020	139431	139338	129353	25	80103	40100	30000	10000	30100	30000	10000	1264310	6693535	20081697	1	140026	0	140035	140050	130531	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140047	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	1	3210	1	128	1	2	139563	40000	9	9	9	10000	20000	40100	140140	140061	140048	140048	140051
70204	140035	1049	0	0	0	0	0	0	6	0	0	0	0	140035	139431	139338	129353	25	80103	40100	30003	10000	30100	30000	10000	1264328	6692791	20079451	0	140023	0	140047	140047	130543	0	3	131126	70465	30200	10000	30000	60200	10000	30000	140050	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3210	2	153	2	2	139563	40000	6	6	0	10000	20000	40100	140051	140051	140036	140051	140036
70204	140050	1049	0	0	0	0	0	0	1	0	0	0	0	140020	139534	139325	129356	25	80103	40100	30003	10000	30100	30000	10000	1264342	6692791	20081697	1	140023	0	140050	140047	130558	0	3	131146	70100	30200	10000	30195	60200	10000	30000	140050	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	3210	1	153	2	2	139560	40000	6	6	6	10000	20000	40100	140048	140048	140048	140036	140048
70204	140047	1048	0	0	0	0	0	0	1	0	1	0	0	140032	139404	139338	129353	25	80103	40100	30003	10000	30100	30167	10000	1264328	6693388	20079451	1	140023	0	140047	140035	130531	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140050	140042	1	1	50201	100	99	100	40100	10000	10000	1	100	10025	4	1	10029	2	0	0	10006	1	1	0	0	0	3701	4	321	2	2	139544	40166	0	0	0	10000	20000	40100	140137	140051	140051	140037	140051
70204	140050	1049	1	0	0	0	0	0	13	0	0	0	0	140035	139434	139351	129356	25	80103	40100	30000	10000	30100	30000	10000	1264342	6693535	20079451	1	140026	0	140050	140035	130558	0	3	131146	70100	30200	10000	30000	60200	10000	30000	140050	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	3210	2	128	2	2	139544	40000	0	9	0	10000	20000	40100	140051	140036	140048	140048	140051

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140051	1049	0	0	0	0	0	0	0	0	1	0	0	0	0	140039	139564	139344	129360	25	80010	40010	30003	10000	30010	30000	10000	1264819	6693731	20081843	0	0	140030	140054	140054	130625	3	131176	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	2	1	10000	0	0	0	3	10001	1	1	0	0	3140	0	4	120	2	3	139576	40000	0	0	18	10000	20000	40010	140036	140057	140433	140052	140036
70024	140035	1049	0	0	0	0	1	1	0	0	1	0	1	0	0	140039	139584	139346	129360	25	80010	40010	30003	10005	30010	30000	10000	1264819	6692791	20079451	0	0	140030	140054	140035	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	15	10000	1	1	0	0	3140	0	2	120	2	2	139576	40000	13	0	10	10000	20000	40010	140052	140055	140055	140055	140036
70024	140054	1049	0	1	0	0	1	0	0	0	1	0	0	0	0	140039	139564	139346	129363	25	80010	40010	30000	10000	30010	30000	10000	1264819	6693731	20082304	0	0	140030	140051	140052	130553	3	131161	70010	30020	10000	30000	60020	10000	30000	140054	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	4	1	10000	0	0	0	3	10000	0	1	0	0	3140	0	2	121	2	4	139576	40000	13	0	10	10000	20000	40010	140036	140036	140036	140055	140055
70024	140051	1049	0	0	0	1	1	0	0	0	12	0	0	0	0	140039	139564	139325	129360	25	80010	40010	30000	10000	30010	30000	10000	1264719	6692791	20081843	0	0	140027	140054	140035	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	2	1	10000	0	1	0	0	10000	1	1	0	0	3140	0	2	121	2	2	139653	40035	13	13	10	10000	20000	40010	140441	140279	140265	140233	140356
70024	140054	1049	0	0	0	0	0	0	0	0	45	0	1	0	0	140039	139536	139346	129360	25	80013	40010	30003	10000	30010	30590	10000	1264819	6692791	20082131	0	1	140030	140245	140058	130553	3	131161	70010	30020	10212	30000	60020	10000	30000	140054	140054	5	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	3	10000	1	1	0	0	3140	0	2	121	2	2	139576	40000	0	13	10	10000	20000	40010	140052	140036	140036	140055	140055
70024	140035	1048	0	0	0	0	0	0	0	0	1	0	1	0	0	140039	139474	139346	129360	25	80026	40010	30003	10000	30010	30000	10000	1264810	6693731	20089300	0	0	140011	140051	140051	130569	3	131176	70010	30020	10000	30000	60020	10000	30000	140035	140052	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	0	10000	1	1	0	0	3140	0	2	121	2	2	139577	40000	0	10	10	10000	20000	40010	140055	140055	140052	140036	140055
70024	140035	1049	0	0	0	0	0	0	0	0	1	0	0	0	0	140039	139487	139346	129343	25	80013	40010	30003	10000	30010	30000	10000	1264819	6693731	20089647	0	1	140011	140054	140154	130572	3	131179	70010	30020	10000	30000	60020	10053	30000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	0	10000	1	0	0	0	3140	0	2	121	2	2	139576	40000	13	13	10	10000	20000	40010	140053	140036	140036	140055	140052
70024	140054	1049	0	0	0	1	0	0	0	0	40	88	0	0	0	140036	139507	139344	129341	57	80010	40010	30000	10000	30010	30000	10000	1264719	6693584	20081843	0	0	140027	140051	140054	130572	3	131179	70010	30020	10000	30160	60020	10000	30000	140054	140035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	3140	0	2	121	2	2	139576	40000	10	13	10	10000	20000	40010	140052	140055	140055	140055	140055
70024	140035	1049	0	0	0	0	0	0	0	0	12	88	0	0	0	140136	139507	139325	129360	25	80013	40019	30003	10001	30010	30000	10000	1264783	6693731	20079451	0	0	140034	140079	140052	130572	3	131161	70010	30020	10000	30000	60020	10000	30000	140054	140144	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	3140	0	2	121	2	2	139573	40000	0	13	10	10000	20000	40010	140036	140052	140055	140036	140036
70024	140035	1049	0	0	0	0	0	0	0	0	0	0	0	0	0	140039	139507	139346	129360	25	80013	40010	30003	10000	30010	30000	10000	1264819	6693731	20082304	0	0	140011	140054	140054	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	0	3140	0	2	121	2	3	139652	40000	10	0	10	10000	20000	40010	140055	140055	140055	140055	140036

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.1d, v1.1d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	0e	0f	1e	22	23	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140058	1051	0	0	1	1	3	25	0	0	140872	140439	139552	129565	25	80103	40100	30003	10000	30249	30000	10000	1266232	6694039	20112218	0	140863	140045	140267	131420	3	131982	70100	30200	10000	30000	60200	10000	30000	140260	140260	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	0	0	10000	1	0	0	0	3210	3	133	3	3	140396	40000	10	10	0	10000	20000	40100	140888	140037	140888	140037	140888
70204	140887	1051	0	0	1	0	0	37	1	0	140021	139405	140175	130189	25	80100	40100	30003	10000	30100	30000	10000	1264319	6733631	20202004	0	140863	140887	140036	130767	3	131355	70100	30200	10000	30000	60200	10000	30000	140036	140036	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	10000	0	1	0	0	3210	2	129	3	3	139772	40000	0	13	13	10000	20000	40100	140888	140888	140037	140888	140888
70204	140934	1049	0	0	0	0	0	12	0	0	140872	140439	139326	130189	25	80103	40100	30003	10000	30100	30000	10000	1272055	6692839	20079595	0	140863	140887	140036	130826	3	131127	70100	30200	10000	30000	60200	10000	30000	140887	140036	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	1	0	0	3210	2	173	3	2	139545	40000	0	0	0	10000	20000	40100	140037	140261	140037	140261	140888
70204	140260	1051	0	0	1	0	0	31	1	0	140245	139408	140175	130189	25	80100	40100	30003	10000	30100	30000	10000	1272055	6733631	20111930	1	140863	140887	140887	131391	3	131982	70100	30200	10000	30000	60200	10000	30000	140260	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	36	10000	0	1	0	0	3210	3	129	3	3	139772	40000	0	13	13	10000	20000	40100	140888	140888	140037	140888	140888
70204	140887	1049	0	0	0	0	0	1	1	0	140245	139805	139326	129565	25	80103	40100	30003	10000	30100	30000	10000	1266232	6692839	20111930	0	140012	140260	140260	130532	3	131982	70100	30200	10000	30000	60200	10000	30000	140887	140308	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	1	10000	0	0	10000	0	0	0	0	3210	3	129	3	3	140396	40000	10	0	10	10000	20000	40100	140261	140037	140037	140037	140261
70204	140887	1050	0	0	0	0	0	13	1	0	140872	140439	140175	130189	25	80100	40100	30003	10000	30100	30000	10000	1264319	6733631	20111930	1	140863	140036	140887	130767	3	131982	70100	30200	10000	30000	60200	10000	30000	140889	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	0	10000	0	1	0	0	3210	3	129	3	3	139772	40000	13	13	0	10000	20000	40100	140888	140888	140888	140261	140888
70204	140036	1051	0	0	0	0	0	1	0	0	140872	139405	140175	129342	25	80100	40100	30003	10000	30100	30000	10000	1272091	6692839	20079595	1	140863	140887	140036	130767	3	131127	70100	30200	10000	30000	60200	10000	30000	140036	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	10000	0	3	10000	1	0	0	0	3210	2	129	3	3	139545	40000	0	10	10	10000	20000	40100	140037	140261	140261	140037	140037
70204	140036	1051	0	0	0	0	0	1	1	0	140245	139770	139552	129565	25	80100	40100	30003	10000	30100	30000	10000	1266232	6703613	20111930	1	140012	140036	140036	130767	3	131355	70100	30200	10000	30000	60200	10000	30000	140036	140036	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	1	0	10000	1	1	0	0	3210	3	133	3	3	139545	40000	13	0	13	10000	20000	40100	140888	140888	140888	140037	140888
70204	140260	1050	0	0	0	0	0	0	0	0	140872	139770	139552	129565	25	80103	40100	30003	10000	30100	30000	10000	1264319	6703613	20111930	1	140236	140260	140260	130767	3	131127	70100	30200	10000	30000	60200	10000	30000	140887	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	1	10000	0	0	10000	1	0	0	0	3210	3	129	3	3	139545	40000	13	0	13	10000	20000	40100	140888	140037	140037	140888	140888
70204	140260	1051	0	0	1	0	0	13	1	0	140021	140439	140177	129343	25	80103	40100	30003	10000	30100	30000	10000	1272073	6733679	20112218	1	140863	140036	140036	130767	3	131982	70100	30200	10000	30000	60514	10159	30000	140735	140260	3	1	50201	100	99	100	40100	10000	10000	0	100	10005	1	10000	1	0	10000	0	1	0	0	3210	3	129	2	3	140396	40000	13	0	13	10000	20000	40100	140040	140037	140037	140888	140888

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140448	1051	0	0	1	0	0	0	0	0	1	1	0	0	0	140245	139717	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	0	140236	0	140268	140262	130777	0	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	1	0	0	10000	1	0	1	1	0	0	0	3140	4	122	4	3	140201	40000	10	10	10	10000	20000	40010	140261	140261	140037	140261	140343
70024	140261	1050	0	0	0	0	0	0	0	0	1	1	0	0	0	140245	139488	139552	129342	25	80013	40010	30003	10000	30010	30000	10000	1264728	6703613	20079595	1	140236	0	140260	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10062	30000	140262	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	3140	3	122	4	3	139558	40000	10	10	10	10000	20000	40010	140037	140261	140261	140261	140037
70024	140261	1051	0	0	0	0	0	0	0	0	1	0	0	0	0	140667	139827	139747	129985	25	80016	40010	30006	10000	30010	30000	10000	1272485	6723821	20172574	1	140236	0	140261	140260	130554	0	3	131384	70010	30020	10000	30000	60020	10000	30000	140036	140039	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	1	0	0	0	3140	3	122	2	4	140201	40000	10	10	10	10000	20000	40010	140261	140037	140261	140261	140037
70024	140260	1050	0	0	0	0	0	0	0	0	1	1	0	0	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266716	6703613	20111930	1	140236	0	140684	140682	131197	0	3	131806	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	9	10000	0	0	1	1	4	0	0	3140	3	121	2	4	139978	40000	10	10	10	10000	20000	40010	140459	140683	140459	140459	140683
70024	140458	1054	1	0	0	0	0	0	0	0	6	0	0	0	0	140245	139716	139552	129565	25	80010	40010	30003	10000	30160	30000	10000	1266662	6703613	20111930	1	140236	0	140682	140461	131199	0	3	131806	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	0	0	3140	3	122	4	3	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140037	140037
70025	140260	1050	0	0	0	0	0	0	0	0	1	1	0	0	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	0	140236	0	140260	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	1	1	0	0	3140	2	122	3	2	140201	40000	10	10	10	10000	20000	40010	140683	140683	140683	140683	140683
70024	140682	1053	1	0	0	1	0	0	0	0	1	0	0	0	0	140245	139716	139326	129565	25	80013	40010	30000	10000	30010	30000	10000	1266662	6703613	20111930	0	140012	0	140465	140682	130974	0	3	131806	70010	30020	10000	30000	60020	10000	30000	140682	140682	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	3	0	10003	6	1	0	10000	1	0	1	0	0	0	0	3140	2	122	2	3	139558	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261
70024	140260	1049	0	0	0	0	0	0	0	0	1	1	0	0	0	140245	139716	139326	129565	25	80013	40010	30003	10000	30010	30000	10000	1264728	6692839	20079595	1	140012	0	140263	140122	130777	0	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	1	1	2	0	0	3140	4	122	4	3	139978	40000	10	10	10	10000	20000	40010	140683	140459	140683	140459	140683
70024	140682	1053	1	1	0	0	0	0	0	0	1	0	0	0	0	140245	139488	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266671	6693127	20111930	1	140236	0	140260	140036	130777	0	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	3140	3	122	2	4	139781	40013	0	10	10	10000	20000	40010	140261	140261	140037	140261	140558
70024	140392	1049	0	0	0	0	0	0	0	0	1031	1	0	0	0	140670	140235	139972	129985	25	80013	40010	30006	10000	30010	30000	10000	1268578	6723917	20140295	1	140434	0	140260	140260	130777	0	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	1	3	0	0	3140	5	122	2	3	140201	40000	0	10	0	10000	20000	40010	140261	140261	140261	140215	140261

Test 4: throughput

Count: 8

Code:

  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]
  ld2r { v0.1d, v1.1d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	40063	300	0	0	37	0	1	0	1	40026	10	0	0	25	240170	100	160070	80000	100	160000	80000	500	417954	4560014	1	0	40022	40064	40064	9973	3	9999	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80031	0	31	80000	6	1	31	37	5110	0	2	16	2	2	40056	0	0	80000	160000	100	40042	40060	40060	40060	40060
240204	40069	300	0	0	37	0	0	0	0	40044	10	10	0	25	240170	100	160070	80000	100	160000	80000	500	419911	1883850	0	0	40040	40059	40059	9973	3	9999	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80000	1	31	80031	6	1	0	37	5110	0	2	16	2	2	40056	14	10	80000	160000	100	40042	40042	40060	40060	40042
240204	40059	300	0	0	41	0	0	0	0	40044	8	10	0	25	240170	100	160070	80000	100	160000	80000	500	418050	4560014	0	0	40040	40059	40059	9973	3	10003	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	1	100	80000	37	80035	0	46	80031	6	0	0	37	5110	0	2	16	2	2	40056	10	10	80000	160000	100	40065	40042	40060	40060	40060
240204	40059	300	0	0	0	0	0	0	1	40026	10	0	0	25	240170	100	160070	80000	100	160000	80000	500	418498	4560016	0	0	40040	40041	40064	9973	3	9999	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80031	0	31	80031	6	1	31	37	5110	0	2	16	2	2	40056	10	10	80000	160000	100	40060	40042	40060	40060	40060
240204	40059	300	1	1	37	0	0	0	0	40044	0	10	0	25	240100	100	160082	80000	100	160000	80000	500	419850	4560014	0	0	40022	40059	40064	9973	3	10022	240100	200	80000	160000	200	80000	160000	40041	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80031	0	31	80031	0	1	31	37	5110	0	2	16	2	2	40056	14	10	80000	160000	100	40203	40060	40042	40060	40065
240204	40059	300	0	0	37	0	1	0	0	40049	0	10	0	25	240100	100	160070	80000	100	160000	80000	500	420571	5439994	0	0	40040	40041	40041	9973	3	10017	240100	200	80000	160000	200	80000	160000	40059	40041	1	1	80201	100	99	100	100	80000	80000	1	100	80000	37	80031	0	31	80000	0	1	31	37	5110	0	2	16	2	2	40038	0	10	80000	160000	100	40042	40060	40060	40065	40065
240204	40059	300	0	0	0	0	0	0	1	40044	10	8	0	25	240100	100	160000	80000	100	160000	80000	500	421999	1920972	0	0	40040	40059	40059	9973	3	9999	240100	200	80000	160000	200	80000	160000	40059	40041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	0	80000	0	31	80000	6	1	0	0	5110	0	2	16	2	2	40038	10	10	80000	160000	100	40065	40042	40060	40042	40060
240204	40059	300	0	0	37	0	1	0	0	40049	10	10	0	25	240170	100	160000	80000	100	160000	80000	500	422317	4560014	0	0	40040	40064	40059	9973	3	9999	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	41	80000	0	31	80031	0	1	31	0	5110	0	2	16	2	2	40061	14	0	80000	160000	100	40042	40060	40060	40060	40042
240204	40059	300	0	0	37	0	1	0	0	40026	0	0	0	25	240170	100	160082	80000	100	160000	80000	500	419942	1886788	0	0	40040	40041	40041	9973	3	10022	240100	200	80000	160000	200	80000	160000	40041	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80031	0	31	80035	6	1	31	37	5110	0	2	16	2	3	40038	0	10	80000	160000	100	40060	40060	40042	40060	40042
240204	40059	300	1	1	0	0	1	0	0	40044	10	10	0	25	240100	100	160070	80000	100	160000	80000	500	417950	4560014	0	0	40022	40041	40041	9973	3	10017	240100	200	80000	160000	200	80000	160000	40059	40041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	80000	0	31	80031	6	1	31	37	5110	0	2	16	2	2	40061	10	0	80000	160000	100	40060	40060	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	0e	0f	1e	22	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	e7	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	40055	300	0	0	1	0	37	0	0	0	40040	11	11	25	240064	10	160054	80000	10	160000	80135	50	419236	3457264	0	40119	40044	40055	9996	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	1	10	80000	30	0	80000	0	24	80024	6	1	24	30	5020	4	16	0	0	4	3	40052	0	6	6	80000	160000	10	40042	40056	40060	40056	40221
240024	40055	300	0	0	1	1	30	0	0	0	40026	11	11	25	240064	10	160054	80000	10	160000	80000	50	418753	3920018	0	40036	40055	40059	9996	3	10022	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	30	0	80000	1	24	80000	6	0	24	0	5020	4	16	0	0	4	2	40056	0	0	6	80000	160000	10	40056	40056	40042	40056	40056
240024	40055	300	0	0	0	0	30	0	0	0	40026	11	11	25	240010	10	160054	80000	10	160000	80000	50	418757	3920014	0	40036	40055	40059	9996	3	10021	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	30	0	80024	0	24	80024	0	0	0	30	5020	3	16	0	0	5	5	40052	0	6	6	80000	160000	10	40060	40042	40042	40060	40042
240024	40055	300	0	0	0	0	30	1	0	0	40040	11	11	25	240064	10	160054	80000	10	160000	80000	50	420942	3920014	0	40036	40055	40043	9996	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	30	0	80024	0	24	80024	6	1	24	30	5020	4	16	0	0	4	4	40052	0	6	6	80000	160000	10	40056	40042	40056	40056	40056
240024	40055	300	0	0	1	0	30	1	0	0	40040	11	11	25	240064	10	160070	80000	10	160000	80000	50	418496	3920014	1	40036	40041	40055	9996	3	10035	240010	20	80000	160000	20	80000	160000	40041	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	30	0	80024	0	24	80024	0	1	24	30	5020	5	16	0	0	3	5	40052	0	0	0	80000	160000	10	40056	40056	40056	40056	40056
240024	40055	300	0	0	0	0	30	1	0	0	40040	11	0	25	240010	10	160054	80000	10	160000	80000	50	418655	1930186	0	40036	40055	40055	9996	3	10021	240010	20	80000	160000	20	80000	160000	40055	40041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	30	0	80024	0	24	80000	6	1	0	30	5020	5	16	0	0	5	5	40052	0	6	0	80000	160000	10	40056	40042	40056	40056	40042
240024	40055	300	0	1	1	0	0	1	0	0	40040	11	11	25	240064	10	160054	80000	10	160000	80000	50	419553	4000002	0	40036	40055	40059	9996	3	10036	240010	20	80000	160000	20	80000	160000	40055	40041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80024	1	24	80000	6	1	24	30	5020	3	16	0	0	3	2	40052	0	0	6	80000	160000	10	40056	40056	40056	40056	40060
240024	40055	300	0	0	0	0	30	0	0	0	40040	0	0	25	240010	10	160054	80000	10	160000	80000	50	422010	3920016	1	40036	40055	40055	9996	3	10021	240010	20	80000	160000	20	80000	160000	40041	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	30	0	80031	0	24	80024	6	0	24	30	5020	4	16	1	0	4	3	40056	0	6	6	80000	160000	10	40056	40057	40056	40056	40056
240024	40055	300	0	0	0	0	30	1	0	0	40040	11	11	25	240010	10	160070	80000	10	160000	80000	50	418992	3920014	0	40022	40055	40055	9996	3	10035	240010	20	80000	160000	20	80000	160000	40041	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	30	0	80024	1	24	80024	6	1	24	30	5020	4	16	0	0	4	4	40052	0	6	0	80000	160000	10	40056	40042	40056	40042	40042
240024	40055	300	0	1	1	1	0	0	0	0	40040	0	11	25	240064	10	160070	80000	10	160000	80000	50	418582	3920014	0	40036	40055	40055	9996	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	30	0	80024	0	24	80024	0	1	31	37	5020	4	16	0	0	3	4	40052	0	6	0	80000	160000	10	40042	40056	40042	40056	40056

LD2R (1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations