Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (2S)

Test 1: uops

Code:

  ld2r { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f22233a3f43464951schedule uop (52)schedule simd uop (54)schedule ldst uop (55)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaebec? ldst retires (ed)? simd retires (ee)f5f6f7f8fd
630052842321424020000053901047712812901116073300020041000200010005000238566228182839428441310300010002000100020022827628334116100110001000110000210000001001212013675994070793375155197983395381720504627939143131254613536100020002829828206283352833228233
63004283162120202000008000510928074001161603000200010002000100050002387282276428169281603103000100020001000200028270281041161001100010001100002100110010012020137001013372533350044194783432382213444227886143761250213420100020002825028397282592834628400
63004282442110202001003660105106281290001633130062006100020001000500023804112278028363282793103000100020001000200028281281111161001100010000100002100000110001020139161016271933335147197393304381021494627879144511229113100100020002820328462283832840028400
6300428446212010100000396010502828113010161473004200410002000100050002381272278328236281403103000100020001000200028269282901161001100010001100002100122010011020137921032772723404152197333440382312495027867143821242013295100020002849228284282622827928459
63004284112120102100003620105018280750001625230042004100020001000500023814102279428318283343103000100020001000200028197282911161001100010000100002100010110011020137941008671813257045198563265381510514727894144411291913498100020002828728326283102824828291
6300428301212020200000275000498028039011161633004200410002000100050012384802275028264282853103000100020001000200028261282651161001100010000100002100010010002000136261027571723407046196953211381410485427921148841260113690100020002834328337282832842728395
630042830521302010000045010501428216000161903004200410002000100050002385922280428367285193103000100020001000200028261284331161001100010000100002100000010001100136441011871763395146196983324381821465228122156521304513726100020002895228874287392870328641
63004287242220202010002000504528323000161933004200610002000100050002386002272228356283263103000100020001000200028295282881161001100010000100002100100010001030136081004072393324145195283316381312474827938143481246913058100020002842928198281822816428157
6300428246211020301000170005095282360001625230002004100020001000500023816422747282232838631030001000200010002000282432839311610011000100001000001000000100100201353198237212342304519740335838139434427880145401237713081100020002808728176284182838528363
630042841121101020000060501050472807200116192300420061000200010005000238595227472826528416310300010002000100020002830528247116100110001000110000210010011000002013750102767170340305119739333138185444627796144911280913254100020002838228301283232846728232

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2s, v1.2s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

retire uop (01)cycle (02)03mmu table walk data (08)0e0f18191e2223243f4d4e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)branch cond mispred nonspec (c5)cfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
70205140051104900000110014008613961413934612936025801034010030000100003010030000100001264354669373120081843051400301401071400551305620313115070100302001000030000602001000030000140035140051115020110099100401001000010000110010000011000000100011103210501128111395664000001013100002000040100140052140055140036140055140052
70204140035104901104250001400201394041393461293602580100401003000310000301003000010000126431066927912008184315140030140054140053130559031311507010030200100003000060200100003000014005414005111502011009910040100100001000001001000001100001180100001103210521128111395444000001313100002000040100140036140055140036140055140055
7020414005410490000011001400201395611393251293572580103401003000310000301003000010000126431066937312008184315140030140131140057130562031311507010030200100003000060200100003000014003514005111502011009910040100100001000001001000001100001010000110321001112811139544400000013100002000040100140036140055140052140036140055
70204140054104900000000014002013960813932512936025801034010030003100003010030000100001264390669373120081843151400111400541400511305310313115070100302001000030000602001000030000140054140035115020110099100401001000010000010010000011000011100001103210021133111395664000010010100002000040100140055140036140052140055140052
702041400511049000001000140020139608139346129360258010340100300031000030100300001000012643106693584200818431514002714008814005113056203131127701003020010000300006020010000300001400541400361150201100991004010010000100000100100000010000011000001032100011281113956440000101013100002000040100140055140055140036140053140055
70204140051104900000000014003913940413934612936025801034010030003100003010030000100001264310669279120082304151400111400381400541305670313112670100302001000030000602001000030000140035140051115020110099100401001000010000010010000011000000100001103210521133111395444000001313100002000040100140036140055140055140055140055
702041400541049000400000140039139608139346129341258010340100300031000030100300001000012643106693731200818431514001114005514005113056203131147701003020010000300006020010000300001400541400351150201100991004010010000100000100100010010000001000011032105311281113956640000000100002000040100140055140055140036140055140036
70204140054104900000100014002013940413938012936625801004010030000100003010030000100001264319669373120079451101400111400541400571305610313115070100302001000030000602001000030000140035140051115020110099100401001000010000010010000011000000100001103210511133111395694000001310100002000040100140055140055140055140036140055
70204140054104900000100014003913960813932512934125801034010030009100003010030000100001264390669279120082563151400301400601400541305620313114770100302001000030000602001000030000140051140035115020210099100401001000010000010010000011000011100000103210501128111395664000013130100002000040100140060140055140055140055140055
7020414005410490010060001400201396081393251293412580100401003000310000301003000010000126431066937312008184315140030140054140035130567031311507010030200100003000060200100003000014005414003511502011009910040100100001000001001000001100000010000010321051112811139566400001300100002000040100140055140036140055140055140055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0051

retire uop (01)cycle (02)030e0f18191e1f22233f4d4e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
70025140057104900006010140036139507139325129357258001040010300061000030010300001000012647836693584200818430140027014005114005113056931311767001030020100003000060020100003000014005114005111500211091040010100001000001010000110000101000010000314061213313957340000101010100002000040010140052140052140036140036140040
7002514008910490000201014003613950713934412934125800134001030000100003001030000100001264783669363220081843014002801400511400511305693131176700103002010000300006002010000300001400511400511150021109104001010000100000101000011000016100001010031407121741395734000010010100002000040010140052140036140052140052140052
70024140036104900011010140020139507139344129357258001340010300031000030010300001000012647196693584200794510140027014005114005113055331311797001030020100003000060020100003000014005114003511500211091040010100001000001010000110000191000010100314071207313957340000131010100002000040010140052140052140052140055140052
700241400511049000010101400241395071393441293572580010400103000310000300103000010000126478366927912008184301400760140051140051130569313118470010300201000030000600201000030000140051140059115002110910400101000010000010100001100000010000101003140712173139557400000100100002000040010140036140052140052140036140052
70024140051104900001010140020139487139325129357258001340010300001000030010300001000012647836693584200818430140027014005114003513055331311767001030020100003000060020100003000014005114005111500211091040010100001000001010000110000001000000100314031217413957340000101010100002000040010140052140052140052140052140055
700241400511049000000001400361395071392751293632580013400103000310000301503073810050126478366927912008184301400280140409140051130569313117670010300201000030000600201010730000140051140051115002110910400101000010000010100001100001127241000210100314031203313957340000101010100002000040010140036140102140053140054140052
700241400531049001313010140020139507139344129341258001340010300031000030010300001000012649456694064200794510140027014005114005413056931311767001030020100003000060020100003000014005114005111500211091040010100001000001010000010000101000010100317731213313957340000131010100002000040010140052140052140052140052140052
70024140052105000001010140020139507139344129357258001040010300031000030010300001000012648196693584200794510140027014005114005113056931311767001030020100003000060020100003000014005114003511500211091040010100001000001010000110000001000010000314041213813957340000101010100002000040010140052140055140052140036140052
70024140051104900001010140036139487139344129357258001340010300031000030010300001000012647836693731200818430140011014005114005113060131311797001030020100003000060020100003000014008314005111500211091040010100001000001010000110000001000010000314071217313957340000101010100002000040010140052140036140036140052140052
7002414005110490000100014003613948713934412935725800134001030003100003001030000100001264783669358420081843114002701400511400511305693131176700103002010000300006002010000300001400351400511150021109104001010000100000101000011000000100001010031403120331395734000013100100002000040010140036140052140052140052140052

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2s, v1.2s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0887

retire uop (01)cycle (02)0309l2 tlb miss data (0b)0e0f191e22233f4d4e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)int prf full (71)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
702051406511050100001101402451394051401751295652580103401003000310000301003000010000126623266928392011193011408631408871408871313910313198270100302001000030000602001000030000140260140036115020110099100401001000010000110010000011000000010000110321021332114039640000101010100002000040100140037140037140888140261140261
7020414088710480001016200140021140439140175130189258010340100300001000030100300001000012643196733631201119300140012140447140887130532031319827010030200100003000060200100003000014088714003611502011009910040100100001000001001000001100020001000010032102129121403964000013010100002000040100140037140888140888140888140261
702041408871050000001101400211394051401751293732580103401003000310000301003000010000126431966928392011193011408631400361408871313910313112770100302001000030000602001000030000140260140260115020110099100401001000010000110010000011000000010000100321021291214039640000131310100002000040100140037140037140888140888140262
702041408881051000006101402451404391401751301892580100401003000010000301003000010000127205566928392011193011408631408871408871313910313198270100302001000030000602001000030000140036140260115020110099100401001000010000010010000001000300010000100321021332213954540000131313100002000040100140037140078140043140261140888
702041400361050000000101408721404391401751301892580103401003000310000301003000010000127205567336312011193011408631400361400361307670313112770100302001000030000602001000030000140887140036115020110099100401001000010000010010000011000300010000110321021291113977240000000100002000040100140037140888140888140261140888
70204140260105100000697101402451394051393261301892580103401003000010000301003000010000127205566928392011193011402361402601408871305320313198270100302001000030000602001000030000140887140036115020110099100401001000010000010010000011000201010000100321011291113977240000000100002000040100140888140888140888140888140261
7020414088710500000001014024513940514017512956525801034010030003100003010030000100001272055673363120111930114086314088714088713057203131982701003020010000300006020010000300001404271402601150201100991004010010000100000100100000110003500100001103210112922140396400001000100002000040100140037140888140888140261140037
70204140887105100000600140872140278139326130189258010040100300001000030100300001000012720556692839201071871140863140260140887131391031319827010030200100003000060200100003000014088714026011502011009910040100100001000001001000001100040001000011032102129221403964000013013100002000040100140037140888140888140037140040
70204140036105100000100140872140439140175130189258010340100300001000030100300001000012643196692839201119301140863140887140887131391031311277010030200100003000060200100003000014003614026011502011009910040100100001000001001000001100020001000011032102129221395454000013010100002000040100140888140888140888140037140261
7020414088710480000030014087214043914017513018925801004010030000100003010030000100001272055673363120079595114086314088714026013076703131982701003020010000300006020010000300001408871400361150201100991004010010000100000100100000110004100100001003210212922140396400000013100002000040100140888140888140037140888140888

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0464

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f191e1f22233a3f4d4e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acafb5l1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
7002514046410520100001010014044913986813979712977525800134001030003100003001030000100001268532671336620141197014001301403591404661309803131589700103002010000300006002010000300001404641404641150021109104001010000100000101000011000000010000110314041212213998440000666100002000040010140485140469140465140465140465
7002414046410520000001010014002113986213975312976825800134001030003100003001030000100001268532671336620141197114044001400361404641309803131589700103002010000300006002010000300001404641400361150021109104001010000100000101000011000000010000110314021212213998440000666100002000040010140526140465140037140465140465
7002414046410520000001010014044913986513975312976825800134001030003100003001030000100001268532671336620141197114044001404641404641309803131589700103002010000300006002010000300001404641404641150021109104001010000100000101000011000000010000100314021212213998440000666100002000040010140550140467140468140465140456
7002414046410520000001010014044913948813981112976825800134001030000100003001030000100001268532671336620141197114001201404791404641309803131589700103002010000300006002010000300001404641404641150021109104001010000100000101000011000000010000100314021212213955840000666100002000040010140499140465140503140469140465
7002414003610490000001000014044913986213975312976825800134001030003100003001030000100001268532669283920141197114044001404671400361309803131589700103002010000300006002010000300001404641404641150021109104001010000100000101000011000000010000110314021212213998440000666100002000040010140466140465140465140465140465
700241404641052000000101001400211398621397531297682580013400103000310000300103000010000126853266964612014119711404400140464140720130980201315897001030181100003000060020100523000014046514071911500211091040010100001000001010024110034050100001143476232632139984400006256100002000040010140465140465140465140037140465
7002414046410520000001010014002113948813977612976925800134001030003100003001030000100001268532671336620141197114044001404641404641309803131162700103002010000300006002010000300001404641404641150021109104001010000100000101000011000000310000010314021202213998440000666100002000040010140532140474140465140465140037
7002414046410520000001010014044913986213975312976825800104001030003100003001030000100001268532671336620141197114047601404641400361309803131589700103002010000300006002010000300001404641404641150021109104001010000100000101000001000000010000110314021212213998440000000100002000040010140045140465140037140037140465
70024140464109000000010100140449139862139753129768258001340010300031000030010300001000012685326692839201411971140440014046414046413098028131589700103002010000300006002010000300001404641404641150021109104001010000100000101000011000000010000100314021212213998440000666100002000040010140465140465140476140484140465
7002414046410520000001010014044913977713975312934225800134001030000100003001030000100001268532671336620141197114044001404641404641305543131589700103002010000300006002010000300001404641400361150021109104001010000100000101000011000000010000000314021212213998440000066100002000040010140506140465140465140465140465

Test 4: throughput

Count: 8

Code:

  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  ld2r { v0.2s, v1.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)030e0f1e1f22233f43464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
24020540063300003701040044310102524010010016007080000100160000800005004184201845094140158400594005999730310017240100200800001600002008000016000040059400591180201100991001008000080000010080000080000031800006031370511021622400561010800001600001004004540060400604006040060
2402044005930000001040044010102524017010016007080000100160000800005004184264560014140040400594005999730310017240100200800001600002008000016000040059400411180201100991001008000080000010080000378003100800316131370511021622400561010800001600001004006040060400604006040060
2402044005930000370004004401010252401701001600708000010016000080000500418403456001414004040059400599973039999240100200800001600002008000016000040041400591180201100991001008000080000110080000378000009180031613137051102162240056010800001600001004006040060400604004240060
2402044005930000370104004401010252401701001600708000010016000080000500418403456001414004040041400599973031001724010020080000160000200800001600004005940059118020110099100100800008000011008000037800310318003161037051102162240038100800001600001004006040044400444004240060
240204400593000037000400440101025240100100160070800001001600008000050041842045600141400404005940041997303100172401002008000016000020080000160000400594004111802011009910010080000800000100800003780000031800316031370511021622400381010800001600001004006040046400604049540060
240204400593000037010400440101025240170100160070800001001600008000050041840318450941400224005940059101040310017240100200800001600002008000016000040059400591180201100991001008000080000110080000378000003180031613137051103162240056100800001600001004006040060400604006040060
24020440059300003701040044010102524017010016007080000100160000800005004184264560014140022400594004199730399992401002008000016000020080000160000400594004111802011009910010080000800001100800003780000031800310100051102162240056010800001600001004004440060400604004240060
24020440059300000010400440101025240100100160000800001001600008000050041842045600141400404005940041997303100172401002008000016000020080000160000400594004111802011009910010080000800000100800003780000031800316131370511021622400561010800001600001004006040062400604004240060
240204400413000000104004401010252401701001600708000010016000080000500418403456001414004040041400599973031001724010020080000160000200800001600004004140041118020110099100100800008000001008000037800310378055161310051102162240056010800001600001004006040060400604004540060
24020440041300000010400440101025240170100160070800001001600008000050041842645600141400404005940059997303102782401002008000016000020080000160000400414005911802011009910010080000800000100800003780423031800316131370511021622400561010800001600001004006040060403434006040044

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5008

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)09l2 tlb miss data (0b)0e0f1e22243a3f4346494e51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
24002540065300111100621034005021818125240088101600788000010160000800005041861754400800400464006540065999631004524001020800001600002080000160000400654004711800211091010800008000001080000000800000003180000615301605020516544004409080000160000104064840060400604005640056
2400244005930000000037101400440181812524009210160024800001016000080000504186575440082040046400474004799963100452400102080000160000208000016000040065400651180021109101080000800000108000003008003100031800310016411615020517664006200080000160000104006640066400484006640066
240024400653001111006300140032201812524009210160024800001016000080000504186175440082140046400654006599963100452400102080000160000208000016000040065400651180021109101080000800000108001617008005301020800376052411615020616554006200980000160000104006640066400484006640048
24002440065300100000631034005021818125240092101600828000010160000800005041861754400801400464004740065999631004524001020800001600002080000160000400654006511800211091010800008000011080017164108005410257800370152411615020516564006200980000160000104004840066400664006640066
24002440065300111100630024005021818125240092101600248000010160000800005041528154400801400464006540065999631004524001020800001600002080000160000400654004711800211091010800008000001080018184108005210057800000053411615020516564006200980000160000104006640066400664004840066
2400244004730010010062003400322180125240088101600788000010160000800005041528754400821400464006540065999631002724001020800001600002080000160000400474006511800211091010800008000001080017174108005310057800006153411615020416664006209980000160000104006640066400664006640066
240024400653001011006300140050218002524003410160082800001016000080000504158255440082140028400474006599963100452400102080000160000208000016000040065400651180021109101080000800001108001817008005400020800380153421605020616544006209980000160000104006640066400484006640066
240024400653001011012010240050001812524008810160024800001016000080000504185905440082140028400474004799963100452400102080000160000208000016000040065400651180021109101080000800001108001616008005300260800006116411605020516764006200980000160000104006640066400484006640048
2400244004730011100064002400502180125240092101600828000010160000800005041528154400821400464006540065999631004524001020800001600002080000160000400474004811800211091010800008000001080018174108001610056800376053411605020616664006200980000160000104006640066400664006640048
24002440065300100100640024005021818125240092101600828000010160000800005041528154400801400284006540065999631004524001020800001600002080000160000400654006511800211091010800008000001080016184108001610020800320153411615020616544004409980000160000104006640066400484004840066