Firestorm: LD2R (8B) measurements

Code:

  ld2r { v0.8b, v1.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	0e	0f	1e	1f	22	24	3a	3f	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	28209	212	16	1	12	0	1	2	0	0	0	5254	28000	0	16061	3000	2004	1000	2000	1000	5000	23804	5	0	22781	28157	28053	3	10	3000	1000	2000	1000	2000	28080	27960	1	1	61001	1000	1000	0	1000	2	1001	0	0	1000	2	0	2	14055	10535	7321	3498	6	48	19419	3377	3833	16	40	41	27904	13905	12442	12895	1000	2000	28173	28511	28542	28128	28090
63004	28016	212	14	0	16	1	1	2	0	1	0	4922	27880	0	16591	3004	2000	1000	2000	1000	5000	23865	1	0	22819	28028	28262	3	10	3000	1000	2000	1000	2000	28445	28559	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	0	2	13982	10549	7194	3520	4	43	19591	3414	3824	10	38	42	27824	14016	13067	12585	1000	2000	28112	28116	28173	28300	28291
63004	28072	210	16	0	11	1	1	0	0	0	0	5198	27943	0	15931	3004	2004	1000	2000	1000	5000	23818	2	0	22807	28073	28134	3	10	3000	1000	2000	1000	2000	28505	28072	1	1	61001	1000	1000	0	1000	0	1000	0	0	1000	2	0	2	13585	10479	7353	3562	9	43	19872	3411	3826	14	39	40	27786	15244	12368	13512	1000	2000	28037	28134	28301	28077	28133
63004	28463	210	15	0	12	1	1	38	0	1	0	4958	27832	1	16036	3006	2000	1000	2000	1000	5000	23852	2	0	22726	28039	28600	3	10	3000	1000	2000	1000	2000	28398	27976	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	1	0	2	14231	10504	7308	3448	7	38	19532	3502	3826	14	43	38	28106	13654	12110	12787	1000	2000	28113	28550	28203	28047	28635
63004	27972	210	14	0	6	0	0	2	88	0	0	5005	27897	0	15962	3006	2004	1000	2000	1000	5000	23848	4	0	22784	28054	28486	3	10	3000	1000	2000	1000	2000	28282	28050	1	1	61001	1000	1000	0	1000	2	1000	0	3	1000	2	0	2	14205	9771	7307	3308	4	45	19400	3425	3825	15	45	40	27890	14122	12611	13230	1000	2000	27990	28601	28018	28167	28108
63004	28069	210	13	0	9	0	0	2	0	0	0	5225	27860	0	16463	3004	2004	1000	2000	1000	5000	23802	3	0	22727	28035	28104	3	10	3000	1000	2000	1000	2000	27998	28195	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	2	0	2	14105	10275	7229	3479	5	41	19530	3529	3827	11	38	39	27778	13912	12224	12960	1000	2000	28101	28124	28320	28248	28248
63004	28112	211	12	0	12	0	0	0	0	0	0	5300	27750	0	16013	3006	2004	1000	2000	1000	5000	23864	6	0	22774	28166	28089	3	10	3000	1000	2000	1000	2000	28275	28129	1	1	61001	1000	1000	0	1000	2	1000	0	4	1000	2	0	0	13843	10596	7269	3123	7	38	19367	3431	3825	15	43	44	27826	14282	12042	12871	1000	2000	28041	28196	28111	28002	28257
63004	28035	214	16	0	16	0	1	2	0	0	0	5215	27979	0	15965	3004	2004	1000	2000	1000	5000	23882	2	0	22794	27957	28136	3	10	3000	1000	2000	1000	2000	28631	28099	1	1	61001	1000	1000	0	1000	2	1000	0	0	1000	0	0	2	13095	10168	7358	3471	5	40	19364	3415	3829	9	39	43	27828	13579	12159	12707	1000	2000	28170	28157	28718	28094	28571
63004	28536	214	16	0	16	0	0	2	0	0	0	5188	28018	0	16195	3002	2004	1000	2000	1000	5000	23808	2	0	22806	28187	28199	3	10	3000	1000	2000	1000	2000	28094	28190	1	1	61001	1000	1000	0	1000	2	1000	1	0	1000	1	0	0	13895	10392	7327	3533	4	34	19456	3352	3829	8	40	37	27808	15192	12426	12766	1000	2000	28135	28568	28142	28650	28086
63004	28109	211	13	0	16	0	0	0	0	1	0	4911	27925	0	16399	3006	2000	1000	2000	1000	5000	23867	2	0	22824	28082	28027	3	10	3000	1000	2000	1000	2000	28122	28164	1	1	61001	1000	1000	0	1000	2	1000	1	0	1000	2	0	2	14126	9889	7286	3506	6	41	19624	3138	3831	13	39	39	28023	14697	13196	14021	1000	2000	28231	28341	28274	28144	28101

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8b, v1.8b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140053	1049	1	0	0	1	1	1	0	0	2	0	1	0	0	0	140687	139450	139345	129359	25	80106	40100	30006	10000	30100	30000	10000	1264288	6693091	20082149	1	140029	0	140056	140056	130564	3	131152	70100	30200	10000	30000	60200	10000	30000	140056	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	0	10001	0	0	1	10000	0	1	1	1	1	0	3210	0	1	128	1	1	139573	40000	9	0	9	10000	20000	40100	140057	140057	140057	140062	140152
70204	140041	1049	1	0	0	0	1	1	0	0	34	0	1	0	0	1	140041	139450	139348	129359	25	80106	40100	30006	10000	30100	30000	10000	1264288	6693682	20082149	0	140017	0	140056	140041	130549	3	131137	70100	30200	10000	30000	60200	10000	30000	140041	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10002	0	1	1	10000	1	1	1	1	0	0	3210	0	1	128	1	0	139568	40000	9	6	9	10000	20000	40100	140057	140042	140057	140057	140057
70204	140056	1049	1	1	0	0	1	1	0	0	2	0	0	0	0	0	140041	139638	139332	129362	25	80103	40100	30006	10000	30100	30000	10000	1264288	6693829	20082149	1	140032	0	140041	140056	130549	3	131264	70100	30200	10000	30000	60200	10000	30000	140056	140041	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	3	1	10002	0	0	1	10000	1	1	0	1	1	0	3248	0	1	128	1	1	139554	40000	0	9	9	10000	20000	40100	140057	140057	140073	140042	140054
70204	140056	1049	1	1	0	1	1	1	0	0	2	0	1	0	0	0	140041	139450	139348	129362	25	80103	40100	30006	10000	30100	30000	10000	1264304	6693829	20080361	1	140032	0	140053	140041	130549	3	131137	70100	30200	10000	30000	60200	10000	30000	140041	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	0	10001	0	0	1	10000	0	1	0	1	0	0	3210	0	1	128	1	1	139565	40000	9	9	9	10000	20000	40100	140057	140057	140042	140042	140057
70204	140056	1049	1	0	0	0	0	0	0	0	1	0	0	0	0	0	140041	139439	139348	129362	25	80106	40100	30006	10000	30100	30000	10000	1264288	6693829	20080361	1	140032	0	140056	140056	130564	3	131152	70100	30200	10000	30000	60200	10000	30000	140041	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10002	0	2	1	10000	1	1	1	1	0	0	3210	0	1	128	1	1	139554	40000	0	6	0	10000	20000	40100	140042	140054	140054	140054	140057
70204	140053	1049	1	0	0	0	0	0	0	0	2	0	0	0	0	0	140043	139638	139332	129359	25	80106	40100	30003	10000	30100	30000	10000	1264288	6693829	20080361	1	140032	0	140056	140053	130564	3	131149	70100	30200	10000	30000	60200	10000	30000	140056	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10002	1	1	1	10000	1	1	1	1	0	0	3210	0	1	128	1	1	139568	40000	0	0	6	10000	20000	40100	140057	140042	140057	140042	140057
70205	140041	1049	1	1	0	0	0	1	0	0	2	0	0	0	0	0	140077	139592	139348	129362	25	80106	40100	30006	10000	30100	30000	10000	1264288	6693091	20082149	1	140017	0	140041	140056	130564	3	131152	70100	30200	10000	30000	60200	10000	30000	140053	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	2	1	10001	1	1	1	10000	1	1	0	1	1	0	3210	0	1	128	1	1	139568	40000	9	9	9	10000	20000	40100	140057	140057	140057	140057	140057
70204	140041	1049	1	0	0	1	0	0	0	0	2	0	0	0	0	0	140041	139638	139354	129362	25	80106	40100	30006	10000	30100	30000	10000	1264304	6693091	20082149	1	140032	0	140041	140041	130564	3	131152	70100	30200	10000	30000	60200	10000	30000	140056	140041	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10002	0	1	184	10000	1	1	1	1	1	0	3210	0	1	128	1	1	139612	40000	9	9	0	10000	20000	40100	140057	140057	140054	140057	140057
70204	140041	1049	1	1	0	1	0	0	0	0	2	0	0	0	0	0	140041	139638	139332	129359	25	80106	40100	30006	10000	30100	30000	10000	1264304	6693829	20080361	1	140032	0	140056	140041	130549	3	131152	70100	30200	10000	30000	60200	10000	30000	140056	140053	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	3	1	10001	0	0	1	10000	0	1	1	1	0	0	3210	0	1	128	1	1	139565	40000	0	0	0	10000	20000	40100	140057	140057	140057	140057	140042
70204	140056	1049	1	1	0	0	0	0	0	0	2	0	0	0	0	0	140038	139638	139332	129362	25	80106	40100	30006	10000	30100	30000	10000	1264381	6693829	20080361	1	140017	0	140043	140056	130549	3	131202	70100	34074	10902	33836	67530	11276	32868	142436	142588	27	1	50201	100	99	100	40100	10000	10000	1	100	10034	4	1	10041	0	0	32509	10000	1	1	1	1	0	0	3868	0	1	272	2	4	141296	40146	9	9	0	10000	20000	40100	142300	140042	140055	140057	140170

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140052	1049	0	0	0	1	0	0	1	0	0	0	183	0	1	0	0	0	140035	139446	139343	129360	25	80010	40010	30000	10000	30010	30000	10000	1264719	6693388	20079451	0	140024	3	140047	140035	130565	0	3	131175	70010	30020	10000	30000	60020	10000	30000	140035	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	1	0	10000	1	0	0	0	0	3140	9	120	5	4	139572	40000	9	6	6	10000	20000	40010	140051	140051	140051	140051	140149
70024	140050	1049	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	140035	139487	139325	129353	151	80010	40010	30003	10000	30010	30000	10198	1264771	6692791	20081263	0	140023	0	140035	140047	130568	0	3	131173	70010	30020	10000	30000	60020	10000	30000	140035	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	1	6	10000	1	0	0	0	0	3140	7	120	7	4	139572	40000	0	9	9	10000	20000	40010	140051	140051	140051	140048	140051
70024	140050	1049	0	0	0	0	0	0	0	1	2	0	598	0	0	0	0	1	140020	139491	139325	129356	25	80010	40010	30003	10000	30010	30000	10000	1264771	6692791	20079451	0	140026	0	140050	140047	130568	0	3	131175	70010	30020	10000	30000	60020	10000	30000	140035	140053	5	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	0	1	0	0	0	3140	5	122	4	6	139844	40000	9	9	9	10000	20000	40010	140051	140036	140095	140048	140051
70024	140050	1049	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	0	140020	139491	139338	129356	25	80013	40010	30003	10000	30010	30000	10000	1275691	6692983	20081697	0	140011	0	140039	140439	130568	0	3	131175	70010	30020	10211	30000	60020	10000	30000	140035	140049	1	1	50021	10	9	10	40010	10000	10000	1	10	10005	1	10000	0	0	0	10000	0	1	0	0	0	3140	6	121	7	4	139572	40000	9	0	9	10000	20000	40010	140048	140036	140048	140048	140048
70024	140050	1048	0	0	0	0	0	0	0	0	1	0	1	0	1	0	0	0	140032	139446	139338	129356	25	80013	40010	30003	10000	30010	30000	10000	1264719	6693388	20081263	0	140026	0	140035	140047	130568	0	3	131174	70010	30020	10000	30000	60020	10000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	0	10000	1	1	0	0	0	3140	5	120	4	3	139569	40000	0	6	6	10000	20000	40010	140036	140051	140036	140036	140056
70024	140050	1049	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	140032	139487	139343	129356	25	80013	40010	30003	10000	30010	30000	10000	1264719	6693535	20081697	0	140026	0	140035	140050	130553	0	3	131161	70010	30020	10000	30000	60020	10000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	10000	0	0	0	10000	1	0	0	0	0	3140	7	120	7	4	139557	40000	0	6	9	10000	20000	40010	140051	140051	140036	140036	140051
70024	140145	1049	0	0	0	0	0	0	0	0	0	0	10	0	0	0	0	0	140035	139487	139338	129356	25	80013	40010	30003	10000	30010	30000	10000	1264771	6692791	20079451	1	140023	0	140050	140050	130568	0	3	131175	70010	30020	10000	30000	60020	10000	30000	140035	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	0	3	10000	0	0	0	0	0	3140	4	120	4	5	139572	40000	9	9	9	10000	20000	40010	140036	140051	140048	140048	140051
70024	140050	1049	0	0	0	0	0	0	0	0	0	0	9	0	0	0	0	0	140037	139491	139325	129341	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693535	20081263	0	140023	0	140050	140050	130568	0	3	131175	70010	30020	10000	30000	60020	10000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	0	3	10007	1	0	0	0	0	3140	5	120	5	3	139572	40000	6	9	0	10000	20000	40010	140048	140037	140051	140051	140051
70024	140050	1049	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	140040	139491	139338	129356	25	80013	40010	30003	10000	30010	30000	10000	1264748	6693388	20081697	0	140011	0	140035	140050	130553	0	3	131175	70010	30020	10000	30190	60020	10000	30000	140065	140057	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	0	10000	0	0	0	0	0	3140	4	121	4	3	139569	40000	6	0	0	10000	20000	40010	140048	140048	140036	140053	140052
70024	140050	1049	0	0	0	0	0	0	1	0	0	0	1	0	1	0	0	0	140020	139446	139325	129353	25	80013	40010	30000	10000	30010	30000	10000	1264771	6692791	20079451	0	140026	0	140035	140050	130568	0	3	131161	70010	30020	10000	30000	60020	10000	30000	140047	140035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	0	0	10000	0	1	0	1	0	3140	3	120	4	5	139557	40000	9	9	15	10000	20000	40010	140048	140036	140095	140051	140038

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8b, v1.8b }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140701	1052	0	0	0	0	1	0	2	0	1	0	0	0	140021	139770	139326	129565	25	80100	40100	30003	10000	30100	30000	10000	1264319	6703613	20111930	140236	0	140036	140260	130532	3	131777	70100	30200	10000	30000	60200	10000	30000	140260	140260	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10002	0	0	0	1	10000	1	0	1	0	0	0	0	3210	4	129	4	3	139778	40000	10	0	10	10000	20000	40100	140037	140261	140261	140264	140261
70204	140263	1050	0	0	0	0	0	0	10	88	1	0	0	0	140249	139770	139552	130189	25	80103	40100	30003	10000	30253	30000	10000	1266232	6703613	20111930	140236	0	140260	140260	131391	3	131127	70100	30200	10000	30000	60200	10000	30000	140261	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10001	1	0	1	0	0	0	0	3210	3	129	4	4	139787	40000	10	10	0	10000	20000	40100	140888	140261	140037	140261	140037
70204	140036	1050	0	0	0	0	0	0	1	0	0	0	0	0	140245	140439	139555	129342	59	80149	40100	30003	10000	30100	30000	10000	1266241	6703613	20111930	140239	0	140260	140260	130780	73	131982	70100	30516	10106	30475	60516	10107	30000	140260	140263	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	1	10003	1	8	2	12328	10000	1	0	1	0	0	0	0	3210	4	129	4	4	139775	40000	10	10	10	10000	20000	40100	140037	140037	140261	140037	140262
70204	140887	1049	0	0	0	1	1	0	13	0	1	0	0	0	140245	139405	139552	130189	25	80100	40100	30003	10000	30100	30000	10000	1272055	6703613	20202004	140863	0	140263	140684	130767	19	131355	70778	30349	10266	30470	61486	10054	30316	140260	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	3	10000	0	0	1	0	0	0	0	3210	4	129	4	4	140396	40000	0	10	10	10000	20000	40100	140261	140261	140263	140261	140264
70204	140260	1050	0	0	0	0	0	0	0	0	0	0	0	0	140021	140040	139802	129342	25	80100	40100	30003	10000	30100	30590	10000	1272055	6696915	20111930	140236	0	140260	140887	130767	3	131355	70100	30200	10000	30000	60200	10000	30000	140887	140260	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	0	0	0	0	0	3210	4	129	4	4	139772	40000	13	0	10	10000	20000	40100	140261	140261	140261	140888	140037
70204	140036	1050	0	0	0	0	0	0	1	0	0	0	0	0	140245	139770	139552	129342	25	80100	40100	30003	10000	30100	30000	10000	1266232	6703613	20111930	140236	0	140036	140260	130767	3	131355	70100	30200	10000	30000	60200	10000	30000	140887	140036	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	0	10000	1	0	1	0	0	0	0	3210	4	129	4	3	139772	40000	10	10	0	10000	20000	40100	140037	140261	140037	140261	140261
70204	140887	1051	0	0	0	0	0	0	1	0	1	0	0	0	140245	139770	139552	129342	25	80103	40100	30000	10000	30100	30000	10000	1266232	6703613	20202004	140863	0	140036	140260	130767	3	131355	70100	30200	10000	30000	60200	10000	30000	140260	140260	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	0	10000	1	3	1	1	0	1	0	3210	4	129	4	4	140191	40000	6	6	0	10000	20000	40100	140459	140679	140459	140468	140679
70204	140678	1054	1	1	1	0	0	0	10	0	0	0	0	0	140666	140216	139967	129984	25	80106	40100	30003	10000	30100	30000	10000	1270117	6723625	20140295	140434	0	140678	140458	131188	21	131783	70100	30200	10000	30000	60200	10000	30000	140678	140678	1	1	50201	100	99	100	40100	10000	10000	1	100	10002	2	0	10002	0	0	2	1	10000	0	1	1	1	0	0	0	3210	4	129	3	3	140188	40000	6	6	6	10000	20000	40100	140679	140679	140459	140679	140459
70204	140678	1052	1	1	0	0	0	0	2	0	0	1	0	1	140666	139866	139967	129981	25	80103	40100	30006	10000	30100	30000	10000	1270117	6713069	20171978	140654	0	140681	140678	131183	3	131773	70100	30200	10000	30000	60200	10000	30000	140678	140678	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	2	1	10003	0	0	1	1	10000	0	1	0	1	1	0	0	3210	4	129	4	3	140189	40019	0	0	6	10000	20000	40100	140459	140679	140679	140459	140459
70204	140678	1052	1	0	0	1	0	0	2	0	0	1	0	1	140665	140262	139967	129981	25	80103	40100	30006	10000	30100	30000	10000	1270024	6723625	20171978	140658	0	140678	140678	131183	3	131773	70100	30200	10000	30000	60200	10000	30000	140678	140458	1	1	50202	100	99	100	40100	10000	10000	0	100	10002	1	0	10002	0	0	0	1	10000	1	1	0	1	2	0	0	3210	4	129	4	3	140188	40000	6	6	9	10000	20000	40100	140679	140679	140679	140679	140682

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0260

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140260	1051	0	0	1	0	0	0	0	0	0	1	0	0	0	0	140245	139488	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1264728	6703613	20079595	1	140236	0	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	30000	140036	140260	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	1	0	0	10000	1	1	0	3140	0	0	20	122	0	0	17	6	139781	40000	10	0	10	10000	20000	40010	140037	140261	140261	140261	140261
70024	140260	1051	0	0	0	0	0	0	0	0	0	1	0	0	0	0	140245	139716	139552	129565	36	80013	40010	30000	10000	30010	30000	10000	1264728	6703613	20111930	1	140236	0	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	0	1	10000	0	0	0	0	10000	0	0	0	3140	0	0	7	122	0	0	5	17	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140037
70024	140260	1051	0	0	0	0	0	0	0	0	0	0	0	1	0	0	140245	139716	139552	129342	25	80010	40010	30003	10000	30010	30000	10000	1266662	6692839	20111930	1	140236	0	140260	140260	131401	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	0	6	122	0	0	5	17	139558	40000	10	10	10	10000	20000	40010	140261	140261	140261	140037	140261
70024	140260	1049	0	0	1	0	0	0	0	0	0	1	0	1	0	0	140021	139716	139552	129565	25	80027	40010	30003	10000	30010	30000	10000	1264728	6703613	20111930	1	140012	0	140260	140069	130781	3	131384	70010	30020	10000	30000	60020	10000	30000	140036	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	1	0	0	10000	1	0	0	3140	0	0	5	120	0	0	17	7	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261
70024	140260	1050	0	0	0	0	0	0	0	0	0	1	0	1	0	0	140245	139716	139326	129565	25	80013	40010	30000	10000	30010	30000	10000	1266662	6703613	20079595	1	140236	0	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	0	5	122	0	0	17	17	139558	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261
70024	140260	1050	0	0	0	0	0	0	0	0	0	1	0	1	0	0	140021	139716	139552	129565	25	80013	40010	30000	10000	30010	30000	10000	1266662	6703613	20079595	1	140236	0	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	0	6	122	0	0	11	17	139781	40000	10	10	10	10000	20000	40010	140037	140261	140261	140261	140037
70024	140260	1051	0	0	0	0	0	1	1	0	0	16	0	1	0	0	140245	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6692839	20111930	1	140236	0	140036	140260	130554	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	3140	0	0	7	122	0	0	6	17	139834	40000	10	10	10	10000	20000	40010	140219	140037	140304	140261	140261
70025	140296	1050	0	0	0	0	0	0	0	0	0	1	0	1	0	0	140021	139716	139552	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6692839	20111930	1	140236	0	140036	140036	130777	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	1	0	3140	0	0	17	122	0	0	7	17	139558	40000	0	10	10	10000	20000	40010	140261	140261	140261	140155	140261
70024	140260	1051	0	0	0	0	0	0	0	0	0	10	0	1	0	0	140245	139747	139561	129565	25	80013	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	0	140260	140260	130777	3	131384	70010	30020	10000	30000	60020	10000	30000	140036	140260	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	3140	0	0	7	122	0	0	5	17	139781	40000	10	10	10	10000	20000	40010	140261	140037	140261	140261	140261
70024	140260	1050	0	0	0	0	0	0	0	0	0	0	0	0	0	0	140245	139716	139326	129565	25	80010	40010	30003	10000	30010	30000	10000	1266662	6703613	20111930	1	140236	0	140260	140260	130554	3	131384	70010	30020	10000	30000	60020	10000	30000	140260	140036	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	0	10000	1	0	0	3140	0	1	18	122	0	0	17	7	139781	40000	10	10	10	10000	20000	40010	140261	140261	140261	140261	140261

Test 4: throughput

Count: 8

Code:

  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]
  ld2r { v0.8b, v1.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5009

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	40070	300	1	1	1	0	1	1	0	79	1	0	1	40040	15	18	0	6	0	25	240204	100	160054	80000	100	160000	80000	500	418423	5440824	1	40051	0	40054	40055	9979	3	10023	240100	200	80000	160000	200	80000	160000	40070	40070	1	1	80201	100	99	100	100	80000	80000	0	100	80149	17	41	80069	0	1	1	34	80052	6	1	53	0	16	1	0	5110	0	2	16	2	2	40052	6	0	0	80000	160000	100	40056	40164	40056	40056	40071
240204	40055	300	1	1	0	0	1	1	0	41	1	0	1	40055	14	0	30	6	0	25	240204	100	160104	80000	100	160000	80000	500	415845	5440824	1	40051	0	40070	40070	9979	3	10023	240100	200	80000	160000	200	80000	160000	40070	40055	1	1	80201	100	99	100	100	80000	80000	0	100	80017	18	56	80053	1	0	0	73	80178	6	1	69	44	16	0	0	5110	0	2	16	2	2	40067	6	6	0	80000	160000	100	40071	40056	40071	40071	40071
240204	40055	300	1	0	0	0	0	0	0	78	1	0	1	40055	21	18	31	6	0	25	240196	100	160106	80000	100	160000	80000	500	418423	4000034	1	40051	0	40070	40070	9974	3	10028	240100	200	80000	160000	200	80000	160000	40070	40065	1	1	80201	100	99	100	100	80000	80000	0	100	80018	16	0	80038	0	0	2	75	80052	0	0	37	0	16	1	0	5110	0	2	16	2	2	40052	0	6	0	80000	160000	100	40071	40071	40071	40056	40071
240204	40070	300	1	1	0	0	1	1	0	79	1	0	2	40055	15	18	30	6	0	25	240202	100	160096	80000	100	160000	80000	500	415827	5440822	1	40051	0	40055	40055	9979	3	10028	240100	200	80000	160000	200	80000	160000	40070	40055	1	1	80201	100	99	100	100	80000	80000	0	100	80018	16	56	80068	1	0	1	1060	80053	0	1	69	44	16	1	0	5110	0	2	16	2	2	40067	0	6	0	80000	160000	100	40056	40056	40056	40071	40066
240204	40055	300	1	1	0	0	0	0	0	78	0	0	1	40040	14	18	30	0	0	25	240196	100	160104	80000	100	160000	80000	500	415872	4000034	1	40051	0	40055	40070	9973	3	10013	240100	200	80000	160000	200	80000	160000	40070	40055	1	1	80201	100	99	100	100	80000	80000	0	100	80148	18	0	80038	0	0	0	75	80022	6	1	53	0	16	0	0	5110	0	2	16	2	2	40067	0	0	0	80000	160000	100	40071	40071	40071	40071	40056
240204	40065	299	1	0	1	0	0	0	0	78	0	0	1	40040	14	0	0	0	0	25	240204	100	160048	80000	100	160289	80000	500	415842	5440822	1	40051	0	40070	40055	9973	3	10014	240100	200	80000	160000	200	80000	160000	40056	40070	1	1	80201	100	99	100	100	80000	80000	0	100	80017	17	0	80069	1	0	1	57	80052	6	0	68	0	16	1	0	5110	0	2	16	2	2	40067	6	6	0	80000	160000	100	40071	40071	40071	40056	40056
240204	40070	300	1	0	0	0	1	0	0	79	0	0	1	40055	14	18	0	6	0	25	240194	100	160104	80000	100	160000	80000	500	419328	4000032	1	40051	0	40070	40070	9973	3	10012	240100	200	80000	160000	200	80000	160000	40070	40055	1	1	80201	100	99	100	100	80000	80000	0	100	80018	16	56	80068	2	0	0	41	80051	6	1	68	0	16	1	0	5110	0	2	16	2	2	40052	6	6	0	80000	160000	100	40071	40071	40071	40200	40056
240204	40070	300	1	1	0	0	0	1	0	79	1	0	0	40055	14	18	30	0	0	25	240204	100	160104	80000	100	160000	80000	500	415605	5440824	1	40150	0	40055	40055	9979	3	10013	240100	200	80000	160000	200	80000	160000	40055	40055	1	1	80201	100	99	100	100	80000	80000	0	100	80017	16	56	80069	1	0	0	42	80022	6	1	37	44	16	1	0	5110	0	2	16	3	2	40052	0	0	0	80000	160000	100	40071	40071	40071	40071	40056
240204	40070	300	1	0	0	0	1	1	0	78	0	0	1	40040	21	18	30	6	0	25	240196	100	160096	80000	100	160000	80000	500	418423	4000036	1	40051	0	40055	40055	9973	3	10013	240100	200	80000	160000	200	80000	160000	40055	40070	1	1	80201	100	99	100	100	80000	80000	0	100	80018	18	56	80038	0	0	0	42	80022	6	0	68	44	16	1	0	5110	0	2	16	2	2	40067	6	9	0	80000	160000	100	40056	40056	40071	40071	40056
240204	40201	300	1	0	0	0	0	1	0	41	0	0	0	40039	14	18	0	1	0	25	240156	100	160104	80000	100	160000	80000	500	418418	5440822	1	40051	0	40070	40070	9973	3	10013	240100	200	80000	160000	200	80000	160000	40070	40070	1	1	80201	100	99	100	100	80000	80000	0	100	80016	16	56	80068	0	1	0	72	80053	0	1	38	41	16	0	0	5110	0	2	16	2	2	40067	6	6	0	80000	160000	100	40071	40066	40071	40071	40071

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	1e	1f	22	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	40055	300	0	0	0	1	0	0	30	0	0	0	40040	0	11	11	0	25	240010	10	160054	80000	10	160000	80000	50	418518	1845674	0	40036	0	40055	40055	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	0	80024	6	1	24	30	0	0	5020	0	0	17	16	15	13	40052	6	6	80000	160000	10	40056	40056	40056	40056	40056
240024	40055	300	0	1	0	1	1	0	20	0	0	2	40050	2	18	0	1	25	240034	10	160024	80000	10	160000	80000	50	415287	5440082	0	40036	0	40055	40055	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40055	40055	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	30	80000	0	0	0	24	80027	6	1	16	41	16	0	5020	0	0	13	16	12	12	40044	9	0	80000	160000	10	40048	40066	40066	40066	40066
240024	40065	300	1	0	0	0	1	0	62	0	1	3	40050	1	18	18	1	25	240088	10	160082	80000	10	160000	80000	50	415287	5440082	0	40036	0	40055	40055	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40055	40056	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80024	0	1	0	24	80024	6	0	16	41	16	1	5020	0	0	13	16	17	13	40044	9	0	80000	160000	10	40048	40048	40048	40066	40066
240024	40065	300	1	0	0	0	0	0	63	0	0	0	40050	2	18	18	1	25	240092	10	160082	80000	10	160000	80000	50	415825	2720036	0	40028	0	40065	40065	9996	0	3	10027	240010	20	80000	160000	20	80000	160000	40065	40065	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	80024	0	0	0	24	80024	6	0	16	41	16	2	5020	0	0	15	16	13	13	40062	9	9	80000	160000	10	40066	40066	40048	40048	40048
240024	40065	299	1	0	0	0	0	0	30	0	1	0	40040	0	11	18	1	25	240034	10	160082	80000	10	160000	80000	50	418617	5440148	0	40046	0	40065	40065	9996	0	3	10035	240010	20	80000	160000	20	80000	160000	40055	40047	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	24	80024	0	1	16	41	0	0	5020	0	0	12	16	12	12	40038	6	6	80000	160000	10	40056	40056	40042	40056	40042
240024	40055	300	0	1	1	0	0	0	30	0	1	0	40041	0	11	11	0	25	240064	10	160054	80000	10	160000	80000	50	418692	3920014	0	40046	0	40065	40065	9996	0	27	10045	240010	20	80000	160000	20	80000	160000	40065	40065	1	1	80021	10	9	10	10	80000	80000	0	10	80016	17	41	80053	1	0	2	57	80038	6	1	24	30	0	0	5020	0	0	13	16	14	14	40038	6	0	80000	160000	10	40066	40066	40066	40048	40048
240024	40065	300	1	0	0	0	0	0	30	0	0	0	40026	0	0	0	0	25	240064	10	160000	80000	10	160000	80000	50	418745	3920014	0	40046	0	40047	40065	9996	0	3	10045	240010	20	80000	160000	20	80000	160000	40065	40065	1	1	80021	10	9	10	10	80000	80000	0	10	80017	18	42	80016	0	0	1	57	80037	6	1	24	0	0	0	5020	0	0	16	16	10	16	40062	9	9	80000	160000	10	40056	40056	40056	40042	40056
240024	40055	300	0	1	1	0	0	0	19	0	1	2	40032	2	18	18	1	25	240064	10	160054	80000	10	160000	80000	50	415825	3920014	1	40046	0	40065	40047	9996	0	3	10027	240010	20	80000	160000	20	80000	160000	40065	40065	1	1	80021	10	9	10	10	80000	80000	0	10	80016	17	41	80052	1	0	1	56	80037	6	1	24	30	0	0	5020	0	0	16	16	15	11	40052	6	0	80000	160000	10	40056	40056	40056	40042	40056
240024	40041	300	0	1	1	0	0	0	62	0	0	3	40050	2	0	18	1	25	240090	10	160024	80000	10	160000	80000	50	418658	5440080	0	40036	0	40055	40055	9996	0	3	10027	240010	20	80000	160000	20	80000	160000	40047	40065	1	1	80021	10	9	10	10	80000	80000	0	10	80017	17	41	80053	1	0	1	57	80037	6	1	24	30	0	0	5020	0	0	17	16	15	15	40052	6	6	80000	160000	10	40056	40056	40056	40042	40056
240024	40055	300	0	1	1	1	1	0	20	0	1	3	40050	2	0	18	1	25	240092	10	160082	80000	10	160000	80000	50	418617	5440082	0	40036	0	40056	40055	9996	0	3	10021	240010	20	80000	160000	20	80000	160000	40055	40041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	30	80024	0	0	0	936	80024	6	1	53	41	16	2	5020	0	0	10	16	10	14	40062	0	0	80000	160000	10	40066	40066	40066	40049	40066

LD2R (8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations