Firestorm: LD2R (8H) measurements

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.004

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	51	schedule uop (52)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	f5	f6	f7	f8	fd
63005	29519	221	0	23	0	0	23	0	1	1	0	0	2	0	0	0	4852	28781	0	0	1	17182	3008	2000	1000	2000	1000	5000	23866	2	22766	29091	29252	3	10	3000	1000	2000	1000	2000	29163	29163	1	1	61001	1000	1000	0	1000	0	2	1000	0	1	0	3	1000	0	0	3	0	0	12991	9285	6846	3229	9	78	20793	3072	3826	15	60	54	28425	16387	13743	14958	1000	2000	29411	29289	29452	29348	29256
63004	29386	220	0	23	0	0	21	0	1	1	0	0	2	0	0	0	4638	28815	0	0	0	17287	3000	2004	1000	2000	1000	5000	23808	2	22662	29106	29278	3	10	3000	1000	2000	1000	2000	29121	29088	1	1	61001	1000	1000	0	1000	0	0	1000	0	3	0	0	1000	0	0	0	0	0	12828	9026	6892	3199	9	60	20567	3050	3827	21	57	62	28303	16410	14101	15045	1000	2000	29295	29227	29211	29257	29225
63004	29392	219	0	21	0	0	21	0	0	0	0	0	0	0	0	0	4591	28766	0	0	0	17246	3000	2004	1000	2000	1000	5000	23819	0	22689	29125	29228	3	10	3000	1000	2000	1000	2000	29194	29248	1	1	61001	1000	1000	0	1000	0	3	1000	0	2	0	3	1000	2	0	2	0	0	12857	9141	6869	3104	6	59	20716	3061	3828	25	59	56	28402	16374	13982	14723	1000	2000	29272	29268	29297	29285	29295
63004	29276	219	0	23	0	0	17	0	0	0	0	0	3	0	0	0	4572	28748	0	0	0	17188	3000	2006	1000	2000	1000	5000	23928	0	22717	29132	29207	3	10	3000	1000	2000	1000	2000	29198	29179	1	1	61001	1000	1000	0	1000	0	3	1000	0	1	0	3	1000	3	1	2	0	0	12870	9245	6805	3017	7	61	20555	3070	3827	22	55	59	28381	16644	14032	15072	1000	2000	29301	29333	29309	29347	29273
63004	29223	220	0	23	0	0	17	0	0	0	0	0	0	0	1	0	4633	28768	0	1	0	17180	3000	2004	1000	2000	1000	5000	23812	3	22662	29007	29303	3	10	3000	1000	2000	1000	2000	29223	29161	1	1	61001	1000	1000	0	1000	0	3	1000	0	3	0	3	1000	0	1	2	0	0	12990	9161	6864	3032	8	65	20683	3070	3824	17	55	61	28383	16447	14164	15174	1000	2000	29136	29252	29312	29343	29259
63004	29333	219	0	26	0	0	18	0	0	0	0	0	4	0	1	0	4834	28832	0	0	0	17252	3000	2006	1000	2000	1000	5000	23864	0	22705	29076	29204	3	10	3000	1000	2000	1000	2000	29235	29187	1	1	61001	1000	1000	0	1000	0	3	1000	0	28	0	6	1000	3	0	2	0	0	12912	9090	6835	3042	9	53	20569	3078	3826	12	47	53	28344	16356	13966	15177	1000	2000	29289	29293	29309	29356	29208
63004	29255	219	0	18	0	0	18	0	0	0	0	0	0	0	0	0	4598	28710	0	0	0	17309	3004	2004	1000	2000	1000	5000	23890	4	22700	29043	29301	3	10	3000	1000	2000	1000	2000	29218	29220	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	0	93	1000	2	0	2	0	0	12838	9235	6838	3185	9	55	20723	3054	3823	13	55	57	28365	16655	13794	15112	1000	2000	29247	29212	29336	29236	29238
63004	29375	220	0	17	0	0	16	0	0	1	0	0	0	0	0	0	4630	28786	0	0	0	17128	3000	2004	1000	2000	1000	5000	23868	4	22726	29203	29363	3	10	3000	1000	2000	1000	2000	29191	29123	1	1	61001	1000	1000	0	1000	0	2	1001	0	34	0	6	1000	2	0	0	0	0	13043	9249	6808	3185	12	59	20635	3051	3825	18	56	49	28376	16176	13683	15022	1000	2000	29268	29315	29272	29324	29271
63004	29298	220	0	21	0	0	24	0	0	0	0	0	0	0	0	0	4601	28742	0	0	0	17194	3000	2004	1000	2000	1000	5000	23868	0	22714	29059	29299	3	10	3000	1000	2000	1000	2000	29101	29126	1	1	61001	1000	1000	0	1000	0	2	1000	0	2	0	0	1000	3	0	2	0	0	12891	9655	6861	3067	11	53	20671	3072	3822	20	56	57	28418	16117	14063	15041	1000	2000	29369	29330	29307	29323	29329
63004	29411	220	0	25	0	0	20	0	0	0	0	0	0	0	0	0	4609	28956	0	0	0	17226	3000	2004	1000	2000	1000	5000	23888	0	22751	29081	29361	3	10	3000	1000	2000	1000	2000	29312	29163	1	1	61001	1000	1000	0	1000	0	2	1000	0	24	0	6	1000	3	0	0	0	0	12972	9059	6837	3230	7	57	20649	3101	3827	22	60	56	28393	16412	13829	15285	1000	2000	29281	29262	29290	29325	29271

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	0e	0f	18	19	1e	1f	22	23	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140051	1049	0	0	0	0	0	0	0	0	0	1	0	140036	139608	139325	129347	25	80103	40100	30003	10000	30100	30000	10000	1264310	6693731	20081843	0	140030	0	140054	140095	130563	0	3	131150	70100	30200	10000	30000	60200	10000	30000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	1	0	0	3210	2	128	2	3	139566	40000	0	11	0	10000	20000	40100	140052	140036	140036	140055	140036
70204	140054	1049	0	0	0	0	0	0	0	4	108	0	0	140039	139608	139325	129363	25	80103	40100	30003	10000	30100	30000	10000	1264390	6693731	20081843	0	140011	0	140054	140051	130559	0	3	131150	70100	30200	10000	30000	60200	10000	30000	140054	140054	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	0	0	2	0	0	0	3210	3	133	3	3	139566	40000	0	0	13	10000	20000	40100	140055	140055	140036	140036	140055
70204	140054	1049	0	0	0	0	0	0	0	1	0	0	0	140020	139561	139325	129435	25	80103	40100	30003	10000	30100	30000	10000	1264399	6693731	20081843	0	140011	0	140054	140054	130531	0	3	131150	70100	30200	10000	30000	60200	10000	30000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	0	3210	3	133	3	3	139566	40000	0	13	13	10000	20000	40100	140036	140055	140055	140036	140036
70204	140035	1049	0	0	0	0	0	0	0	0	0	0	0	140020	139404	139325	129363	25	80103	40106	30003	10000	30100	30000	10000	1264390	6693584	20079451	0	140027	0	140054	140054	130562	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140051	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	3	10000	0	1	0	0	0	0	3210	3	128	3	3	139566	40000	13	13	0	10000	20000	40100	140036	140113	140055	140036	140055
70204	140054	1049	0	0	0	0	0	0	0	1	0	0	0	140039	139608	139344	129363	150	80103	40100	30003	10000	30100	30000	10000	1264390	6692791	20079451	0	140030	0	140054	140051	130562	0	3	131150	70100	30200	10000	30000	60200	10000	30000	140051	140143	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	0	3247	3	133	3	3	139544	40000	13	10	0	10000	20000	40100	140055	140055	140036	140052	140036
70204	140054	1049	0	0	0	0	0	0	0	0	0	1	0	140039	139608	139344	129365	25	80103	40100	30000	10000	30100	30000	10000	1264390	6693731	20081843	1	140035	0	140054	140051	130562	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140051	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	10000	1	1	0	0	0	0	3210	3	128	3	3	139572	40000	10	13	13	10000	20000	40100	140055	140052	140036	140052	140055
70204	140054	1049	0	0	0	0	0	0	0	1	0	0	0	140020	139608	139346	129363	25	80103	40100	30000	10000	30100	30000	10000	1264390	6693731	20079595	0	140586	0	140051	140051	130531	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140037	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	0	0	10000	0	3	10000	1	1	4	0	0	0	3237	3	128	3	3	139564	40000	0	13	13	10000	20000	40100	140036	140057	140055	140055	140057
70204	140054	1049	0	0	0	0	0	0	0	1	0	0	0	140020	139405	139352	129411	25	80100	40100	30006	10000	30100	30000	10000	1264390	6693731	20079451	0	140030	0	140035	140035	130562	0	3	131150	70100	30200	10000	30000	60200	10000	30000	140059	140051	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	3	10000	1	0	0	0	0	0	3210	3	128	3	3	139810	40043	0	0	13	10000	20000	40100	140273	140474	140036	140162	140255
70204	140054	1049	0	0	0	0	0	0	0	12	0	0	0	140041	139608	139344	129366	25	80103	40100	30003	10000	30100	30000	10000	1264390	6693731	20079451	1	140011	0	140102	140054	130531	0	3	131126	70100	30200	10000	30000	60200	10000	30000	140035	140035	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	2	0	10000	1	1	0	0	0	0	3210	7	143	3	3	139564	40000	13	0	13	10000	20000	40100	140055	140055	140036	140055	140036
70204	140054	1049	0	0	0	0	0	0	0	0	0	0	0	140036	139561	139325	129363	153	80122	40100	30003	10000	30100	30000	10000	1264390	6693974	20079451	0	140030	0	140051	140037	130567	0	3	131150	70100	30200	10000	30000	60200	10000	30000	140054	140051	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	10000	1	1	0	0	0	0	3210	3	128	5	3	139567	40000	13	13	13	10000	20000	40100	140055	140039	140435	140055	140061

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140102	1049	0	1	0	0	0	0	61	1	0	140039	139564	139346	129357	25	80010	40010	30009	10000	30290	30000	10000	1264819	6693731	20081843	0	140030	0	140054	140035	130572	3	131161	70010	30020	10000	30000	60020	10000	30000	140054	140035	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	3	10000	1	1	0	3140	6	121	2	4	139645	40000	10	10	11	10000	20000	40010	140055	140062	140052	140055	140036
70024	140035	1049	0	0	0	0	0	0	1	0	0	140020	139564	139325	129360	25	80013	40010	30003	10000	30010	30000	10000	1264819	6693584	20081843	0	140011	0	140054	140035	130572	3	131176	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	1	0	0	3140	4	120	4	2	139614	40000	13	13	13	10000	20000	40010	140036	140036	140052	140055	140036
70024	140035	1049	0	0	0	0	0	0	1	1	0	140039	139564	139325	129360	25	80013	40010	30000	10000	30157	30000	10000	1264819	6695888	20081843	0	140030	0	140054	140054	130572	3	131161	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10000	1	1	0	3140	4	121	4	2	139576	40000	13	10	13	10000	20000	40010	140055	140036	140055	140036	140052
70024	140054	1049	0	0	0	0	0	0	1	0	0	140039	139564	139346	129360	25	80013	40010	30003	10000	30010	30000	10000	1264783	6693731	20081843	0	140030	0	140051	140054	130553	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	10000	0	0	10001	1	1	0	3140	4	121	4	2	139580	40000	10	0	0	10000	20000	40010	140055	140036	140055	140036	140055
70024	140054	1049	0	0	0	0	0	0	0	0	0	140020	139564	139344	129341	25	80013	40010	30003	10000	30010	30000	10000	1264819	6693731	20082304	0	140030	0	140035	140054	130553	3	131179	70010	30020	10000	30000	60020	10000	30000	140035	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	1	0	3140	4	121	4	2	139573	40000	13	13	13	10000	20000	40010	140055	140055	140036	140055	140055
70024	140054	1049	0	0	0	1	0	0	1	1	0	140020	139487	139346	129360	25	80013	40010	30000	10002	30010	30000	10000	1264819	6693731	20081843	0	140011	0	140054	140054	130572	3	131161	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	3	10000	1	1	0	3140	4	121	4	5	139573	40000	13	13	10	10000	20000	40010	140036	140055	140055	140052	140036
70024	140035	1049	0	0	0	0	0	0	1	1	0	140039	139487	139346	129360	25	80013	40010	30003	10000	30010	30000	10000	1264819	6692791	20079451	0	140030	0	140054	140035	130572	3	131179	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	6	10000	1	1	1	3140	5	121	4	2	139593	40000	13	0	13	10000	20000	40010	140036	140055	140055	140036	140036
70024	140054	1049	0	0	0	0	0	0	0	0	0	140036	139564	139325	129360	25	80013	40010	30003	10000	30010	30000	10000	1264719	6692791	20079451	0	140031	0	140054	140051	130553	3	131179	70010	30020	10000	30000	60020	10000	30000	140035	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	0	0	3140	4	120	2	4	139573	40000	0	0	13	10000	20000	40010	140036	140036	140055	140055	140055
70025	140051	1049	0	0	0	0	0	0	10	1	0	140020	139564	139344	129341	25	80010	40010	30003	10000	30010	30000	10000	1264719	6692791	20082304	1	140030	0	140035	140054	130553	3	131179	70010	30020	10000	30000	60020	10000	30189	140054	140051	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	1	10000	0	0	10000	0	0	0	3140	2	120	2	4	139573	40000	13	0	13	10000	20000	40010	140036	140055	140036	140055	140055
70024	140035	1049	0	0	0	0	0	0	6	0	0	140020	139564	139346	129360	25	80013	40010	30003	10000	30010	30000	10000	1264819	6693731	20081843	1	140030	3	140054	140054	130572	3	131176	70010	30020	10000	30000	60020	10000	30000	140054	140051	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	1	10000	0	0	10000	1	1	0	3140	4	121	4	4	139627	40000	10	0	13	10000	20000	40010	140055	140055	140055	140036	140055

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0685

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140496	1053	1	1	1	1	1	0	0	2	0	0	1	140670	140279	139974	129762	25	80103	40100	30006	10000	30100	30000	10000	1269613	6723821	20172574	0	140658	0	140685	140458	131190	3	131553	70100	30200	10000	30000	60200	10000	30000	140685	140458	1	1	50201	100	99	100	40100	10000	10000	1	100	10001	2	0	10002	0	0	0	1	10000	1	1	1	1	1	0	0	3210	2	129	1	1	139969	40000	13	10	13	10000	20000	40100	140459	140686	140686	140683	140459
70204	140682	1054	1	1	0	0	0	0	0	1	0	0	0	140670	139866	139754	129626	25	80106	40100	30003	10000	30100	30000	10000	1268087	6723821	20172718	0	140661	0	140458	140685	131190	3	131780	70100	30200	10000	30000	60200	10000	30000	140682	140685	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	0	10001	0	0	0	1	10000	1	1	1	1	0	0	0	3210	1	129	1	1	140192	40000	10	10	13	10000	20000	40100	140459	140686	140686	140686	140686
70204	140685	1054	1	1	1	1	0	0	0	1	0	0	0	140488	140279	139972	129762	25	80106	40100	30006	10000	30100	30000	10000	1269962	6713069	20172574	1	140434	0	140682	140682	131187	3	131553	70100	30200	10000	30000	60200	10000	30000	140682	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	1	10001	0	0	1	1	10000	1	1	0	1	0	0	0	3210	1	129	1	1	139969	40000	13	10	0	10000	20000	40100	140686	140686	140459	140459	140686
70204	140682	1053	1	1	1	0	0	0	0	1	1	0	0	140443	139866	139974	129987	25	80103	40100	30006	10000	30100	30000	10000	1269962	6723965	20172574	1	140434	0	140685	140685	131187	3	131777	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	0	10002	0	0	0	1	10000	1	1	1	1	1	0	0	3210	1	129	2	1	140192	40000	13	10	0	10000	20000	40100	140686	140686	140459	140459	140459
70204	140685	1054	1	1	1	1	0	0	0	1	0	0	0	140670	140279	139974	129987	25	80106	40100	30006	10000	30100	30000	10000	1269946	6723821	20140439	1	140661	0	140682	140458	130964	3	131780	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10003	3	1	10001	0	0	2	1	10000	1	1	0	1	0	0	0	3210	1	129	1	1	139969	40000	0	13	13	10000	20000	40100	140683	140686	140686	140723	140459
70204	140690	1053	1	1	1	0	0	0	0	1	1	0	0	140670	140276	139974	129987	25	80106	40100	30006	10000	30100	30000	10000	1269962	6723965	20172574	1	140661	0	140387	140685	131191	3	131780	70100	30200	10000	30000	60200	10000	30000	140685	140461	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	0	0	1	10000	1	1	0	1	1	0	0	3210	1	129	1	1	140192	40000	13	0	10	10000	20000	40100	140686	140459	140686	140686	140683
70204	140458	1054	1	0	1	0	0	0	0	1	0	0	0	140443	139942	139974	129762	25	80106	40100	30003	10000	30100	30000	10000	1269962	6723965	20172574	1	140434	0	140685	140685	131189	3	131777	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	0	10002	0	0	0	1	10002	1	1	0	1	0	0	1	3210	1	129	4	1	140195	40000	13	13	0	10000	20000	40100	140689	140459	140686	140683	140683
70204	140458	1053	1	1	1	0	0	0	0	2	1	0	1	140670	140276	139972	129987	25	80103	40100	30006	10000	30100	30000	10000	1268087	6723965	20172574	0	140434	0	140685	140458	131190	3	131553	70100	30200	10000	30000	60200	10000	30000	140458	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	2	0	10001	0	0	0	1	10000	1	1	1	1	1	0	0	3210	1	129	1	1	139969	40000	10	13	10	10000	20000	40100	140686	140643	140683	140459	140459
70204	140458	1052	1	1	1	1	0	0	0	1	0	0	0	140670	140279	139974	129987	25	80106	40100	30006	10000	30100	30000	10000	1269962	6713069	20140295	0	140661	0	140685	140690	131190	3	131553	70100	30200	10000	30000	60200	10000	30000	140685	140682	1	1	50201	100	99	100	40100	10000	10000	0	100	10002	1	0	10001	0	0	2	1	10000	0	1	1	1	2	0	0	3210	1	129	1	1	139969	40000	0	10	0	10000	20000	40100	140459	140686	140683	140686	140459
70204	140685	1052	1	1	1	0	0	0	0	11	0	0	0	140669	140279	139747	129987	25	80106	40100	30003	10000	30100	30000	10000	1269962	6713069	20173746	0	140666	0	140685	140690	131190	3	131553	70100	30200	10000	30000	60200	10000	30000	140685	140458	1	1	50201	100	99	100	40100	10000	10000	0	100	10001	1	1	10001	0	0	0	1	10000	1	1	0	1	0	0	0	3210	1	129	1	1	140192	40000	13	13	13	10000	20000	40100	140686	140686	140459	140686	140686

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0679

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140464	1052	0	0	0	0	0	0	0	1	0	1	0	0	1	140666	140232	139970	129981	25	80016	40010	30006	10000	30010	30000	10000	1270547	6723772	20171978	1	140654	140678	140681	131196	3	131857	70010	30020	10000	30000	60020	10000	30000	140458	140458	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	1	1	10001	0	2	1	10000	1	1	1	1	0	0	3140	7	122	2	6	139978	40000	6	6	9	10000	20000	40010	140459	140459	140679	140682	140682
70024	140458	1053	1	0	1	0	1	0	0	8	0	0	0	0	1	140443	140175	139747	129762	25	80013	40010	30003	10000	30010	30000	10000	1268578	6723772	20171978	1	140654	140458	140678	130974	3	131583	70010	30020	10000	30000	60020	10000	30000	140458	140678	1	1	50021	10	9	10	40010	10000	10000	1	10	10001	2	1	10001	0	2	1	10000	1	1	0	1	1	0	3140	2	122	2	6	140200	40000	0	6	0	10000	20000	40010	140682	140682	140459	140682	140682
70024	140678	1054	1	1	1	0	0	0	0	1	0	0	0	0	0	140663	140173	139970	129981	25	80016	40018	30006	10000	30010	30000	10000	1270454	6723772	20172426	1	140654	140681	140458	131196	3	131862	70010	30179	10000	30000	60020	10000	30000	140681	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10003	4	1	10003	0	1	25	10000	1	1	1	1	1	0	3140	2	121	2	6	140200	40000	9	9	0	10000	20000	40010	140682	140459	140682	140459	140459
70024	140681	1053	1	0	0	0	0	0	0	2	0	1	0	0	0	140666	140173	139747	129741	25	80016	40010	30006	10000	30010	30000	10000	1268578	6723772	20140295	0	140434	140461	140681	130974	3	131859	70010	30020	10000	30000	60020	10000	30000	140681	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	0	10001	0	0	1	10000	1	1	1	1	1	0	3140	2	121	2	2	140200	40000	6	6	9	10000	20000	40010	140682	140687	140459	140682	140682
70024	140684	1053	1	0	0	0	0	0	0	2	0	1	0	0	0	140663	140173	139967	129984	25	80016	40010	30006	10000	30010	30000	10000	1270454	6713069	20140295	1	140434	140681	140458	131196	3	131886	70010	30020	10000	30000	60020	10000	30000	140681	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10006	0	0	1	10000	0	1	1	1	2	0	3140	2	122	2	2	139978	40000	6	0	9	10000	20000	40010	140682	140686	140682	140459	140679
70024	140458	1054	1	1	0	0	0	0	0	2	0	1	0	0	0	140669	140176	139967	129984	25	80013	40010	30003	10000	30152	30000	10000	1270454	6723772	20171978	1	140657	140681	140681	130974	3	131802	70010	30020	10000	30000	60332	10000	30000	140678	140681	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10003	4	2	1	10000	0	1	1	1	2	0	3140	2	121	2	2	140200	40000	9	9	0	10000	20000	40010	140682	140459	140679	140459	140459
70024	140681	1052	1	1	2	0	0	0	0	1	0	1	0	0	0	140443	139826	139970	129762	25	80016	40010	30006	10000	30010	30000	10050	1270547	6723772	20171978	1	140657	140678	140681	131196	19	131802	70010	30020	10053	30000	60020	10000	30000	140681	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	1	1	10002	3	3	1	10000	0	1	0	1	6	0	3140	2	122	2	6	140201	40000	9	0	9	10000	20000	40010	140682	140744	140683	140682	140682
70024	140681	1052	1	1	0	0	0	0	0	13	0	0	0	0	0	140443	140232	139747	129984	25	80013	40010	30003	10000	30010	30148	10000	1270454	6723772	20172426	0	140654	140458	140458	131198	3	131858	70010	30179	10000	30000	60020	10000	30000	140681	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	1	0	1	10000	1	1	1	1	0	0	3140	6	122	2	2	140200	40000	6	9	0	10000	20000	40010	140682	140460	140683	140529	140459
70024	140681	1054	1	0	1	1	0	0	0	7	0	1	0	0	1	140666	140173	139970	129984	25	80016	40010	30003	10000	30010	30000	10000	1270454	6723772	20171978	1	140434	140458	140458	131196	3	131872	70010	30020	10000	30000	60020	10000	30000	140681	140458	1	1	50021	10	9	10	40010	10000	10000	0	10	10002	2	1	10002	0	0	1	10000	1	1	0	1	1	0	3140	2	121	2	2	140200	40008	9	6	9	10000	20000	40010	140682	140679	140682	140682	140687
70024	140458	1054	1	1	1	0	0	0	0	2	0	1	0	0	0	140667	140232	139970	129984	25	80013	40010	30006	10000	30010	30000	10000	1270454	6723916	20176621	0	140434	140678	140458	131196	3	131802	70010	30020	10000	30000	60020	10000	30000	140681	140678	1	1	50021	10	9	10	40010	10000	10000	0	10	10001	1	1	10002	0	1	1	10001	0	1	1	1	1	0	3140	2	122	2	6	140200	40000	6	9	9	10000	20000	40010	140679	140679	140679	140459	140682

Test 4: throughput

Count: 8

Code:

  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]
  ld2r { v0.8h, v1.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5008

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0e	0f	19	1e	1f	22	23	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	40073	300	0	1	1	0	0	358	0	1	0	1	40049	0	8	25	240182	100	160082	80000	100	160000	80000	500	418985	4560014	1	40040	40041	40059	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40059	40059	1	1	80201	100	99	100	100	80000	80000	1	100	80000	37	0	80000	0	0	0	80035	6	1	31	41	0	5110	1	16	1	1	40061	14	0	80000	160000	100	40060	40065	40065	40065	40060
240204	40064	299	0	0	1	1	0	0	0	0	0	1	40049	0	8	25	240182	100	160070	80000	100	160000	80000	500	418996	5439994	1	40022	40064	40064	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40041	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	0	80031	0	0	35	80000	6	1	31	37	0	5110	1	16	1	1	40038	10	10	80000	160000	100	40065	40042	40065	40065	40042
240204	40059	300	0	0	0	0	0	130	0	1	0	1	40044	10	8	25	240182	100	160082	80000	100	160000	80000	500	417950	5439994	1	40045	40041	40064	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40064	40041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	0	80035	0	0	35	80035	0	0	35	0	0	5110	1	16	1	1	40061	14	14	80000	160000	100	40065	40065	40042	40060	40065
240204	40064	300	0	0	0	0	0	206	0	1	0	0	40049	8	0	25	240182	100	160082	80000	100	160000	80000	500	418996	1845094	1	40022	40041	40041	9973	31	3	10022	240100	200	80000	160000	200	80000	160000	40041	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	0	80000	0	0	35	80035	0	1	35	41	0	5110	1	16	1	1	40061	14	14	80000	160000	100	40042	40042	40060	40042	40065
240204	40059	300	0	0	0	0	0	117	0	1	0	0	40026	10	8	25	240100	100	160082	80000	100	160000	80000	500	418973	5439994	1	40045	40059	40059	9973	0	3	10001	240100	200	80000	160000	200	80000	160000	40064	40041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	0	80035	0	0	35	80000	6	1	35	37	0	5110	1	16	1	1	40061	14	14	80000	160000	100	40065	40042	40065	40065	40065
240204	40041	300	0	0	0	0	0	212	0	1	0	1	40049	8	10	25	240100	100	160070	80000	100	160000	80000	500	418996	1845094	1	40022	40064	40059	9974	0	3	10017	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	0	80000	0	1	0	80035	0	0	31	41	0	5110	1	16	1	1	40038	10	0	80000	160000	100	40065	40065	40060	40065	40042
240204	40041	300	1	0	0	1	0	163	0	0	0	1	40049	8	0	25	240182	100	160082	80000	100	160000	80000	500	417950	1845094	0	40040	40059	40041	9973	0	3	10001	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80201	100	99	100	100	80000	80000	1	100	80000	41	0	80035	0	0	0	80035	6	0	35	41	0	5110	1	16	1	1	40038	14	14	80000	160000	100	40065	40060	40042	40065	40042
240204	40064	300	0	0	0	0	0	161	0	1	0	1	40049	8	8	25	240182	100	160082	80000	100	160000	80000	500	419006	1845094	0	40045	40064	40041	9973	0	3	10022	240100	200	80000	160000	200	80000	160000	40043	40059	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	0	80035	0	0	0	80035	6	1	35	41	0	5110	1	16	1	1	40056	14	0	80000	160000	100	40042	40065	40065	40042	40065
240204	40041	300	0	1	0	0	0	176	0	1	0	1	40049	8	8	25	240182	100	160082	80000	100	160000	80000	500	418996	5439994	0	40022	40064	40064	9973	0	3	10017	240100	200	80000	160000	200	80000	160000	40041	40041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	37	0	80035	0	0	35	80031	6	1	0	41	0	5110	1	16	1	1	40056	10	14	80000	160000	100	40065	40065	40065	40065	40042
240204	40041	300	0	0	0	0	0	37	0	0	0	1	40049	8	0	25	240170	100	160000	80000	100	160000	80000	500	418996	4560014	0	40045	40041	40059	9973	0	3	10006	240100	200	80000	160000	200	80000	160000	40064	40059	1	1	80202	100	99	100	100	80000	80000	0	100	80000	37	0	80000	0	0	35	80031	6	1	0	41	0	5110	1	16	1	1	40061	0	0	80000	160000	100	40060	40042	40042	40065	40065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	43	46	49	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	40059	300	0	0	0	0	0	0	457	0	0	0	1	40054	3	0	0	7	25	240094	10	160024	80000	10	160000	80000	50	419931	5440750	0	40050	0	40047	40069	10001	3	10039	240010	20	80000	160000	20	80000	160000	40059	40059	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	37	80031	0	0	0	0	80035	6	1	0	41	0	0	5020	11	16	17	16	40044	0	13	0	0	80000	160000	10	40070	40048	40048	40070	40070
240024	40069	300	1	1	0	1	1	1	444	0	1	0	1	40044	0	0	0	0	25	240092	10	160000	80000	10	160000	80000	50	419015	4560014	1	40045	0	40064	40064	9996	3	10049	240010	20	80000	160000	20	80000	160000	40069	40047	1	1	80021	10	9	1	10	10	80000	80000	0	10	80017	18	0	80057	2	2	2	20	80000	6	0	16	45	16	1	5020	15	16	15	12	40038	0	14	0	0	80000	160000	10	40065	40042	40065	40065	40060
240024	40059	300	0	0	0	0	0	0	143	0	1	0	1	40044	0	0	8	0	25	240092	10	160070	80000	10	160000	80000	50	419586	1845674	0	40022	0	40041	40041	9996	3	10044	240010	20	80000	160000	20	80000	160000	40064	40059	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	37	80035	0	0	0	35	80031	0	1	31	0	0	0	5020	16	16	14	14	40056	0	14	14	0	80000	160000	10	40065	40060	40042	40060	40065
240024	40041	300	0	0	0	0	0	0	170	0	1	0	1	40044	0	8	8	0	25	240010	10	160082	80000	10	160000	80000	50	419009	5439994	0	40045	0	40064	40064	9996	3	10039	240010	20	80000	160000	20	80000	160000	40041	40041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	0	80035	6	1	31	41	0	0	5020	13	16	10	15	40066	0	13	0	2	80000	160000	10	40048	40048	40070	40048	40070
240024	40069	300	1	1	0	1	0	0	41	0	0	0	0	40049	0	8	8	0	25	240010	10	160000	80000	10	160000	80000	50	419586	5439994	0	40022	0	40064	40064	9996	22	10129	240010	20	80000	160000	20	80000	160000	40064	40042	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	37	80000	0	0	0	0	80035	6	0	0	41	0	0	5020	15	16	16	13	40061	0	10	14	0	80000	160000	10	40042	40060	40065	40065	40065
240024	40059	300	0	0	0	0	0	0	41	0	1	0	1	40049	0	8	8	0	25	240092	10	160082	80000	10	160000	80000	50	418518	5439994	0	40022	0	40041	40041	9996	3	10039	240010	20	80000	160000	20	80000	160000	40064	40041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	0	80000	0	0	0	0	80035	6	1	35	0	0	0	5020	10	16	17	13	40066	0	13	0	2	80000	160000	10	40070	40048	40048	40048	40070
240024	40069	300	1	1	1	1	0	0	71	0	1	0	1	40049	0	10	8	0	25	240010	10	160082	80000	10	160000	80000	50	419721	4560014	0	40045	0	40064	40064	9996	3	10049	240010	20	80000	160000	20	80000	160000	40047	40069	1	1	80021	10	9	1	10	10	80000	80000	0	10	80017	16	0	80057	1	0	0	20	80041	6	0	57	45	16	2	5020	10	16	11	13	40061	0	14	0	0	80000	160000	10	40065	40042	40060	40065	40042
240024	40059	300	0	0	0	0	0	0	364	0	1	0	2	40054	3	9	9	5	25	240034	10	160084	80000	10	160000	80000	50	419769	5440750	0	40028	0	40069	40047	9996	3	10044	240010	20	80000	160000	20	80000	160000	40059	40059	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	37	80035	0	0	0	35	80000	0	1	35	41	0	0	5020	16	16	12	16	40044	0	13	15	2	80000	160000	10	40048	40070	40070	40051	40070
240024	40047	300	1	1	1	1	0	0	151	0	1	0	0	40026	0	8	8	0	25	240092	10	160070	80000	10	160000	80000	50	419586	1975048	0	40022	0	40064	40041	9996	3	10039	240010	20	80000	160000	20	80000	160000	40041	40041	1	1	80021	10	9	0	10	10	80000	80000	0	10	80000	0	37	80000	0	0	0	0	80035	6	1	0	41	0	0	5020	12	16	15	15	40061	0	0	14	0	80000	160000	10	40042	40042	40060	40065	40060
240024	40041	300	0	0	0	0	0	0	33	176	0	0	1	40049	0	0	8	0	25	240092	10	160000	80000	10	160000	80000	50	419586	4560014	0	40045	0	40041	40064	9996	3	10049	240010	20	80000	160000	20	80000	160000	40047	40047	1	1	80021	10	9	0	10	10	80000	80000	1	10	80017	18	0	80058	1	0	0	61	80041	6	1	58	45	16	2	5020	12	16	16	12	40061	0	0	14	0	80000	160000	10	40060	40042	40065	40065	40060

LD2R (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations