Firestorm: LD2R (post-index, 1D) measurements

Code:

  ld2r { v0.1d, v1.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.002

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	c9	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	28806	231	32	0	1	24	0	1	2	0	0	3	88	1	0	0	4785	28408	0	0	0	16702	4002	1000	2002	1001	1000	2000	1000	5000	5002	23858	6	0	0	22674	28806	28749	7	10	4000	1000	2000	2000	2002	28671	28699	2	1	61001	1000	1000	1	1000	2	2	1002	0	0	0	150	1000	2	0	0	2	0	13032	9318	6842	3058	16	66	20437	3239	3819	15	58	67	2	28596	1000	16047	12895	14379	1000	2000	1000	29313	29357	29268	29403	29278
63004	29281	237	27	0	1	25	1	0	0	0	0	0	0	0	0	0	4619	28791	0	1	0	17125	4006	1000	2000	1000	1000	2002	1000	5000	5003	23866	5	0	0	22682	29089	29163	3	10	4000	1000	2000	2000	2000	29117	29181	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	159	1000	1	0	3	0	213	13047	9425	6806	3050	13	66	20394	3311	3814	23	62	60	2	28461	1000	15894	12933	14381	1000	2000	1000	29422	28920	28945	29002	29130
63004	29192	234	33	0	0	24	0	0	0	0	1	3	0	1	0	0	4678	28650	0	1	0	17014	4006	1000	2006	1000	1000	2000	1000	5000	5024	23846	5	0	0	22708	28786	29023	3	10	4004	1000	2000	2000	2000	28914	28954	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	151	1001	0	1	3	0	0	13161	9344	6906	3066	12	62	20326	3259	3812	17	64	60	2	28342	1000	15672	12939	13924	1000	2000	1000	28884	28947	28989	29053	29012
63004	29013	232	28	1	0	26	0	0	0	1	0	0	0	0	0	0	4597	28652	0	0	0	17070	4006	1000	2006	1000	1000	2000	1000	5000	5024	23873	3	0	0	22663	28899	29108	8	10	4000	1000	2000	2000	2000	29058	28957	1	1	61001	1000	1000	0	1000	0	0	1000	0	0	0	24	1000	2	1	3	0	0	13070	9348	6901	3142	11	61	20318	3226	3808	21	67	68	2	28309	1000	15800	12754	14075	1000	2000	1000	29000	29004	29111	29075	28954
63004	29247	234	23	0	0	25	0	0	0	0	0	132	0	0	0	0	4644	28497	0	1	1	17012	4000	1000	2006	1000	1001	2000	1000	5000	5026	23800	6	0	0	22726	28848	29062	3	10	4000	1000	2000	2000	2000	28850	28941	1	1	61001	1000	1000	0	1000	2	3	1001	0	0	0	150	1001	2	0	0	0	0	13057	9461	6867	3110	13	66	20413	3237	3815	17	62	60	2	28371	1000	15941	12918	14090	1000	2000	1000	29098	29023	29065	29106	29059
63004	29025	234	31	0	1	29	0	0	0	0	0	0	88	0	0	0	4732	28495	0	0	1	16972	4006	1001	2006	1000	1000	2000	1000	5000	5028	23890	5	0	0	22695	28893	29191	3	10	4000	1000	2000	2000	2000	28917	28915	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	145	1001	2	3	0	0	0	13105	9262	6870	3140	11	55	20449	3265	3815	14	56	61	2	28308	1000	15922	12945	14164	1000	2000	1000	29106	29206	29155	29060	29086
63004	29103	233	25	0	0	29	1	0	0	0	0	4	0	1	0	0	4663	28659	0	1	0	17104	4006	1000	2008	1000	1000	2000	1000	5000	5008	23872	6	0	0	22688	28886	29053	3	10	4000	1000	2000	2000	2000	28800	28824	1	1	61001	1000	1000	1	1000	0	0	1001	0	0	0	147	1000	2	0	0	0	0	13298	9341	6866	3116	14	60	20420	3190	3814	21	55	63	2	28386	1000	15718	13083	14277	1000	2000	1000	29200	29060	29208	29138	29017
63004	28941	234	28	1	0	28	0	0	0	0	0	4	0	0	0	0	4574	28587	0	0	0	16924	4010	1000	2006	1000	1002	2000	1000	5000	5005	23858	7	0	0	22744	28959	29109	3	10	4000	1000	2000	2000	2000	28900	28941	2	1	61001	1000	1000	0	1002	0	3	1000	0	0	0	172	1000	0	1	2	0	0	13171	9223	6855	3101	9	67	20650	3320	3815	14	66	69	2	28532	1000	16007	12831	14270	1000	2000	1000	29293	29339	29381	29246	29070
63004	29149	234	25	0	0	22	0	0	1	0	0	4	0	0	0	0	4692	28441	0	0	1	16961	4000	1000	2006	1000	1000	2000	1000	5000	5023	23850	5	0	0	22714	28847	29123	3	10	4000	1000	2000	2000	2000	28802	28699	1	1	61001	1000	1000	0	1000	0	3	1001	0	0	0	153	1000	2	0	1	0	0	13263	9390	6913	3086	19	61	20136	3301	3810	13	59	58	2	28272	1000	15716	12673	13928	1000	2000	1000	28824	28898	28885	28884	28811
63004	29037	235	25	0	0	22	0	0	0	0	0	2	0	0	0	0	4738	28369	0	0	1	16909	4002	1001	2000	1000	1000	2002	1000	5005	5020	23862	5	0	0	22712	28655	28989	3	10	4000	1000	2000	2000	2000	29376	29360	1	1	61001	1000	1000	0	1000	0	3	1000	0	0	0	157	1000	2	0	0	0	0	13133	8995	6831	3114	11	67	20742	3295	3812	24	60	63	2	28648	1000	15957	12946	14075	1000	2000	1000	29494	29585	29521	29308	29303

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.1d, v1.1d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140053	1049	0	0	0	1	0	0	13	0	1	0	0	140020	139577	25	90103	50100	30000	10000	40100	30000	10000	1244786	5330042	16114109	0	140012	0	140050	140050	130726	0	3	131194	80100	30200	10000	30000	60200	20000	30000	140050	140035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	3	10000	1	1	0	0	0	3210	1	121	1	1	139708	50000	9	0	0	10000	20000	50100	140036	140052	140051	140051	140051
70204	140036	1085	0	0	1	0	0	0	1	0	0	0	0	140035	139552	25	90103	50100	30000	10000	40100	30000	10000	1244786	5366527	16139330	0	140082	0	140050	140050	130726	0	3	131194	80422	30200	10000	30000	60200	20000	30000	140050	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	3235	1	80	1	1	139711	50000	9	0	9	10000	20000	50100	140051	140036	140036	140048	140051
70204	140050	1085	0	0	1	1	1	0	12	0	0	0	0	140035	139577	25	90100	50127	30003	10000	40100	30000	10000	1247784	5331203	16114340	0	140026	0	140050	140050	130749	0	3	131150	80100	30200	10000	30000	60442	20000	30000	140141	140047	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3231	10003	1	1	0	0	0	3210	1	102	1	1	139722	50000	9	0	0	10000	20000	50100	143487	140036	140049	140036	140036
70204	140047	1086	0	0	1	1	0	0	1	0	0	0	0	140020	139640	25	90133	50100	30000	10000	40100	30000	10000	1236925	5329939	16112701	0	140011	0	140050	140053	130726	0	3	131150	80413	30200	10000	30000	60200	20000	30000	140037	140052	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	1	0	3	10000	0	1	0	0	0	3210	1	121	1	1	139722	50000	9	6	9	10000	20000	50100	140051	140053	140036	140036	140051
70204	140050	1086	1	0	1	1	1	0	1	0	0	0	0	140038	139592	25	90100	50100	30003	10000	40100	30000	10000	1244786	5330042	16114109	0	140026	0	140051	140035	130723	0	3	131194	80100	30200	10000	30000	60200	20000	30000	140050	140035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	1	0	3	10000	1	1	0	0	0	3237	1	80	1	1	139722	50000	6	6	6	10000	20000	50100	140051	140051	140051	140051	140051
70204	140050	1085	0	0	0	0	1	0	0	0	0	0	0	140033	139589	25	90133	50100	30003	10000	40100	30000	10000	1236903	5330746	16114109	1	140023	0	140035	140143	130726	0	3	131194	80100	30320	10000	30000	60200	20000	30000	140050	140047	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	0	0	0	3210	1	80	1	1	139778	50000	9	6	9	10000	20000	50100	140051	140051	140051	140051	140151
70204	140054	1085	0	0	1	1	0	0	13	0	0	0	0	140035	139589	25	90103	50100	30003	10000	40244	30000	10000	1236903	5330746	16114109	0	140011	0	140047	140035	130724	0	3	131304	80100	30200	10000	30000	60200	20000	30000	140140	140035	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	0	10000	0	0	0	10001	0	1	0	0	0	3210	1	80	2	1	139722	50000	9	6	6	10000	20000	50100	140048	140051	140052	140051	140048
70204	140050	1086	0	0	0	0	0	0	13	88	0	1	0	140131	139577	25	90103	50100	30003	10000	40100	30000	10000	1248022	5331056	16112853	1	140024	0	140047	140047	130711	0	31	131153	80100	30200	10000	30000	60200	20000	30000	140145	140047	2	1	50201	100	99	100	40100	10000	10000	0	100	10003	0	1	10000	1	0	3	10000	1	1	0	0	0	3210	1	80	1	1	139799	50000	9	9	0	10000	20000	50100	140128	140052	140051	140048	140036
70204	140050	1086	0	0	1	0	0	0	13	0	0	1	0	140033	139577	25	90103	50100	30003	10000	40100	30000	10000	1246269	5330473	16112739	1	140026	0	140050	140035	130726	0	17	131194	80100	30200	10000	30000	60200	20000	30000	140142	140047	2	1	50201	100	99	100	40100	10000	10000	1	100	10001	0	1	10000	0	2	3	10001	1	1	0	0	0	3210	1	80	1	1	139705	50000	9	6	9	10000	20000	50100	140051	140147	140048	140048	140036
70204	140035	1086	1	0	0	0	0	0	0	0	0	1	0	140035	139552	25	90103	50100	30003	10000	40100	30000	10000	1248731	5331828	16114109	0	140026	0	140050	140051	130725	0	3	131194	80100	30320	10000	30000	60442	20000	30121	140050	140134	2	1	50201	100	99	100	40100	10000	10000	1	100	10005	0	0	10005	0	0	6380	10002	0	1	0	0	0	3257	1	125	3	1	139855	50033	11	6	9	10000	20000	50100	140234	140228	140232	140376	142835

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140047	1086	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	140038	139653	25	90013	50010	30006	10000	40161	30000	10000	1245879	5333173	16114899	140023	140047	140047	130746	3	131215	80010	30020	10040	30124	60020	20000	30000	140150	140050	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	3	0	0	10000	1	0	0	0	0	3140	18	87	21	19	139719	50000	6	6	6	10000	20000	50010	140051	140048	140048	140051	140052
70024	140035	1086	0	0	0	0	0	0	0	0	0	0	0	13	0	0	0	140032	139647	25	90013	50010	30003	10000	40010	30000	10000	1245879	5333173	16114779	140011	140047	140035	130734	3	131206	80343	30167	10000	30000	60020	20000	30000	140098	140055	1	1	50022	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3183	21	87	20	22	139719	50000	6	0	0	10000	20000	50010	140048	140105	140117	140049	140058
70024	140053	1085	0	1	0	1	0	0	1	0	0	0	0	14	0	0	0	140032	139647	25	90013	50010	30000	10000	40010	30000	10000	1245879	5333173	16113463	140026	140050	140047	130746	3	131210	80010	30020	10000	30000	60020	20000	30000	140055	140047	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	3140	13	87	21	20	139719	50000	6	6	6	10000	20000	50010	140048	140048	140051	140048	140048
70024	140035	1085	0	0	0	0	0	0	0	0	0	0	0	6	0	0	0	140039	139647	25	90013	50010	30003	10000	40010	30000	10000	1245879	5333173	16114779	140023	140253	140051	130746	3	131206	80010	30020	10000	30000	60020	20000	30000	140078	140052	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	24	87	22	17	139724	50000	6	6	6	10000	20000	50010	140048	140048	140048	140048	140051
70024	140047	1085	0	0	0	0	0	0	0	0	1	0	0	1	0	0	0	140033	139647	25	90013	50010	30003	10000	40010	30000	10000	1245879	5333285	16114779	140023	140047	140084	130746	3	131209	80010	30020	10000	30000	60020	20000	30000	140424	140048	2	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	0	10000	0	0	9	10000	1	0	1	0	0	3140	22	87	23	21	139719	50000	6	6	6	10000	20000	50010	140048	140048	140048	140048	140039
70024	140035	1085	0	0	0	0	0	0	0	1	1	0	0	1	0	0	0	140032	139652	25	90013	50010	30003	10000	40010	30000	10000	1245907	5333253	16113346	140023	140047	140050	130749	3	131206	80010	30020	10000	30000	60020	20000	30000	140120	140053	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	1	1	1	3140	24	87	24	23	139725	50000	6	0	12	10000	20000	50010	140054	140248	140236	140279	140343
70024	140241	1087	1	1	0	2	2	1	0	0	0	3	2	398	176	0	1	142156	139949	110	90046	50032	30018	10002	40576	30241	10118	1250705	5338099	16129473	140178	140340	140326	130828	28	131364	80906	30384	10122	30240	60742	20160	30365	140340	140250	4	1	50021	10	9	0	10	40010	10000	10000	0	10	10003	4	1	10003	0	11	3187	10000	1	1	1	1	0	3140	22	87	15	22	139713	50000	6	6	0	10000	20000	50010	140054	140054	140056	140054	140054
70024	140053	1086	0	1	0	0	0	0	0	0	0	0	0	14	0	0	0	140035	139650	25	90013	50010	30003	10000	40010	30000	10000	1245879	5332706	16114779	140023	140047	140047	130746	3	131206	80010	30020	10000	30000	60020	20000	30000	140064	140047	1	1	50021	10	9	4	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	1	0	2	3140	25	87	17	23	139719	50000	9	6	9	10000	20000	50010	140036	140036	140036	140048	140048
70024	140049	1085	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	140032	139664	25	90013	50010	30003	10000	40010	30000	10000	1245879	5333285	16114779	140023	140035	140047	130734	3	131206	80010	30020	10000	30000	60020	20000	30000	140124	140060	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3188	21	109	23	22	139719	50000	6	10	6	10000	20000	50010	140052	140048	140048	140048	140048
70024	140047	1085	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	140032	139650	25	90013	50010	30000	10000	40010	30000	10000	1245907	5333173	16113346	140023	140047	140048	130757	3	131206	80010	30020	10000	30000	60020	20000	30000	140104	140422	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	3140	14	87	21	15	139719	50000	6	6	6	10000	20000	50010	140048	140048	140048	140048	140051

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.1d, v1.1d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0065

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140053	1086	0	0	1	0	1	1	0	0	1	0	0	0	0	140050	139565	25	90103	50100	30003	10000	40100	30000	10000	1244902	5331917	16116236	0	0	140039	140065	140063	130739	3	131178	80100	30200	10000	30000	60200	20000	30000	140063	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	1	0	3	10000	1	0	1	0	0	0	3210	1	80	1	1	139740	50000	0	6	9	10000	20000	50100	140064	140064	140064	140067	140067
70204	140063	1086	0	0	0	0	1	1	0	0	12	0	0	0	0	140051	139565	25	90103	50100	30003	10000	40100	30000	10000	1237096	5330530	16116477	0	0	140039	140063	140063	130731	3	131169	80100	30200	10000	30000	60200	20000	30000	140063	140066	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	3	10000	1	0	1	0	0	0	3210	1	17	1	1	139736	50000	9	9	9	10000	20000	50100	140064	140064	140064	140067	140064
70204	140065	1086	0	0	0	0	1	1	0	0	1	0	0	0	0	140040	139565	25	90103	50100	30000	10000	40100	30000	10000	1237096	5331917	16114980	0	0	140039	140063	140055	130739	3	131158	80100	30200	10000	30000	60200	20000	30000	140068	140066	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10038	1	0	1	0	0	0	3210	1	121	1	1	139735	50000	9	6	9	10000	20000	50100	140064	140166	140069	140065	140067
70204	140068	1087	0	0	0	0	1	0	0	0	1	0	0	0	0	140048	139607	25	90100	50100	30003	10000	40100	30000	10000	1248040	5331499	16116704	0	1	140032	140155	140066	130731	3	131168	80100	30467	10000	30000	60200	20000	30120	140063	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10003	1	2	0	10000	1	0	0	0	0	0	3210	1	121	1	1	139803	50000	6	6	9	10000	20000	50100	140068	140064	140056	140066	140064
70204	140065	1125	0	0	0	0	0	0	0	1	25	0	0	0	0	140048	139565	25	90103	50110	30003	10000	40100	30000	10000	1244189	5332312	16116236	0	0	140039	140065	140065	130739	3	131207	80100	30200	10040	30000	60200	20000	30123	140063	140066	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	0	3210	1	80	1	1	139735	50000	6	9	9	10000	20000	50100	140056	140056	140067	140064	140067
70204	140063	1125	0	0	0	0	1	0	0	0	18	0	0	0	0	140048	139608	25	90103	50100	30007	10000	40100	30000	10000	1242228	5330530	16107932	0	0	140039	140063	140066	130742	3	131207	80100	30200	10000	30000	60448	20000	30121	140063	140061	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	3210	6	461	1	1	139736	50000	6	6	6	10000	20000	50100	140144	140069	140067	140064	140056
70204	140063	1125	0	0	0	0	1	1	0	0	1	0	0	0	0	140051	139598	25	90103	50100	30007	10000	40100	30000	10045	1246783	5330530	16120675	0	0	140039	140066	140055	130739	3	131240	80196	30200	10000	30000	60200	20000	30146	140256	140066	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	0	3210	1	80	1	1	139779	50000	9	6	9	10000	20000	50100	140073	140156	140067	140064	140067
70204	140444	1125	0	0	0	0	1	1	0	0	6	0	0	0	0	140048	139607	25	90103	50100	30003	10000	40100	30000	10000	1244911	5330530	16116236	0	0	140039	140066	140066	130739	3	131209	80400	30200	10000	30000	60200	20000	30000	140063	140063	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	0	0	1	0	0	0	3210	1	121	1	1	139735	50024	9	9	9	10000	20000	50100	140064	140064	140158	140064	140069
70204	140063	1125	0	1	0	0	1	1	0	0	13	0	0	0	0	140048	139565	25	90103	50100	30003	10000	40100	30000	10000	1244902	5330530	16116236	0	0	140042	140066	140055	130742	3	131207	80100	30200	10000	30000	60200	20000	30000	140056	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	1	10000	2	0	0	10000	1	0	1	0	0	0	3233	1	121	1	1	139735	50000	9	6	9	10000	20000	50100	140064	140064	140064	140064	140056
70204	140063	1125	0	0	0	0	1	1	0	0	0	0	0	0	0	140131	139565	81	90122	50125	30007	10002	44372	32235	10118	1241678	5337211	16117370	0	0	140300	140245	140439	130784	125	132679	86099	30577	10081	30359	60934	20082	30485	140348	140143	4	1	50201	100	99	100	40100	10000	10000	0	100	10003	0	1	10006	0	0	0	10002	1	0	1	0	0	0	3257	1	113	2	1	139951	50010	9	9	9	10000	20000	50100	140241	140326	140344	140253	140343

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0052

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140050	1086	0	0	0	0	0	1	0	0	0	140037	139652	25	90013	50010	30003	10000	40010	30000	10000	1245925	5333361	16115004	0	140028	140052	140052	130751	3	131211	80010	30020	10000	30000	60020	20000	30000	140050	140053	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	2	0	0	10000	1	1	0	0	3140	0	6	87	4	5	139724	50000	0	0	9	10000	20000	50010	140053	140112	140054	140086	140037
70024	140039	1085	0	0	0	0	0	1	0	0	0	140037	139762	25	90013	50010	30003	10000	40010	30000	10000	1245925	5333249	16115004	0	140028	140052	140052	130751	3	131211	80010	30020	10000	30000	60020	20000	30000	140052	140049	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	0	0	3140	0	7	87	7	6	139726	50000	9	9	9	10000	20000	50010	140050	140113	140068	140056	140053
70024	140049	1086	0	1	0	0	0	1	0	0	0	140034	139686	25	90013	50010	30003	10000	40010	30119	10000	1247732	5333361	16115401	0	140031	140052	140052	130735	3	131215	80010	30020	10000	30000	60020	20000	30000	140153	140049	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	5	95	4	4	139724	50000	0	0	9	10000	20000	50010	140054	140123	140108	140054	140150
70024	140053	1125	0	1	0	0	2	13	0	0	0	140037	139716	25	90013	50010	30003	10001	40010	30000	10000	1245925	5333361	16115004	0	140028	140058	140055	130751	3	131211	80010	30020	10000	30000	60244	20000	30000	140052	140049	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	0	0	3140	0	12	87	4	6	139724	50000	9	6	9	10000	20000	50010	140060	140054	140096	140060	140125
70024	140052	1085	0	0	0	0	0	22	0	0	0	140039	139688	25	90025	50010	30000	10000	40010	30000	10000	1245925	5333361	16115120	0	140028	140052	140154	130753	16	131213	81801	30143	10000	30000	60020	20000	30000	140036	140049	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10001	2	0	9	10000	0	1	2	1	3173	0	5	115	8	8	139708	50000	9	6	10	10000	20000	50010	140053	140050	140126	140066	140053
70024	140052	1086	0	0	0	1	0	13	0	1	0	140037	139683	25	90010	50020	30007	10000	40010	30000	10000	1245856	5332745	16113820	0	140028	140036	140151	130775	35	131268	80010	30020	10041	30000	60020	20000	30000	140038	140037	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	0	1	10000	0	0	3	10002	1	1	0	0	3140	0	6	87	4	7	139721	50000	9	6	9	10000	20000	50010	140053	140052	140133	140059	140138
70024	140036	1086	0	0	0	1	0	0	0	0	0	140037	139724	54	90013	50010	30000	10000	40010	30000	10000	1245934	5333361	16119150	0	140028	140052	140052	130753	17	131211	80010	30020	10000	30000	60020	20000	30000	140052	140049	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	4	87	6	5	139721	50010	9	0	9	10000	20000	50010	140053	140050	140213	140143	140053
70024	140036	1086	0	0	0	0	1	133	88	0	0	140037	139672	25	90013	50010	30007	10000	40010	30000	10000	1245988	5335358	16115118	0	140110	140052	140052	130752	3	131266	80010	30142	10000	30000	60020	20000	30000	140055	140049	2	1	50021	10	9	0	10	40010	10000	10000	0	10	10001	0	1	10000	0	0	0	10000	0	0	0	0	3140	0	5	87	7	5	139708	50000	0	6	9	10000	20000	50010	140152	140050	140110	140061	140058
70024	140149	1086	0	0	0	0	0	1	88	0	0	140037	139702	53	90013	50010	30000	10000	40010	30118	10000	1245925	5333400	16115121	0	140028	140052	140052	130751	3	131195	80308	30020	10000	30000	60020	20000	30000	140054	140036	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10002	0	1	10002	0	0	3255	10002	1	1	0	0	3211	0	5	125	5	5	139929	50039	9	6	9	10000	20000	50010	140233	140396	140346	140342	140337
70024	140221	1088	1	0	0	27	9	397	88	0	0	140224	139739	137	90043	50039	30015	10003	40294	30610	10157	1253808	5338298	16115401	1	140028	140052	140052	130788	3	131211	80352	30020	10000	30000	60020	20096	30000	140052	140049	1	1	50021	10	9	0	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	3	10000	1	1	0	0	3140	0	4	87	7	6	139724	50000	9	6	9	10000	20000	50010	140053	140061	140117	140074	140053

Test 4: throughput

Count: 8

Code:

  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8
  ld2r { v0.1d, v1.1d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80041	643	1	1	0	0	1	0	0	0	48	0	0	0	1	80026	1	6	6	0	0	25	320170	80100	160068	80000	80100	160000	80000	4408136	3758366	9826559	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	27	80030	0	2	30	80023	6	1	28	0	7	1	5110	0	1	16	1	11	80038	1	80000	14	13	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	0	0	0	0	0	0	34	0	0	0	0	80026	1	6	6	4	10	25	320172	80100	160068	80000	80100	160000	80000	4408215	3758365	9826559	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	8	27	80030	0	1	29	80023	0	1	29	27	7	0	5110	0	1	16	1	4	80038	1	80000	13	14	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	0	0	1	1	0	0	36	0	0	0	1	80026	1	6	6	4	10	25	320172	80100	160072	80000	80100	160000	80000	4408136	3758365	9826573	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80008	6	27	80007	1	0	7	80023	0	1	28	27	7	0	5110	0	1	16	1	15	80038	1	80000	13	0	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	0	1	0	0	0	0	39	0	0	0	1	80026	1	6	0	8	3	25	320172	80100	160072	80000	80100	160000	80000	4408136	3758336	9826559	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80007	8	0	80007	0	0	6	80023	6	1	29	27	7	0	5110	0	1	16	1	5	80038	0	80000	13	17	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	0	1	0	0	0	0	34	0	0	0	1	80026	1	6	6	4	6	25	320172	80100	160012	80000	80100	160000	80000	4408130	3758364	9826558	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	8	27	80029	0	2	28	80023	6	1	30	0	7	0	5110	0	1	16	1	16	80038	1	80000	13	0	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	642	1	0	0	0	0	0	0	0	36	0	1	0	1	80026	1	6	6	0	0	25	320172	80100	160068	80000	80100	160000	80000	4408202	3758365	9826559	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80009	8	27	80031	1	1	28	80023	6	1	30	27	7	0	5110	0	1	16	1	13	80038	1	80000	13	13	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	1	0	0	1	0	0	7	0	0	0	1	80026	1	6	0	4	3	25	320172	80100	160014	80000	80100	160000	80000	4408136	3758365	9826964	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	27	80028	0	1	31	80023	6	1	30	27	7	1	5110	0	1	16	1	3	80038	0	80000	13	13	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	0	0	0	1	0	0	48	0	0	0	1	80026	1	6	6	0	3	25	320172	80100	160068	80000	80100	160000	80000	4408136	3758360	9826559	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	27	80031	0	1	7	80112	6	1	31	27	7	2	5110	0	1	16	1	6	80038	1	80000	0	13	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	0	0	0	0	0	0	6	0	0	0	1	80026	1	0	6	4	1	25	320174	80100	160014	80000	80100	160000	80000	4408136	3758365	9825495	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80095	8	27	80028	0	0	33	80022	6	1	30	27	6	2	5110	0	1	16	1	4	80038	1	80000	13	13	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	1	1	1	0	0	0	0	34	0	0	0	1	80026	0	6	6	0	6	25	320172	80100	160068	80000	80100	160000	80000	4408136	3758359	9826931	0	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80006	7	27	80031	0	0	30	80023	6	1	30	28	7	1	5110	0	1	16	1	3	80038	1	80000	13	13	80000	160000	80100	80042	80166	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80183	643	1	0	1	0	1	1	0	0	1230	0	0	0	0	1	80026	1	0	6	4	3	25	320078	80010	160012	80000	80010	160000	80000	4407617	3758363	9826287	0	0	80022	80041	80041	49947	0	3	50021	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	0	80029	0	0	0	28	80023	6	1	30	27	6	0	0	5020	0	12	16	11	9	80038	1	80000	13	14	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	1	2	0	0	0	0	0	0	1104	0	0	0	0	1	80026	1	6	6	4	6	25	320082	80010	160072	80000	80010	160000	80000	4407617	3758365	9826287	1	0	80022	80041	80041	49947	0	3	50021	320010	20	80000	160000	20	160000	160000	80181	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	10	27	80006	0	0	0	28	80023	6	1	28	28	7	0	0	5020	0	8	16	12	11	80145	1	80000	13	13	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	1	1	0	1	0	0	0	0	35	0	0	0	0	0	80026	1	6	0	4	12	25	320080	80010	160072	80000	80010	160000	80000	4407617	3758369	9827412	0	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	27	80028	0	1	1	33	80023	6	1	30	27	6	0	0	5020	0	12	16	11	11	80038	0	80000	13	13	80000	160000	80010	80042	80042	80183	80042	80042
240024	80041	642	1	0	0	0	0	0	0	0	36	0	0	0	0	0	80026	1	6	0	4	7	25	320082	80010	160250	80000	80010	160000	80000	4407617	3758363	9826307	0	0	80022	80041	80041	49947	20	116	50021	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80006	7	27	80031	0	0	0	30	80023	6	1	30	27	7	0	0	5020	0	8	15	11	11	80038	0	80000	13	13	80000	160000	80010	80182	80042	80042	80042	80042
240024	80041	644	1	0	0	0	0	0	1	0	1509	0	0	0	0	0	80026	1	6	0	4	3	25	320436	80104	160014	80000	80010	160536	80131	4407617	3758366	9845066	0	0	80022	80181	80183	50002	65	89	50103	321075	20	80261	160542	20	160260	160271	80181	80182	3	1	80021	10	9	10	10	80000	80000	0	10	80097	6	0	80097	2	0	0	1230	80193	6	1	30	0	6	0	0	5057	0	15	34	12	11	80143	0	80185	13	13	80000	160000	80010	80323	80332	80189	80042	80323
240024	80323	644	1	2	0	0	0	0	1	2	166	88	0	0	0	2	80307	1	6	6	4	44	113	320843	80103	160252	80282	80143	160525	80134	4412148	3761957	9844337	0	0	80136	80181	80041	50002	39	29	50104	321096	20	80136	160269	20	160544	160544	80182	80182	3	1	80021	10	9	10	10	80000	80000	0	10	80103	7	27	80030	0	0	1	28	80109	6	1	28	27	7	1	0	5020	0	9	25	12	11	80038	1	80000	13	13	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	1	0	0	0	0	0	0	0	40	0	0	0	0	0	80026	1	6	6	4	3	25	320078	80010	160068	80000	80010	160000	80000	4407617	3758366	9826287	0	0	80022	80041	80041	49947	0	3	50021	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	9	27	80030	0	1	1	33	80022	6	1	34	27	7	0	0	5020	0	12	16	11	9	80038	0	80000	0	13	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	1	1	0	0	0	0	0	0	50	0	0	0	0	0	80026	1	6	6	4	3	25	320082	80010	160072	80000	80010	160000	80000	4407686	3758365	9826287	0	0	80022	80041	80041	49947	0	3	50021	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	27	80030	0	0	1	31	80022	0	1	28	27	7	0	0	5020	0	11	16	11	11	80038	1	80000	13	13	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	642	1	0	0	0	0	1	0	0	36	0	0	1	0	0	80026	1	6	6	4	3	25	320078	80010	160068	80000	80010	160000	80000	4407591	3758366	9826287	0	0	80022	80041	80041	49947	0	115	50021	320010	20	80000	160000	20	160000	160000	80041	80749	1	1	80021	10	9	10	10	80000	80000	0	10	80007	8	31	80032	0	2	1	7	80022	6	1	30	27	6	1	0	5020	0	12	16	9	12	80038	0	80000	13	13	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	643	1	0	0	0	1	0	0	0	825	0	0	0	1	0	80026	1	6	6	1	5	25	320072	80010	160064	80000	80010	160013	80000	4407648	3758375	9825143	0	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80007	7	23	80008	0	1	1	32	80018	6	1	26	0	7	0	0	5020	0	13	15	9	13	80038	0	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042

LD2R (post-index, 1D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations