Firestorm: LD2R (post-index, 2D) measurements

Code:

  ld2r { v0.2d, v1.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	24	3a	3f	46	49	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd load (98)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
63005	29813	229	0	16	0	0	17	0	1	1	2	0	0	0	4671	28937	0	0	17428	4012	1000	2002	1000	1000	2000	1000	5000	5000	23902	12	0	22721	29218	29341	8	10	4000	1000	2000	2000	2000	29148	29196	1	1	61001	1000	1000	1003	4	4	1002	0	2	2	1000	3	1	3	0	0	13198	9567	6873	3208	9	40	20684	3169	3814	18	40	40	28643	1000	16407	13125	14415	1000	2000	1000	29429	29362	29339	29345	29325
63004	29452	228	0	21	0	0	15	0	1	1	154	0	0	0	4674	28895	1	1	17275	4008	1001	2004	1000	1000	2000	1000	5000	5000	23870	6	1	22737	29294	29431	3	29	4000	1000	2000	2000	2000	29182	29236	1	1	61001	1000	1000	1000	0	3	1001	0	0	430	1001	3	1	3	0	0	13241	9286	6975	3171	5	37	20707	3235	3810	16	39	40	28965	1000	16346	13076	14473	1000	2000	1000	29381	29316	29317	29306	29304
63004	29460	228	0	21	0	0	15	0	1	1	10	0	0	0	4684	28995	1	1	17295	4006	1000	2006	1000	1001	2000	1000	5000	5000	23884	5	0	22700	29152	29467	3	10	4000	1000	2000	2000	2000	29379	29295	1	1	61001	1000	1000	1000	0	2	1001	0	0	1	1001	2	1	3	0	0	13177	9553	6920	3203	9	34	20717	3253	3811	17	40	40	28812	1000	16167	13181	14360	1000	2000	1000	29428	29404	29489	29392	29403
63004	29421	227	0	16	0	0	20	0	1	1	2	1	0	0	4765	28929	1	1	17287	4006	1000	2004	1000	1000	2000	1001	5000	5000	23889	7	0	22685	29246	29407	10	10	4000	1000	2000	2000	2000	29190	29357	1	1	61001	1000	1000	1000	0	3	1001	0	0	0	1001	2	0	3	0	0	13323	9461	6976	3143	5	40	20807	3387	3815	15	46	44	28739	1000	16176	13158	14382	1000	2000	1000	29471	29352	29314	29402	29331
63004	29382	228	0	15	0	0	13	0	1	1	4	0	0	0	4580	28880	0	1	17194	4006	1000	2010	1000	1000	2000	1000	5000	5000	23898	5	0	22728	29112	29247	3	10	4000	1000	2000	2000	2000	29230	29166	1	1	61001	1000	1000	1000	0	3	1001	0	0	1	1000	2	1	2	0	0	13123	9370	6937	3107	7	40	20759	3293	3815	13	35	35	28574	1000	16334	13110	14399	1000	2000	1000	29347	29363	29240	29357	29229
63004	29404	227	0	17	0	0	14	0	1	0	3	0	0	0	4679	28906	1	0	17345	4000	1000	2006	1000	1000	2000	1000	5000	5000	23880	5	0	22714	29221	29338	3	10	4000	1000	2000	2000	2000	29150	29115	1	1	61001	1000	1000	1000	0	3	1001	0	0	0	1001	2	1	3	0	0	12934	9504	6849	3111	10	39	20700	3139	3817	18	42	34	28682	1000	16341	13284	14486	1000	2000	1000	29325	29338	29411	29339	29289
63004	29372	228	0	13	0	0	23	0	1	1	4	0	0	0	4683	28802	1	1	17302	4006	1000	2006	1000	1000	2000	1000	5000	5000	23872	17	0	22751	29179	29339	3	10	4000	1000	2000	2000	2000	29203	29207	1	1	61001	1000	1000	1000	0	3	1001	0	0	1	1000	2	1	3	0	0	13105	9381	6857	3146	7	39	20609	3225	3802	12	37	36	28442	1000	16140	13353	14236	1000	2000	1000	29244	29235	29296	29315	29388
63004	29341	228	0	18	0	0	16	0	1	1	4	0	0	0	4646	28765	1	1	17309	4006	1000	2006	1000	1000	2000	1000	5000	5000	23870	17	0	22733	29023	29215	3	10	4000	1000	2000	2000	2000	29180	29106	1	1	61001	1000	1000	1000	0	3	1001	0	0	1	1001	2	1	3	0	0	13081	9233	6930	3108	10	36	20586	3193	3806	15	37	36	28500	1000	16244	13255	14409	1000	2000	1000	29363	29476	29214	29192	29318
63004	29235	226	0	14	0	0	15	0	1	1	4	0	0	0	4632	28921	1	0	17245	4006	1000	2006	1000	1000	2000	1000	5000	5000	23896	12	0	22705	29266	29282	3	10	4000	1000	2000	2000	2000	29309	29229	1	1	61001	1000	1000	1000	0	3	1000	1	0	4	1001	3	1	2	1	1	12924	9209	6906	3081	6	40	20618	3042	3812	23	34	41	28431	1000	16318	13337	14693	1000	2000	1000	29431	29417	29324	29373	29318
63004	29285	220	1	18	0	0	18	1	1	1	2	0	0	0	4497	28896	1	0	17260	4006	1000	2006	1000	1000	2000	1000	5000	5000	23812	5	0	22711	29145	29344	3	10	4000	1000	2000	2000	2000	29222	29156	1	1	61001	1000	1000	1000	0	2	1000	0	0	0	1000	2	0	2	0	0	12763	9195	6881	3037	10	43	20709	3081	3815	23	35	36	28417	1000	16520	13371	14627	1000	2000	1000	29326	29322	29337	29357	29303

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2d, v1.2d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0055

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3f	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140061	1086	1	0	0	0	1	1	0	0	2	0	0	0	0	140042	1	1	139597	25	90106	50100	30006	10000	40100	30000	10000	1237053	5334618	16116580	140031	140049	140060	130737	3	131164	80100	30200	10000	30000	60200	20000	30000	140058	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	0	4	10001	0	1	1	0	3210	1	121	1	1	139725	50000	6	6	6	10000	20000	50100	140044	140044	140056	140056	140056
70204	140055	1085	0	0	0	0	1	0	0	0	2	0	0	0	0	140040	1	1	139585	25	90106	50100	30012	10000	40100	30000	10000	1237008	5334210	16118010	140031	140061	140055	130732	3	131152	80100	30200	10000	30000	60200	20000	30000	140055	140055	1	1	50201	100	99	100	40100	10000	10000	1	100	10000	0	1	10001	0	4	10000	1	1	1	0	3210	1	121	1	1	139725	50000	0	0	0	10000	20000	50100	140056	140044	140045	140056	140056
70204	140043	1085	0	0	0	0	0	0	0	0	14	0	0	0	0	140040	1	1	139600	25	90103	50100	30003	10000	40100	30000	10000	1236999	5333748	16116357	142640	140055	140043	130731	3	131161	80100	30200	10000	30000	60200	20000	30000	140055	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	1	4	10002	0	1	1	0	3210	1	121	1	1	139725	50029	6	7	6	10000	20000	50100	140056	140056	140145	140044	140044
70204	140055	1085	0	0	0	0	1	0	0	0	14	0	0	0	0	140133	1	1	139610	25	90106	50100	30006	10000	40100	30000	10000	1237008	5331509	16127292	140093	140043	140055	130731	3	131238	80100	30200	10000	30000	60200	20000	30000	140057	140043	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	0	10001	0	7	10002	0	1	0	0	3210	1	121	1	1	139726	50000	7	6	6	10000	20000	50100	140058	140146	140056	140044	140059
70204	140043	1085	0	0	1	0	0	0	0	0	13	0	0	0	0	140044	1	1	139597	25	90106	50100	30006	10000	40100	30000	10000	1236972	5334196	16122473	140037	140055	140055	130725	3	131244	80100	30200	10000	30000	60200	20000	30000	140043	140043	2	1	50201	100	99	100	40100	10000	10000	1	100	10001	0	2	10001	0	1	10001	1	1	1	0	3210	1	121	1	1	139725	50000	0	0	6	10000	20000	50100	140056	140056	140056	140060	140056
70204	140055	1086	0	0	0	0	0	0	0	0	2	88	0	0	1	140028	1	0	139597	25	90106	50100	30006	10000	40145	30000	10000	1237008	5331203	16126688	140031	140055	140043	130719	3	131158	80100	30200	10000	30000	60200	20000	34364	144033	143064	2	1	50201	100	99	100	40100	10000	10000	0	100	10001	0	2	10001	0	1	10000	1	1	1	0	3210	1	121	1	1	139725	50000	6	6	6	10000	20000	50100	140144	140056	140056	140056	140044
70204	140043	1086	0	0	0	0	1	1	0	0	1	88	0	0	0	140043	1	1	139585	25	90103	50100	30006	10000	40100	30000	10040	1236999	5332611	16115791	140031	140055	140043	130731	3	131158	80100	30200	10000	30000	60200	20000	30000	140055	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	0	3206	10001	1	1	1	0	3210	1	121	1	1	139726	50000	6	0	0	10000	20000	50100	140056	140056	140056	140056	140056
70204	140043	1085	0	0	0	0	1	0	0	0	2	0	0	0	0	140040	1	1	139585	25	90106	50100	30006	10001	40100	30000	10000	1236999	5331281	16120724	140034	140055	140044	130745	3	131158	80100	30200	10000	30121	60492	20000	30000	140043	140055	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	2	1	10001	1	1	1	0	3210	1	121	1	1	139803	50000	6	0	6	10000	20000	50100	140056	140044	140056	140056	140056
70204	140043	1085	0	0	0	1	1	0	0	1	2	0	0	0	0	140040	1	1	139597	54	90124	50100	30003	10000	40100	30000	10000	1236999	5332721	16117892	140031	140161	140049	130731	3	131161	80100	30200	10000	30000	60200	20000	30000	140055	140057	1	1	50201	100	99	100	40100	10000	10000	0	100	10000	0	2	10001	1	1	10001	1	1	1	0	3210	1	121	1	1	139789	50000	6	6	6	10000	20000	50100	140444	140157	140319	140236	140243
70204	140332	1087	0	0	0	0	0	0	23	18	398	176	0	0	0	140218	1	0	139737	109	90160	50139	30011	10005	40254	30474	10040	1252825	5337260	16124962	140188	140223	140247	130808	29	131327	81019	30447	10080	30121	60442	20164	30119	140296	140233	4	1	50201	100	99	100	40100	10000	10000	1	100	10002	0	2	10008	0	4	10000	1	1	0	0	3210	1	121	1	1	139713	50000	0	6	6	10000	20000	50100	140056	140103	140044	140044	140057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140047	1085	0	0	0	0	0	0	0	0	0	13	0	0	0	0	0	140035	139647	25	90013	50010	30003	10000	40010	30000	10000	1245907	5333285	16114779	0	140023	0	140050	140050	130749	3	131209	80010	30020	10000	30000	60322	20000	30000	140095	140050	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	0	3140	9	87	3	7	139719	50000	9	6	9	10000	20000	50010	140048	140051	140051	140054	140141
70024	140047	1085	0	0	0	0	0	0	0	0	0	13	0	0	0	0	0	140020	139653	25	90029	50010	30007	10000	40010	30000	10000	1245847	5332706	16114779	0	140026	0	140047	140050	130781	3	131211	80010	30020	10000	30120	60020	20000	30000	140092	140043	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	3	10000	1	1	0	3140	4	87	6	4	139719	50000	6	6	0	10000	20000	50010	140048	140051	140048	140048	140146
70024	140047	1085	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	140032	139647	25	90025	50010	30003	10000	40010	30000	10000	1245907	5333285	16115176	0	140023	0	140050	140035	130746	3	131194	80010	30020	11213	33018	60020	20000	30000	140048	140121	5	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	0	3140	7	87	5	5	139708	50000	9	0	0	10000	20000	50010	140056	140051	140096	140048	140052
70024	140050	1125	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0	140035	139650	54	90013	50010	30003	10000	40010	30000	10000	1245907	5333211	16114779	0	140032	3	140146	140050	130752	3	131209	80010	30020	10081	30000	60020	20000	30000	140047	140118	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10001	0	0	0	10000	1	0	0	3140	6	87	3	3	139722	50000	9	0	9	10000	20000	50010	140051	140051	140051	140051	140036
70024	140050	1086	0	0	1	0	0	1	1	0	1	0	0	1	0	0	0	140035	139650	25	90013	50010	30003	10000	40010	30000	10000	1245847	5333285	16115181	0	140026	0	140139	140050	130825	3	131211	80010	30020	10000	30000	60020	20000	30000	140050	140035	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	2	0	0	10000	1	1	0	3164	4	87	4	4	139754	50113	9	6	9	10000	20000	50010	140052	140053	140051	140051	140051
70024	140051	1086	0	0	1	0	0	0	0	1	0	114	0	0	1	0	0	140035	139650	25	90013	50010	30003	10000	40010	30000	10000	1245879	5333173	16114779	0	140023	0	140050	140050	130829	3	131210	80010	30020	10000	30000	60020	20000	30000	140053	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10004	1	0	3	10000	1	1	2	3140	7	87	7	5	139707	50000	9	6	10	10000	20000	50010	140052	140051	140051	140052	140052
70024	140050	1086	0	0	1	0	0	1	0	0	0	10	0	0	0	0	0	140080	139650	25	90010	50010	30000	10000	40010	30000	10000	1245847	5333285	16114779	0	140026	0	140050	140035	130822	3	131210	80010	30020	10000	30000	60020	20000	30000	140050	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	3	10000	1	0	0	3140	4	87	8	5	139722	50012	9	0	9	10000	20000	50010	140051	140036	140036	140144	140036
70024	140050	1085	0	0	1	0	0	0	0	0	0	1	0	0	1	0	0	140035	139650	25	90013	50010	30003	10000	40010	30000	10000	1245907	5334524	16115176	0	140026	0	140035	140050	130796	7	131194	80010	30020	10000	30000	60020	20000	30118	140137	140145	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	3278	10000	1	1	0	3140	7	87	6	5	139722	50000	9	0	9	10000	20000	50010	140051	140036	140051	140051	140051
70024	140047	1086	0	0	0	0	0	0	0	0	0	1	88	0	0	0	0	140032	139650	25	90010	50010	30003	10000	40010	30121	10000	1245907	5333327	16114779	0	140011	0	140035	140050	130754	3	131209	80010	30020	10000	30000	60020	20000	30000	140146	140047	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	3140	5	87	7	5	139722	50010	0	6	10	10000	20000	50010	140244	141356	141140	140428	140129
70024	140241	1086	1	0	1	1	1	0	0	3	3	529	88	0	0	0	0	140133	139613	25	90029	50010	30007	10002	40010	30118	10078	1245907	5333285	16119578	0	142097	0	142814	141273	131055	41	131291	81206	30264	10040	30487	60500	20242	30363	140320	140242	4	1	50021	10	9	10	40010	10000	10000	0	10	10004	2	1	10006	1	7	6323	10003	1	1	0	3140	3	87	5	5	139719	50000	0	0	6	10000	20000	50010	140051	140036	140036	140051	140051

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2d, v1.2d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0066

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	18	19	1e	1f	22	24	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70205	140070	1086	1	0	0	0	0	10	0	0	0	140048	139565	25	90100	50100	30003	10000	40100	30000	10000	1237096	5334101	16119069	0	140042	0	140066	140055	130731	3	131178	80100	30200	10000	30000	60200	20000	30000	140063	140061	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	0	1	0	0	3210	1	80	1	1	139735	50000	6	6	0	10000	20000	50100	140064	140105	140067	140064	140064
70204	140055	1086	0	0	0	0	0	1	0	0	0	140048	139608	25	90103	50100	30003	10000	40100	30000	10000	1237096	5333245	16116353	0	140039	0	140063	140063	130739	3	131158	80100	30200	10000	30000	60200	20000	30000	140055	140055	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3289	1	80	1	1	139735	50000	6	7	9	10000	20000	50100	140075	140064	140068	140056	140068
70204	140063	1125	0	0	1	0	0	0	0	1	0	140051	139715	25	90103	50100	30003	10000	40100	30000	10000	1237096	5333551	16117885	0	140039	0	140063	140063	130739	3	131207	80437	30200	10000	30000	60200	20000	30000	140065	140066	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	0	10000	0	0	0	10000	1	1	0	0	3210	1	121	1	1	140051	50000	9	9	9	10000	20000	50100	140056	140064	140064	140064	140064
70204	140066	1049	0	0	0	0	33	1611	0	0	0	140051	139565	25	90103	50100	30003	10000	40100	30000	10000	1237096	5332803	16116353	0	140111	0	140063	140063	130739	3	131207	80100	30200	10000	30000	60200	20000	30000	140122	140066	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10001	0	1	10000	0	0	3	10000	1	1	0	0	3210	1	121	1	1	139735	50000	9	6	6	10000	20000	50100	140064	140056	140064	140067	140056
70204	140063	1049	0	0	0	0	0	1	0	0	0	140040	139565	25	90103	50100	30000	10000	40100	30000	10000	1244902	5333803	16127390	0	140039	0	140404	140063	130731	3	131158	80100	30200	10000	30000	60200	20000	30000	140055	140066	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	1	80	1	1	139735	50000	9	9	9	10000	20000	50100	140064	140064	140064	140064	140064
70204	140063	1049	0	0	0	0	0	1	0	0	0	140051	139600	25	90103	50100	30003	10000	40100	30000	10000	1237771	5330764	16116236	0	140039	0	140063	140063	130739	3	131158	80100	30200	10000	30000	60200	20000	30000	140063	140066	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	0	0	0	10000	1	1	0	0	3210	1	80	1	1	139735	50000	9	6	9	10000	20000	50100	140066	140111	140068	140070	140067
70204	140063	1086	0	0	0	0	0	22	0	0	0	140051	139598	25	90103	50100	30003	10000	40100	30000	10000	1237114	5333340	16116470	0	140039	0	140063	140063	130731	3	131210	80100	30200	10000	30000	60200	20000	30000	140064	140070	1	1	50201	100	99	0	100	40100	10000	10000	1	100	10000	0	1	10000	0	0	3	10000	1	1	0	0	3210	1	80	1	1	139735	50000	9	6	0	10000	20000	50100	140064	140067	140064	140067	140067
70204	140066	1085	0	0	0	0	0	6	0	0	0	140048	139565	25	90103	50100	30003	10000	40100	30000	10000	1237222	5333517	16116863	0	140039	0	140063	140055	130739	3	131207	80100	30200	10000	30000	60200	20000	30000	140063	140061	1	1	50201	100	99	0	100	40100	10000	10000	4	100	10000	0	1	10000	1	0	30	10000	1	1	0	0	3210	1	80	1	1	139735	50000	9	9	9	10000	20000	50100	140068	140056	140064	140064	140064
70204	140063	1086	0	0	0	0	0	13	0	0	0	140228	139565	25	90103	50100	30003	10000	40100	30000	10000	1237096	5334222	16118125	0	140041	0	140063	140109	130748	3	131207	80100	30200	10000	30000	60928	20000	30000	140066	140063	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	2	0	0	10000	0	1	0	0	3210	1	121	1	1	139735	50000	9	6	9	10000	20000	50100	140067	140067	140067	140064	140056
70204	140063	1085	0	0	0	0	0	1	0	0	0	140049	139567	25	90103	50117	30000	10000	40100	30000	10000	1237699	5337178	16116236	0	140039	0	140063	140063	130766	3	131158	80100	30200	10000	30120	60200	20000	30000	140063	140066	1	1	50201	100	99	0	100	40100	10000	10000	0	100	10000	0	1	10000	1	2	0	10000	1	1	0	0	3210	1	121	1	1	139803	50000	9	6	9	10000	20000	50100	140064	140064	140064	140064	140067

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0052

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	24	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
70025	140053	1086	0	0	0	1	1	0	0	1	0	0	0	0	140021	139658	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333591	16115517	140030	0	140060	140054	130753	3	131213	80010	30020	10000	30000	60020	20000	30000	140058	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	1	0	0	3140	0	2	87	3	2	139730	50000	13	0	13	10000	20000	50010	140059	140059	140059	140037	140510
70024	140036	1085	0	0	0	1	1	0	0	1	0	0	0	0	140534	139884	167	90092	50058	30025	10006	40719	30596	10196	1258398	5344866	16155844	140034	3	140447	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140058	140058	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	6	10000	1	1	0	0	3140	0	2	87	2	3	139730	50000	13	13	10	10000	20000	50010	140059	140059	140061	140059	140055
70024	140054	1086	0	0	0	1	1	0	0	1	0	0	0	0	140039	139655	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333591	16115517	140014	0	140058	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140036	140058	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	2	87	3	3	139730	50000	13	10	13	10000	20000	50010	140059	140059	140059	140061	140059
70024	140054	1086	0	0	0	0	0	0	0	1	0	1	0	0	140021	139658	25	90013	50010	30003	10000	40010	30000	10000	1245979	5333591	16115708	140034	0	140058	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140058	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	3	87	3	3	139726	50000	10	13	13	10000	20000	50010	140059	140059	140059	140063	140059
70024	140036	1085	0	0	0	0	0	0	0	1	0	0	0	0	140021	139658	25	90013	50010	30000	10000	40010	30000	10000	1245979	5332745	16113460	140034	0	140058	140054	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140058	140058	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	0	10000	1	0	0	10000	1	1	0	0	3140	0	3	87	3	3	139731	50000	13	0	13	10000	20000	50010	140059	140059	140059	140060	140061
70024	140058	1086	0	0	0	0	0	0	0	1	0	0	0	0	140046	139659	25	90010	50010	30003	10000	40010	30000	10000	1245979	5333630	16115708	140034	0	140058	140058	130753	3	131217	80010	30020	10000	30000	60020	20000	30000	140058	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	2	0	10000	1	0	0	0	3140	0	3	87	3	3	139730	50000	13	10	13	10000	20000	50010	140062	140059	140059	140037	140038
70024	140058	1086	0	0	0	0	0	0	0	1	0	0	0	0	140043	139654	25	90013	50020	30003	10000	40010	30000	10000	1245979	5332745	16117756	140012	0	140037	140058	130735	3	131195	80010	30020	10040	30000	60020	20000	30000	140036	140058	1	1	50021	10	9	10	40010	10000	10000	1	10	10000	0	1	10000	1	0	6	10000	1	1	0	0	3140	0	3	87	3	3	139732	50000	0	13	10	10000	20000	50010	140059	140059	140061	140059	140059
70024	140058	1086	0	0	0	0	0	1	0	1	0	0	0	0	140046	139658	25	90010	50010	30003	10000	40010	30000	10000	1245979	5333708	16115517	140034	0	140058	140061	130760	3	131213	80010	30020	10000	30000	60020	20000	30000	140058	140058	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	1	0	0	10000	1	0	0	0	3140	0	3	87	2	3	139708	50000	13	13	0	10000	20000	50010	140059	140153	140059	140037	140059
70024	140054	1086	0	0	0	0	0	0	0	1	0	0	0	0	140043	139658	25	90013	50010	30003	10000	40010	30000	10039	1245979	5332745	16115517	140034	0	140054	140058	130757	3	131217	80010	30020	10000	30000	60020	20000	30000	140149	140054	1	1	50021	10	9	10	40010	10000	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	3140	0	3	102	3	3	139730	50000	0	0	14	10000	20000	50010	140059	140158	140500	140059	140158
70024	140244	1087	1	1	1	0	0	23	1	133	88	0	1	0	140217	139702	52	90055	50032	30011	10003	40298	30237	10039	1250782	5337252	16130541	140240	0	140252	140238	130816	27	131300	80313	30880	10780	33147	66612	22094	33166	142396	142164	23	1	50021	10	9	10	40010	10000	10000	0	10	10005	2	1	10004	0	2	9385	10003	1	1	0	0	3140	0	3	87	2	3	139730	50000	13	10	0	10000	20000	50010	140037	140037	140037	140037	140037

Test 4: throughput

Count: 8

Code:

  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8
  ld2r { v0.2d, v1.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	23	24	3a	3f	43	46	49	4e	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240205	80041	643	1	0	0	1	0	0	0	0	10	0	0	0	1	80026	1	0	6	1	2	25	320162	80100	160014	80000	80100	160000	80000	4408211	3758374	9826445	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	2	1	80201	100	99	100	100	80000	80000	0	100	80008	8	23	80026	0	0	6	80018	6	1	7	18	0	1	5110	1	16	0	1	1	80038	1	80000	0	0	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	1	1	0	0	0	0	45	0	1	0	0	80026	1	6	6	1	4	25	320140	80100	160032	80000	80100	160000	80000	4408215	3758374	9826363	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	1	100	80008	7	23	80010	1	1	25	80019	6	1	26	0	7	0	5110	2	16	0	1	1	80038	0	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	0	0	0	0	0	6	0	0	0	1	80026	0	6	6	1	0	25	320114	80100	160062	80000	80100	160000	80000	4408215	3758363	9826353	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	0	18	80027	0	0	7	80014	6	1	10	18	6	0	5110	1	16	0	2	3	80038	1	80000	9	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	0	1	1	1	0	0	22	0	0	0	0	80026	1	6	6	0	1	25	320162	80100	160062	80000	80100	160000	80000	4408211	3758372	9826361	0	80022	80041	80041	49924	478	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	8	23	80025	1	0	17	80019	6	1	24	23	7	0	5110	1	16	0	1	1	80038	0	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	0	0	0	0	0	37	0	0	0	0	80026	1	6	6	0	5	25	320162	80100	160064	80000	80100	160000	80000	4408215	3758374	9826360	0	80022	80041	80182	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80008	7	23	80007	0	0	29	80018	6	1	7	0	6	0	5110	1	16	0	1	1	80038	1	80102	0	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	642	1	1	0	0	1	0	0	0	7	0	0	0	0	80026	1	6	6	1	4	25	320100	80100	160032	80000	80100	160000	80000	4408203	3758371	9826363	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80008	8	23	80000	0	0	29	80019	6	1	25	23	7	0	5110	1	16	0	1	1	80038	1	80000	12	0	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	0	0	0	0	0	0	0	0	19	0	0	0	0	80026	1	6	0	1	1	25	320162	80100	160062	80000	80100	160000	80000	4408206	3758361	9826353	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80006	0	14	80025	0	0	25	80014	6	1	10	18	7	0	5110	1	16	0	1	1	80038	1	80000	9	6	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	642	1	0	2	0	0	0	0	0	23	0	0	0	1	80026	1	6	6	0	3	25	320162	80100	160062	80000	80237	160785	80133	4414558	3758378	9825493	0	80022	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80000	8	23	80026	0	0	12	80019	6	1	25	23	7	0	5110	1	16	0	1	1	80038	0	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	642	1	0	0	0	0	0	0	0	32	0	0	0	0	80026	0	6	6	1	3	25	320164	80207	160062	80000	80100	160000	80000	4408202	3758373	9826361	0	80022	80041	80041	49924	33	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	23	80026	1	0	6	80019	6	1	25	23	7	3	5110	1	16	0	1	1	80038	1	80000	9	10	80000	160000	80100	80042	80042	80042	80042	80042
240204	80041	643	1	0	0	0	1	1	0	0	32	0	0	0	0	80026	1	6	6	1	3	25	320114	80100	160062	80000	80100	160000	80000	4408209	3758362	9826363	0	80127	80041	80041	49924	0	3	49999	320100	200	80000	160000	200	160000	160000	80041	80041	1	1	80201	100	99	100	100	80000	80000	0	100	80007	7	23	80117	0	0	25	80018	0	1	26	23	6	0	5110	1	16	0	1	1	80038	1	80000	9	9	80000	160000	80100	80042	80042	80042	80042	80042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd load (98)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
240025	80041	620	0	0	0	0	0	0	0	0	31	0	0	0	0	80026	1	6	6	0	25	320048	80010	160038	80000	80010	160000	80000	4407696	3758361	9825509	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	0	80014	0	12	80013	6	1	0	18	0	5020	19	16	19	18	80038	0	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	0	0	1	1	0	0	19	0	0	0	0	80026	1	6	6	0	25	320048	80010	160040	80000	80010	160000	80000	4407696	3758360	9825505	0	80022	80164	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80014	3	17	80014	6	1	10	14	0	5020	20	15	18	10	80038	1	80000	9	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	1	1	0	1	1	0	0	15	0	0	0	0	80026	1	6	6	0	25	320042	80010	160032	80000	80010	160000	80000	4407696	3758372	9825509	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80000	0	14	80013	6	1	0	14	0	5020	19	15	11	20	80038	1	80000	0	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	0	0	0	0	32	0	0	0	0	80026	1	6	6	8	25	320050	80010	160040	80000	80010	160000	80000	4407696	3758360	9825493	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80014	0	14	80014	6	1	10	18	0	5039	11	15	19	12	80038	1	80102	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	623	0	0	0	0	0	0	0	0	24	0	0	0	0	80026	1	6	6	0	25	320048	80010	160040	80000	80010	160000	80000	4407696	3758372	9825493	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80014	0	17	80014	6	1	9	14	0	5020	11	16	18	12	80038	0	80000	9	0	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	0	0	0	0	15	0	0	0	0	80026	1	6	6	0	25	320048	80010	160040	80000	80010	160000	80000	4407687	3758361	9825511	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	0	80014	0	14	80014	6	1	10	14	0	5020	12	15	19	13	80038	0	80000	2	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	0	0	0	0	20	0	0	0	0	80026	1	6	6	4	25	320050	80010	160038	80000	80010	160000	80000	4407696	3758372	9825509	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	0	80013	0	0	80014	6	1	10	14	0	5020	20	15	13	22	80038	0	80000	9	6	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	621	0	0	0	0	0	0	0	0	20	0	0	0	0	80026	1	6	6	0	25	320050	80010	160038	80000	80010	160000	80000	4407696	3758375	9825509	0	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	0	0	80013	0	16	80014	6	1	9	18	0	5020	20	15	20	12	80038	1	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	0	0	0	0	0	0	6	0	0	0	0	80026	1	6	0	4	25	320050	80010	160216	80000	80010	160000	80000	4407696	3758361	9825511	1	80022	80041	80041	49947	0	3	50022	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	14	0	80013	0	13	80000	6	1	14	14	0	5020	20	15	22	18	80038	1	80000	9	9	80000	160000	80010	80042	80042	80042	80042	80042
240024	80041	620	0	0	0	0	0	0	0	0	32	0	0	0	0	80026	1	6	6	0	25	320050	80010	160038	80000	80010	160000	80000	4407665	3758371	9825509	0	80022	80041	80041	49947	0	3	50101	320010	20	80000	160000	20	160000	160000	80041	80041	1	1	80021	10	9	10	10	80000	80000	0	10	80000	0	18	0	80101	1	14	80014	6	1	9	14	0	5020	17	25	10	20	80038	1	80000	11	6	80000	160000	80010	80042	80042	80042	80042	80042

LD2R (post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations