Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD2R (post-index, 2S)

Test 1: uops

Code:

  ld2r { v0.2s, v1.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.004

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 2.004

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e181e22233a3f464951schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd load (98)inst ldst (9b)9dl1d tlb access (a0)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)cfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
63005294122282841103004661289091017407400610002006100010002000100050005000238008226962959729478310400010002000200020002936229417116100110001000010002100000100021011289790226868310845520703310638111755622841310001653313362145021000200010002933229298293892926629350
6300429385219085000200454828797001721740041000200410001000200010005000500023893222717290952931031040001000200020002000291772914511610011000100011000010000150100001001277092126888309045520605306538141757612842510001649713417145291000200010002929629264293282933529296
6300429252220067000000455728882001724940001000200010001000200010005000500023870222710291492930731040001000200020002000291902917611610011000100001000210000010000020128759138689230751592072930453813859622840010001626113536144541000200010002926429300293182933829237
63004292462200481000004613287710017186400410002000100010002000100050005000238153227042914929333310400010002000200020002923129224116100110001000010002100100100000001285890516851307736220616304638171363622842310001641713440146121000200010002927229220292722929429284
63004293692190670000004568288350017208400410002000100010002000100050005000238851227632911829325310400010002000200020002916129114116100110001000010002100000100020301282593016873308076420730307038121266622844910001640413333144711000200010002927429296293202934429301
63004293062200760002004677288640017224400010002004100010002000100050005000238625227822919729321310400010002000200020002918729191116100110001000010002100100100000201284493466878310646320648306838141462622835810001631113513145981000200010002925029291293612940329284
63004293222200690103104594288850017199400410002004100010002000100050005000238654227162912229260310400010002000200020002921029141116100110001000010000100000100020001279792916924304026320624313038121565592842310001642513361143741000200010002935329321293032924129195
63004293462200350002004690288900017232400410002004100010002000100050005000238643227902910029343310400010002000200020002919929146116100110001000110000100000100000001285490356876303646620619307038201060592842810001647613457146881000200010002934829313292772921529292
63004292702200760003004537288860017221400410002000100010002000100050005000238061226922911129341310400010002000200020002918629163116100110001000010002100000100020001313693056864309646120636306338161461612841510001636913309144861000200010002936729285293902930629394
63004293082190690000104568288200017225400010002004100010002000100050005000238140227462913829290310400010002000200020002925829226116100110001000010002100000100030201322191306895309046520693306038151462542840010001631713281144461000200010002930329373292342934929358

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2s, v1.2s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)c2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
702051401451087010000023000014014313978582901795014130018100024052730355100791247795533794516111311014022414015314034013077532413228486698304471008230242606882016030246140246140233315020110099100401001000010000010010003411000300063761000311100321021212313972550000101013100002000050100140055140036140058140052140055
70204140052108500000000010014003913959625901035010030003100004010030000100001236903533151016114560014002714005414003513072731311578010030200100003000060200200003000014005414005111502011009910040100100001000001001000001100000003100000010032102121221397215000001013100002000050100140036140055140036140036140055
7020414005110850000000120000140036139596259010350100300031000040100300001003912369725331357161195220140084140035140054130730313116080100302001000030000602002008230000140056140051215020110099100401001000010000010010000011000000031000010100321021212213972450000131010100002000050100140052140055140055140056140036
702041400541085000000031000014003913959625901035010030003100004010030000100001236990533158816112967014011614005414005513073031311578010030200100403000060200202443000014005514005111502011009910040100100001000001001000001100000000100001010032102121221397245000010013100002000050100140055140055140055140055140056
70204140035108600000001000114003913959625901035010030003100004010030000100001236990533147116114560014002714005414005713073031311388010030200100003000060200200003000014005114005411502011009910040100100001000001001000001100000000100001010032102121221397245000010013100002000050100140056140055140052140055140055
7020414005110860001100130000140020139599259010350100300031000040100300001000012369635331357161145600140030140054140054130730313115780100302001000030000602002000030000140054140055115020110099100401001000010000010010000011000001031000010100321021212213972150000131013100002000050100140055140055140054140052140055
702041400561086000110010000140039139593259010350100300031000040100300001000012369635331357161145601140030140054140054130712313115780100302001000030000602002000030000140054140051115020110099100401001000010000010010000011000001001000010000321021212213970550000131013100002000050100140057140064140058140055140055
7020414005410850001000130000140020139596259010350100300031000040100300001000012369905331471161145600140030140056140054130730313115780100302001000030000602002000030000140054140051115020110099100401001000010000010010000011000001001000010100321021212213972150000101010100002000050100140052140052140052140052140055
702041400521086000100057717600014022913969911090158501383001310004426683317911025131160253779461625408401401651402411403591307743013126780707305671004030363606942016430482140235140293415020110099100401001000010000010010004011000600297001000400100321021212213972450000101313100002000050100140055140055140052140055140055
702041400541085000010010000140039139683569015150141300001000040250300001000012369035330746161145600140011140054140051130730313113880100302001000030000602002000030000140051140054115020110099100401001000010000010010000011000001001000010100321031042213972550000131010100002000050100140055140055140055140055140055

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0056

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
70025140047104900000000010100014004113965625900165001030006100004001030000100001246762533351716115415140032014005614005613072731312128001030020100003000060020200003000014005014003511500211091040010100001000001010000211000000001000010100000314028702213972850000699100002000050010140042140042140048140051140048
700241400501086100000000201001140026139641259001350010300061000040010300001000012459615333517161154151400170140056140056130727313121280010300201000030000600202000030000140053140053115002110910400101000010000010100021110001000311000001010000314038702213972250000969100002000050010140048140048140053140054140051
70024140059108600000000020100014004113965625900135001030003100024001030000100001245907533328516115763140033014005014005013074931312518001030020100003000060020200003000014004714004711500211091040010100001000001010000111000002001000010100000314038702313970750000969100002000050010140057140057140051140051140054
700241400501085100000000130100014002013965025900165001030003100004001030000100001245961533328516115013140026014005014005613073431312068001030020100003000060020200003000014004114004111500211091040010100001000001010000011000300011000011100000314028702213972250000960100002000050010140036140054140051140051140048
70024140056108600000000020100014004113965325900165001030006100014001030000100001246762533355616115415140032014005614005613072731312698001030020100003000060020200803000014005614005311500211091040010100001000001010001111000000031000010100000314028702213970750000666100002000050010140048140048140057140057140042
70024140050108600000000010100014003813965625900135001030007100004001030000100001245961533351716115724140020014005714005413074931312158001030020100003012260020200003000014005014004711500211091040010100001000001010001111000100261000010001000314038703213972850000999100002000050010140054140054140054140058140042
70024140041108610101000070100014004713964125900165001030003100004001030000100001245961533351716115415140088014005614005613075531312128001030020100003000060020200003000014005314004111500211091040010100001000011010001101000100011000011110000314028702213972850000969100002000050010140060140057140057140057140057
70024140056108510001000010100014004113965625900165001030006100004001030000100001245961533351716115415140032314005614005613075531312128001030020100003000060020200003000014005614005311500211091040010100001000001010002111000000101000011111000314028702213972850000909100002000050010140042140051140051140091140054
70024140047108500001000010100014012013966425900135001030003100004001030000100001245916533479816114399140026014005614005613074931312868001030020100003000060020200003000014005614005011500211091040010100001000001010002011000201011000000110000314038703213971950000990100002000050010140051140051140051140051140036
70024140051108700000000010100014003513965025900135001030006100004001030000100001245907533328516114779140026014005014005013075531312068001030020100003000060020200003000014005014004711500211091040010100001000001010000011000002001000011110000314029103313972850000969100002000050010140054140054140042140054140054

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld2r { v0.2s, v1.2s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0065

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5l1d cache miss ld nonspec (bf)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
70205142046110501010223971761001402491397335390100501323000710001402413023610000124270453340151611498001400311401711401601307571713123880401304431000030118604442016430000140169140187115020110099100401001000010000010010000011000010010000000321011211113974550000131014100002000050100140056140056140056140076140076
702041400651086000110000010140485139866191902065019030035100074096230709102361260586534663616147394014003314007514007513075117131177804113020010000300006020020000300001400751400651150201100991004010010000100000100100000110000000100001103210112111139746500000010100002000050100140076140066140056140056140066
70204140065108500001000001014006113959725901005010030000100004010030000100001237179533153816116123014005214007514005513074131311688010030200100003000060200200003000014007914006511502011009910040100100001000011001000000100000031000011132101121111397455000013130100002000050100140076140076140056140056140076
70204140075108600000003400001400601396072590103501003000310000401003000010000123717953322621611612301400511400751400751307513131181801003020010000300006020020000300001400551400651150201100991004010010000100001100100000110000103100000103210112111139725500000011100002000050100140076140072140066140076140076
70204140075108501001001001014006013961725901035010030000100004010030000100001237092533226216114980014008414007514005513075531311788010030200100003000060200200003000014005614005511502011009910040100100001000011001000000100001001000000032101121111397355000013100100002000050100140056140076140066140066140076
70204140075108500010001000014006313960725901035010030003100004010030000100001237083533225916116123014003114005514005713074731311588010030200100003000060200200003000014007514005511502011009910040100100001000011001000001100000001000010032101121111397465000001010100002000050100140066140056140056140061140076
7020414006510860001100000001400401396172590103501003000010000401003000010000123708353314991611498001400511400771400551307313131178801003020010000300006020020000300001400751400661150201100991004010010000100000100100000110000000100001003210112111139833500000013100002000050100140076140076140076140075140079
7020414007510860001000130000140060139597259010050100300031000040100300001000012371795332262161149800140055140075140076130731313116880100302001000030000602002000030000140055140065115020110099100401001000010000110010000001000010310000110327711251113997550026131310100002000050100140353140157140311140252142592
7020414247011061100022529176010140244139671110901335014030012100024053430238100791249430533373716119077014005414005514005513073131311788010030200100003000060200200003000014007514006511502011009910040100100001000011001000000100001001000001032101121111397455000013100100002000050100140158140076140057140076140076
702041400551086010100000000140040139607259010350100300031000040100301421000012371795332382161168410140051140075140074130751291312988070530446100403000060200200003000014007514005711502011009910040100100001000001001000001100002001000010032101121111397255000010013100002000050100140076140066140076140068140076

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 11.0054

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)0e0f18191e1f2223243a3f4d51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cdcfd0d2d5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)eaebec? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
700251400571086010110111113417610011401741398451079006450042300141000440155304721011912487775339198161320090014017501403421402461308392913136080610305041012130245607502008030237140357140224315002110910400101000010000010100034110003006386100021111000321100410904413973250000101010100002000050010140062140045140045140045140062
70024140063108511101000002300000140045139644259001350010300061000040010300001000012459975331725161161770014003601400631400601307593131219800103002010000300006002020000300001400441400602150021109104001010000100001101000131100010011000011110003142004910441397325000010010100002000050010140045140061140061140045140045
70024140044108511101000002001001400461396602590016500103000610000400103014110000124601553337481611024705140020014004414006013073031312228001030020100003000060020200003000014006314006011500211091040010100001000011010001211000101110000010110031420048704413971650000101010100002000050010140061140045140061140045140045
700241400441085111010000020010014003913965825900135001030003100004001030000100001245979533274516115517001400120140036140036130757313121380010300201000030000600202000030000140054140054115002110910400101000010000110100000110000000100001000000314200587044139726500000100100002000050010140055140059140038140059140059
7002414005410860100100000100000140024139636259001350010300031000040010300001000012459435333440161155170014003001400361400361307573131195800103002010000300006002020000300001400541400361150021109104001010000100001101000001100000001000010100013142005870541397265000001310100002000050010140055140037140037140055140055
70024140036108601001000001001001400211396362590010500103000310000400103000010000124585653327451611346000140030014005414003613075331312138001030020100003000060020200003000014005414005411500211091040010100001000011010001001000010010000100000031420048705513972650000000100002000050010140037140055140037140055140055
7002414003610860100101100000100140039139636259001050010300031000040010300001000012459435333440161134600014003001400361400541307353131213800103002010000300006002020000300001400361400561150021109104001010000100001101000000100000031000010100003142003870441397085000010100100002000050010140040140055140056140055140056
700241400361085010010110010000014003913965425900135001030003100004001030000100001245856533344016113460001400300140058140054130753313121780010300201000030000600202000030000140058140036115002110910400101000010000010100000110000000100000000000314200487055139730500000100100002000050010140038140059140059140059140037
7002414003610850100101123631176010014026514076875190389502463009310025435433293310965130723253741861621528700140264014022614023313081029131289806143038510080304886050420080303691401481402453150021109104001010000100000101000341100030096901000310100003142003870451397265000001010100002000050010140059140055140037140055140059
700241400541085010010000028000001400211396552590010500103000310000400103000010000124594353327451611551700140030014005414005413075531312138001030020100003000060020200003000014005414005411500211091040010100001000001010000011000000010000100000031660048704313972650000101010100002000050010140059140059140040140059140055

Test 4: throughput

Count: 8

Code:

  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  ld2r { v0.2s, v1.2s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk data (08)l2 tlb miss data (0b)0e0f18191e1f23243f4346494f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6067696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9d9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)a5ld unit uop (a6)l1d cache writeback (a8)acafb5b6bbl1d cache miss ld nonspec (bf)l1d tlb miss nonspec (c1)c2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
24020580041621001000031000800261060253201388010016003880000801001600008000044082153758372982638200800220800418004149924034999932010020080000160000200160000160000800418004111802011009910010080000800000100800008140800130148000001023705110011611800381800009080000160000801008004280042801668004280042
240204800416200001100320008002616742532014080100160040800008010016000080000440821537583759826353008002208004180041499240349999320100200800001600002001600001600008004180041118020110099100100800008000001008000001408000801480013602514005110011611800380800009680000160000801008004280042800428004280042
24020480041621000000020000800261000253201628010016000080000801001600008000044082043758376983547500800220800418004149924034999932010020080000160000200160000160000800418004111802011009910010080000800000100800008140800090258000060923005110011611800381800009980000160000801008004280042800428004280042
240204800416210000000440008002616602532014080100160040800008010016000080000440821537583719825970018002208031880041500060349999320100200800001600002001600001600008004180041118020110099100100800008000001008000001408011621680014613118005110012511800380800009680000160000801008004280042800428004280042
24020480041643000000000108002600002532014080100160030800008010016000080000440821537583819826363008002208004180041499240349999320100200800001600002001600001600008004180041118020110099100100800008000001008000071408000002980102611023005110011611801431800000680000160000801008004280042800428018380042
240204800416430000000190008002616602532014080100160040800008010016000080135440821537583759826353008002208004180041499240349999320100200800001600002001600001600008004180041118020110099100100800008000001008008901408002501380010612518005110011611800381800000680000160000801008004280168800428004280042
24020480041643001000120000800260664253201648010016003880000801001600008000044082153758368982655900801450800418004149924034999932010020080000160000200160000160000800418004111802011009910010080000800000100800008140800140108001461923005110011611800380800009980000160000801008004280042800428004280042
240204800416430000000200008002616606832014080100160040800008010016000080000440821537583619825847008012908004180041499240349999320100200800001600002001602721600008004180041118020110099100100800008000001008000001408002501380089612414005110011611800381800009980000160000801008004280042800428018180042
240204800416430010000200008002606002532016280100160040800008010016000080000441041137583729825507008002208004180041499530349999320100200800001600002001600001600008004180041118020110099100100800008000001008000010140800001258001401024005110021611800381800009680000160000801008004280042800428004280042
240204800416420001100200108002616602532010080100160040800008010016000080000440821537583759826355008002208004180041499240349999320100200801361600002001600001600008004180041118020110099100100800008000001008000001408002611080014011014005110001610800380800009680000160000801008004280042800428004280042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0e0f18191e1f2223243a3f4346494e4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd load (98)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss ld (a3)ld unit uop (a6)l1d cache writeback (a8)a9acafb5b6bbl1d cache miss ld nonspec (bf)c2cfd5map dispatch bubble (d6)ddfetch restart (de)e0e7? int output thing (e9)eaeb? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
240025800416201000000170000080026160002532001080010160040800008001016000080000441218937583709825511080022800418004149947035002132001020800001600002016000016000080041800411180021109101080000800001080000014800141016800146113180502081557800380800009680000160000800108004280042800428004280042
24002480041620000000020010008002616601253200508001016004080000800101600008000044076963758375982549308002280041803254997403500213200102080000160265201600001600008004180041118002110910108000080000108000000800140014800006011180502051685800381800009680000160000800108004280042800428004280042
24002480041621000111000100080026166002532004880010160040800008001016000080000440769637583759825511080022800418004149947035002132001020800001602712016000016000080183800411180021109101080000800001080000014800100014801026110180502051585801430800009680000160000800108004280042800428004280042
240024800416200100100200100080026166002532004880010160040800008001016000080000440769637618759825504080022800418004149947035002132001020800001600002016000016000080041800411180021109101080000800001080000018800141014800136110180502071599800381800006080000160000800108004280042800428004280042
24002480183621000000019000008002606600253200488001016003880000800101600008000044076883758367982549308002280041800414994703500213200102080000160000201600001600008004180041118002110910108000080000108000001480101101380014611400502072688800381800006980000160000800108004280189800428004280042
2400248004162100000001630000080026166002532005080010160000800008001016000080000440769137583749834388080022800418004149947035002232001020800001600002016000016000080041800411180021109101080000800001080000018800141014800130114180502051588800381800009680000160000800108004280042800428004280042
240024800416200000000200100080026166012532040880010160038800008001016000080000440769137583769825493080022800418004149947035002232001020800001600002016000016026680041800411180021109101080000800001080000018800140016800146110180502081548800381800009680000160000800108004280042800428004280042
24002480041620010000020010008002616600253200488001016004080000800101600008013344076843758375983522008002280041800414994703500223200102080000160000201600001600008004180041118002110910108000080000108000001480010101380014019180502041587800380800969680000160000800108004280042800428004280042
240024801936210000000320000080026066062532005080104160040800008001016000080000440769637583759825511180022800418004149947035002132001020800001600002016000016000080041800412180021109101080000800001080000018800140017800136114180502081558800381800969680000160000800108004280042800428004280042
24002480181620000000020000008002616600253200428001016004080000800101600008000044076963758361982569708002280041800414994703500213200102080133160000201600001600008004180041118002110910108000080000108000001480009001480014611100502081658801450800000980000160000800108004280042800428018380042